JP6803042B2 - 貫通電極及びその製造方法、並びに半導体装置及びその製造方法 - Google Patents
貫通電極及びその製造方法、並びに半導体装置及びその製造方法 Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
図2(a)及び(b)は、第1実施形態に係る貫通電極11の構造の一例の詳細を示す断面図である。図2(b)は半導体基板の主面に垂直な断面図であり、図2(a)は図2(b)のA−A線における断面図に相当する。半導体基板10の一方面側には配線21及び絶縁層22を複数含む配線層20が形成されており、配線層20及び半導体基板10は支持基板30上に支持されている。半導体基板10には、配線層20の配線21に達する、シリコン貫通電極(TSV)とすることができる貫通電極11が形成されている。貫通電極11は、半導体基板10に形成された導電層12と、導電層12及び半導体基板10の間であって導電層12及び半導体基板10に接して形成された側壁絶縁膜13とを有する。貫通電極11上には金属材料からなる配線15が形成されている。側壁絶縁膜13として、化学式(1)で示されるパリレン−HT(登録商標)が使用される。
例えば、側壁絶縁膜13を低温、例えば室温(25℃)で形成した場合であっても、半導体基板10に対する側壁絶縁膜13の接着性を確保することができる。側壁絶縁膜13を室温で形成できることから、貫通電極11に起因する半導体基板10への応力の発生を抑制することができる。
また、パリレン−HTのヤング率は酸化シリコンと比べて低いことから、応力緩和層として機能し、半導体基板に形成される半導体デバイスの信頼性を向上させることができる。
また、パリレン−HT膜を低温、例えば室温で形成した場合であっても、ピンホール無く、均一にスルーホールを被覆することができ、高アスペクト比の貫通電極11の形成にも適用可能である。
また、パリレン−HT膜の誘電率が低いことから、容量結合を低減でき、信号遅延や、隣接する配線間でのクロストークを低減することができる。
さらに、パリレン−HT膜は、酸化シリコンと比べて銅拡散係数が低く、かつリーク電流を抑制できることから、バリア層を省略することができる。このため、バリア層の形成のための熱プロセスにより、半導体基板10へ応力が発生することを抑制することができる。また、製造工程を削減でき、コスト低減にもつながる。
第1実施形態では側壁絶縁膜13を形成した後に導電層12を形成したが、第2実施形態では導電層12を形成した後に側壁絶縁膜13を形成するものである。図4を参照して第2実施形態に係る貫通電極の製造方法を説明する。
図5(a)及び(b)は、第3実施形態に係る貫通電極11の構造の一例の詳細を示す断面図である。図5(b)は半導体基板の主面に垂直な断面図であり、図5(a)は図5(b)のA−A線における断面図に相当する。第1及び第2実施形態と異なり、第3実施形態では、導電層12と側壁絶縁膜13との間に半導体基板10と同じ材料、すなわちシリコンからなる筒形状の半導体層14が設けられている。貫通電極11は、導電層12、側壁絶縁膜13、半導体層14により構成される。
第3実施形態では側壁絶縁膜13を形成した後に導電層12を形成したが、第4実施形態では導電層12を形成した後に側壁絶縁膜13を形成するものである。図7を参照して第4実施形態に係る貫通電極の製造方法を説明する。
次に、本実施形態の貫通電極の効果について、実施例の結果を参照して説明する。
Claims (4)
- 半導体基板の一方面側から前記半導体基板にスルーホールを形成する工程と、
前記スルーホールに導電性材料を埋め込み、導電層を形成する工程と、
前記一方面側から前記半導体基板に開口を形成する工程と、
前記開口に下記化学式(1)で示される絶縁材料を埋め込み、側壁絶縁膜を形成する工程と、
を有し、
前記開口を形成する工程において、前記導電層と前記開口との間に前記半導体基板の一部からなる筒形状の半導体層を残すように前記開口を形成する、
貫通電極の製造方法。
- 前記導電性材料を埋め込む工程において、銅または半田を埋め込む、
請求項1に記載の貫通電極の製造方法。 - 前記絶縁材料を埋め込む工程において、室温で前記絶縁材料を埋め込む、
請求項1又は2に記載の貫通電極の製造方法。 - 請求項1〜3のいずれかに記載の貫通電極の製造方法を含む、半導体装置の製造方法。
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US10290584B2 (en) | 2017-05-31 | 2019-05-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conductive vias in semiconductor packages and methods of forming same |
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US6908856B2 (en) * | 2003-04-03 | 2005-06-21 | Interuniversitair Microelektronica Centrum (Imec) | Method for producing electrical through hole interconnects and devices made thereof |
JP2009124087A (ja) * | 2007-11-19 | 2009-06-04 | Oki Semiconductor Co Ltd | 半導体装置の製造方法 |
JP2009181981A (ja) * | 2008-01-29 | 2009-08-13 | Renesas Technology Corp | 半導体装置の製造方法および半導体装置 |
TWI443790B (zh) * | 2008-05-21 | 2014-07-01 | Xintec Inc | 電子元件封裝體及其製作方法 |
US20110207323A1 (en) * | 2010-02-25 | 2011-08-25 | Robert Ditizio | Method of forming and patterning conformal insulation layer in vias and etched structures |
US8659152B2 (en) * | 2010-09-15 | 2014-02-25 | Osamu Fujita | Semiconductor device |
US8349735B2 (en) * | 2010-09-22 | 2013-01-08 | Stats Chippac, Ltd. | Semiconductor device and method of forming conductive TSV with insulating annular ring |
US9054162B2 (en) * | 2010-11-22 | 2015-06-09 | Andreas Fischer | Method and an apparatus for forming electrically conductive vias in a substrate, an automated robot-based manufacturing system, a component comprising a substrate with via holes, and an interposer device |
JP2012231096A (ja) * | 2011-04-27 | 2012-11-22 | Elpida Memory Inc | 半導体装置及びその製造方法 |
JP2013115382A (ja) * | 2011-11-30 | 2013-06-10 | Elpida Memory Inc | 半導体装置及びその製造方法 |
WO2014064755A1 (ja) * | 2012-10-22 | 2014-05-01 | 富士通株式会社 | 半導体装置、半導体装置の製造方法及び熱電発電電子機器 |
US9646917B2 (en) * | 2014-05-29 | 2017-05-09 | Invensas Corporation | Low CTE component with wire bond interconnects |
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2016
- 2016-08-30 US US15/251,470 patent/US9818645B2/en not_active Expired - Fee Related
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- 2017-01-05 JP JP2017000665A patent/JP6803042B2/ja active Active
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US9818645B2 (en) | 2017-11-14 |
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