JP6789945B2 - クロストーク低減のためのグランドビアのクラスタ化 - Google Patents
クロストーク低減のためのグランドビアのクラスタ化 Download PDFInfo
- Publication number
- JP6789945B2 JP6789945B2 JP2017530112A JP2017530112A JP6789945B2 JP 6789945 B2 JP6789945 B2 JP 6789945B2 JP 2017530112 A JP2017530112 A JP 2017530112A JP 2017530112 A JP2017530112 A JP 2017530112A JP 6789945 B2 JP6789945 B2 JP 6789945B2
- Authority
- JP
- Japan
- Prior art keywords
- package substrate
- ground
- package
- vias
- interconnect structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Geometry (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/575,956 | 2014-12-18 | ||
| US14/575,956 US9230900B1 (en) | 2014-12-18 | 2014-12-18 | Ground via clustering for crosstalk mitigation |
| US14/943,880 | 2015-11-17 | ||
| US14/943,880 US9515017B2 (en) | 2014-12-18 | 2015-11-17 | Ground via clustering for crosstalk mitigation |
| PCT/US2015/063822 WO2016099936A1 (en) | 2014-12-18 | 2015-12-03 | Ground via clustering for crosstalk mitigation |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2017539090A JP2017539090A (ja) | 2017-12-28 |
| JP2017539090A5 JP2017539090A5 (enExample) | 2018-12-27 |
| JP6789945B2 true JP6789945B2 (ja) | 2020-11-25 |
Family
ID=56127342
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2017530112A Active JP6789945B2 (ja) | 2014-12-18 | 2015-12-03 | クロストーク低減のためのグランドビアのクラスタ化 |
Country Status (7)
| Country | Link |
|---|---|
| US (8) | US9515017B2 (enExample) |
| EP (5) | EP4220709B1 (enExample) |
| JP (1) | JP6789945B2 (enExample) |
| KR (3) | KR102669054B1 (enExample) |
| CN (4) | CN119560479A (enExample) |
| SG (1) | SG11201704038WA (enExample) |
| WO (1) | WO2016099936A1 (enExample) |
Families Citing this family (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9515017B2 (en) * | 2014-12-18 | 2016-12-06 | Intel Corporation | Ground via clustering for crosstalk mitigation |
| US9971970B1 (en) | 2015-04-27 | 2018-05-15 | Rigetti & Co, Inc. | Microwave integrated quantum circuits with VIAS and methods for making the same |
| US10327268B2 (en) * | 2015-09-25 | 2019-06-18 | Intel Corporation | Microelectronic package with wireless interconnect |
| US11277922B2 (en) | 2016-10-06 | 2022-03-15 | Advanced Micro Devices, Inc. | Circuit board with bridge chiplets |
| US9991215B1 (en) * | 2017-01-19 | 2018-06-05 | Nanya Technology Corporation | Semiconductor structure with through substrate via and manufacturing method thereof |
| US11121301B1 (en) | 2017-06-19 | 2021-09-14 | Rigetti & Co, Inc. | Microwave integrated quantum circuits with cap wafers and their methods of manufacture |
| US10510721B2 (en) | 2017-08-11 | 2019-12-17 | Advanced Micro Devices, Inc. | Molded chip combination |
| US11160163B2 (en) | 2017-11-17 | 2021-10-26 | Texas Instruments Incorporated | Electronic substrate having differential coaxial vias |
| CN111919297B (zh) * | 2018-03-31 | 2025-02-18 | 华为技术有限公司 | 一种半导体封装结构及其封装方法 |
| US10593628B2 (en) | 2018-04-24 | 2020-03-17 | Advanced Micro Devices, Inc. | Molded die last chip combination |
| US10593620B2 (en) | 2018-04-27 | 2020-03-17 | Advanced Micro Devices, Inc. | Fan-out package with multi-layer redistribution layer structure |
| US10672712B2 (en) | 2018-07-30 | 2020-06-02 | Advanced Micro Devices, Inc. | Multi-RDL structure packages and methods of fabricating the same |
| US10373901B1 (en) * | 2018-09-26 | 2019-08-06 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and manufacturing method thereof |
| US11710694B2 (en) * | 2019-05-24 | 2023-07-25 | Intel Corporation | Integrated circuit structures with contoured interconnects |
| US10923430B2 (en) | 2019-06-30 | 2021-02-16 | Advanced Micro Devices, Inc. | High density cross link die with polymer routing layer |
| US11367628B2 (en) | 2019-07-16 | 2022-06-21 | Advanced Micro Devices, Inc. | Molded chip package with anchor structures |
| US11742301B2 (en) | 2019-08-19 | 2023-08-29 | Advanced Micro Devices, Inc. | Fan-out package with reinforcing rivets |
| US11670578B2 (en) | 2020-06-02 | 2023-06-06 | Micron Technology, Inc. | Ball grid arrays and associated apparatuses and systems |
| CN113192923B (zh) * | 2021-03-30 | 2024-04-19 | 新华三半导体技术有限公司 | 一种封装基板的设计方法、封装基板和芯片 |
| WO2023214654A1 (ko) * | 2022-05-03 | 2023-11-09 | 삼성전자 주식회사 | 인터포져를 포함하는 전자 장치 |
| US20230386969A1 (en) * | 2022-05-26 | 2023-11-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Via connection structure having multiple via to via connections |
| CN116682800B (zh) * | 2023-06-08 | 2024-02-23 | 合芯科技有限公司 | 一种导体结构、半导体封装结构及电路板 |
Family Cites Families (75)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6728113B1 (en) * | 1993-06-24 | 2004-04-27 | Polychip, Inc. | Method and apparatus for non-conductively interconnecting integrated circuits |
| US5841191A (en) | 1997-04-21 | 1998-11-24 | Lsi Logic Corporation | Ball grid array package employing raised metal contact rings |
| US6759273B2 (en) | 2000-12-05 | 2004-07-06 | Analog Devices, Inc. | Method and device for protecting micro electromechanical systems structures during dicing of a wafer |
| US20020079572A1 (en) * | 2000-12-22 | 2002-06-27 | Khan Reza-Ur Rahman | Enhanced die-up ball grid array and method for making the same |
| US6906414B2 (en) * | 2000-12-22 | 2005-06-14 | Broadcom Corporation | Ball grid array package with patterned stiffener layer |
| US20040070080A1 (en) * | 2001-02-27 | 2004-04-15 | Chippac, Inc | Low cost, high performance flip chip package structure |
| US6563340B1 (en) * | 2001-05-21 | 2003-05-13 | Cypress Semiconductor Corp. | Architecture for implementing two chips in a package |
| US6525407B1 (en) | 2001-06-29 | 2003-02-25 | Novellus Systems, Inc. | Integrated circuit package |
| US6541842B2 (en) * | 2001-07-02 | 2003-04-01 | Dow Corning Corporation | Metal barrier behavior by SiC:H deposition on porous materials |
| EP1673807B1 (en) * | 2003-10-10 | 2019-12-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Electronic Device |
| US7166492B2 (en) * | 2003-11-14 | 2007-01-23 | Lsi Logic Corporation | Integrated circuit carrier apparatus method and system |
| US20050230821A1 (en) * | 2004-04-15 | 2005-10-20 | Kheng Lee T | Semiconductor packages, and methods of forming semiconductor packages |
| US7189594B2 (en) | 2004-09-10 | 2007-03-13 | Agency For Science, Technology And Research | Wafer level packages and methods of fabrication |
| JP4828164B2 (ja) * | 2005-06-06 | 2011-11-30 | ローム株式会社 | インタポーザおよび半導体装置 |
| CN101199248A (zh) * | 2005-06-15 | 2008-06-11 | 揖斐电株式会社 | 多层印刷线路板 |
| US7675157B2 (en) * | 2006-01-30 | 2010-03-09 | Marvell World Trade Ltd. | Thermal enhanced package |
| US7473577B2 (en) * | 2006-08-11 | 2009-01-06 | International Business Machines Corporation | Integrated chip carrier with compliant interconnect |
| SG146460A1 (en) * | 2007-03-12 | 2008-10-30 | Micron Technology Inc | Apparatus for packaging semiconductor devices, packaged semiconductor components, methods of manufacturing apparatus for packaging semiconductor devices, and methods of manufacturing semiconductor components |
| US20080284037A1 (en) * | 2007-05-15 | 2008-11-20 | Andry Paul S | Apparatus and Methods for Constructing Semiconductor Chip Packages with Silicon Space Transformer Carriers |
| KR20090118747A (ko) * | 2008-05-14 | 2009-11-18 | 삼성전자주식회사 | 관통 전극을 가지는 반도체 칩 패키지 및 인쇄회로기판 |
| US20100019374A1 (en) * | 2008-07-25 | 2010-01-28 | Stmicroelectronics, Inc. | Ball grid array package |
| JP2010045134A (ja) * | 2008-08-11 | 2010-02-25 | Shinko Electric Ind Co Ltd | 多層配線基板、半導体パッケージ及び製造方法 |
| US8344512B2 (en) * | 2009-08-20 | 2013-01-01 | International Business Machines Corporation | Three-dimensional silicon interposer for low voltage low power systems |
| US8088647B2 (en) | 2009-11-17 | 2012-01-03 | Broadcom Corporation | Bumping free flip chip process |
| US9385095B2 (en) * | 2010-02-26 | 2016-07-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D semiconductor package interposer with die cavity |
| US8338934B2 (en) * | 2010-03-18 | 2012-12-25 | Marvell World Trade Ltd. | Embedded die with protective interposer |
| US8866301B2 (en) * | 2010-05-18 | 2014-10-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package systems having interposers with interconnection structures |
| US9437561B2 (en) * | 2010-09-09 | 2016-09-06 | Advanced Micro Devices, Inc. | Semiconductor chip with redundant thru-silicon-vias |
| US8293578B2 (en) * | 2010-10-26 | 2012-10-23 | International Business Machines Corporation | Hybrid bonding techniques for multi-layer semiconductor stacks |
| US8805132B2 (en) * | 2010-12-08 | 2014-08-12 | International Business Machines Corporation | Integrated circuit package connected to a data transmission medium |
| KR101209980B1 (ko) * | 2010-12-09 | 2012-12-07 | 주식회사 네패스 | 반도체 패키지 및 그 제조 방법 |
| US8975751B2 (en) | 2011-04-22 | 2015-03-10 | Tessera, Inc. | Vias in porous substrates |
| US8704384B2 (en) | 2012-02-17 | 2014-04-22 | Xilinx, Inc. | Stacked die assembly |
| KR101798571B1 (ko) | 2012-02-16 | 2017-11-16 | 삼성전자주식회사 | 반도체 패키지 |
| KR102103811B1 (ko) * | 2012-04-24 | 2020-04-23 | 본드테크 가부시키가이샤 | 칩 온 웨이퍼 접합 방법 및 접합 장치, 및 칩과 웨이퍼를 포함하는 구조체 |
| US9219032B2 (en) * | 2012-07-09 | 2015-12-22 | Qualcomm Incorporated | Integrating through substrate vias from wafer backside layers of integrated circuits |
| US9490190B2 (en) * | 2012-09-21 | 2016-11-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thermal dissipation through seal rings in 3DIC structure |
| US8907470B2 (en) * | 2013-02-21 | 2014-12-09 | International Business Machines Corporation | Millimeter wave wafer level chip scale packaging (WLCSP) device and related method |
| JP6088893B2 (ja) * | 2013-04-09 | 2017-03-01 | ルネサスエレクトロニクス株式会社 | 半導体装置及び配線基板 |
| US9679868B2 (en) | 2013-06-19 | 2017-06-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Ball height control in bonding process |
| US9508701B2 (en) * | 2013-09-27 | 2016-11-29 | Freescale Semiconductor, Inc. | 3D device packaging using through-substrate pillars |
| JP6279754B2 (ja) * | 2013-12-09 | 2018-02-14 | インテル コーポレイション | パッケージングされたダイ用のセラミック上アンテナ |
| US9230900B1 (en) * | 2014-12-18 | 2016-01-05 | Intel Corporation | Ground via clustering for crosstalk mitigation |
| US9515017B2 (en) * | 2014-12-18 | 2016-12-06 | Intel Corporation | Ground via clustering for crosstalk mitigation |
| KR101640341B1 (ko) * | 2015-02-04 | 2016-07-15 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 |
| US9842800B2 (en) * | 2016-03-28 | 2017-12-12 | Intel Corporation | Forming interconnect structures utilizing subtractive paterning techniques |
| MY192389A (en) * | 2016-07-01 | 2022-08-18 | Intel Corp | Systems, methods, and apparatuses for implementing a pad on solder mask (posm) semiconductor substrate package |
| US10217716B2 (en) * | 2016-09-12 | 2019-02-26 | Mediatek Inc. | Semiconductor package and method for fabricating the same |
| US11640934B2 (en) * | 2018-03-30 | 2023-05-02 | Intel Corporation | Lithographically defined vertical interconnect access (VIA) in dielectric pockets in a package substrate |
| US10818602B2 (en) * | 2018-04-02 | 2020-10-27 | Amkor Technology, Inc. | Embedded ball land substrate, semiconductor package, and manufacturing methods |
| US10672693B2 (en) * | 2018-04-03 | 2020-06-02 | Intel Corporation | Integrated circuit structures in package substrates |
| US10879220B2 (en) * | 2018-06-15 | 2020-12-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package-on-package structure and manufacturing method thereof |
| US10431537B1 (en) * | 2018-06-21 | 2019-10-01 | Intel Corporation | Electromigration resistant and profile consistent contact arrays |
| US11424197B2 (en) * | 2018-07-27 | 2022-08-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package, package structure with redistributing circuits and antenna elements and method of manufacturing the same |
| US10700021B2 (en) * | 2018-08-31 | 2020-06-30 | Intel Corporation | Coreless organic packages with embedded die and magnetic inductor structures |
| KR102615197B1 (ko) * | 2018-11-23 | 2023-12-18 | 삼성전자주식회사 | 반도체 패키지 |
| US11990449B2 (en) * | 2019-01-14 | 2024-05-21 | Intel Corporation | Dual RDL stacked die package using vertical wire |
| US11227846B2 (en) * | 2019-01-30 | 2022-01-18 | Mediatek Inc. | Semiconductor package having improved thermal interface between semiconductor die and heat spreading structure |
| US12334447B2 (en) * | 2019-06-27 | 2025-06-17 | Intel Corporation | Lithographically defined vertical interconnect access (VIA) for a bridge die first level interconnect (FLI) |
| US10833053B1 (en) * | 2019-07-17 | 2020-11-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package and method of forming the same |
| US10825789B1 (en) * | 2019-08-26 | 2020-11-03 | Nxp B.V. | Underbump metallization dimension variation with improved reliability |
| US11532531B2 (en) * | 2019-10-29 | 2022-12-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package |
| MY203413A (en) * | 2019-12-12 | 2024-06-27 | Intel Corp | Interposer for hybrid interconnect geometry |
| US11430764B2 (en) * | 2019-12-20 | 2022-08-30 | Intel Corporation | Overhang bridge interconnect |
| US11450654B2 (en) * | 2019-12-25 | 2022-09-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and method of fabricating the same |
| TWI751051B (zh) * | 2020-04-17 | 2021-12-21 | 台灣積體電路製造股份有限公司 | 半導體結構及其製造方法 |
| US11277902B2 (en) * | 2020-05-25 | 2022-03-15 | Arbe Robotics Ltd. | Single layer radio frequency integrated circuit package and related low loss grounded coplanar transmission line |
| US11646255B2 (en) * | 2021-03-18 | 2023-05-09 | Taiwan Semiconductor Manufacturing Company Limited | Chip package structure including a silicon substrate interposer and methods for forming the same |
| US12191281B2 (en) * | 2021-06-16 | 2025-01-07 | Intel Corporation | Multi-chip package with recessed memory |
| US12368127B2 (en) * | 2021-10-29 | 2025-07-22 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor chip package having underfill material surrounding a fan-out package and contacting a stress buffer structure sidewall |
| US12394696B2 (en) * | 2022-03-23 | 2025-08-19 | Taiwan Semiconductor Manufacturing Company Limited | Package structure including an array of copper pillars and methods of forming the same |
| US20230386988A1 (en) * | 2022-05-31 | 2023-11-30 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor package with variable pillar height and methods for forming the same |
| US12406936B2 (en) * | 2022-06-01 | 2025-09-02 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor package with substrate recess and methods for forming the same |
| US20240266266A1 (en) * | 2023-02-07 | 2024-08-08 | Taiwan Semiconductor Manufacturing Company Limited | Interposer with built-in wiring for testing an embedded integrated passive device and methods for forming the same |
| US20250022810A1 (en) * | 2023-07-10 | 2025-01-16 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor package substrate with stress buffer pads and methods for making the same |
-
2015
- 2015-11-17 US US14/943,880 patent/US9515017B2/en active Active
- 2015-12-03 EP EP22217374.2A patent/EP4220709B1/en active Active
- 2015-12-03 EP EP21175747.1A patent/EP3951867B1/en active Active
- 2015-12-03 CN CN202411720971.3A patent/CN119560479A/zh active Pending
- 2015-12-03 EP EP15870674.7A patent/EP3234993B1/en active Active
- 2015-12-03 SG SG11201704038WA patent/SG11201704038WA/en unknown
- 2015-12-03 WO PCT/US2015/063822 patent/WO2016099936A1/en not_active Ceased
- 2015-12-03 CN CN202411720970.9A patent/CN119560478A/zh active Pending
- 2015-12-03 KR KR1020237003300A patent/KR102669054B1/ko active Active
- 2015-12-03 KR KR1020177013475A patent/KR102494739B1/ko active Active
- 2015-12-03 KR KR1020247016680A patent/KR102863843B1/ko active Active
- 2015-12-03 CN CN201580062829.7A patent/CN107004668B/zh active Active
- 2015-12-03 EP EP20200804.1A patent/EP3799118B1/en active Active
- 2015-12-03 CN CN201811450623.3A patent/CN110085567B/zh active Active
- 2015-12-03 JP JP2017530112A patent/JP6789945B2/ja active Active
- 2015-12-03 EP EP18214233.1A patent/EP3483932B1/en active Active
-
2016
- 2016-12-05 US US15/369,659 patent/US10026682B2/en active Active
-
2018
- 2018-07-03 US US16/026,824 patent/US10396022B2/en active Active
-
2019
- 2019-07-11 US US16/509,387 patent/US10854539B2/en active Active
-
2020
- 2020-10-20 US US17/074,820 patent/US11244890B2/en active Active
-
2021
- 2021-12-30 US US17/566,523 patent/US11742275B2/en active Active
-
2022
- 2022-09-29 US US17/956,766 patent/US11901280B2/en active Active
-
2023
- 2023-12-05 US US18/530,006 patent/US12482733B2/en active Active
Also Published As
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6789945B2 (ja) | クロストーク低減のためのグランドビアのクラスタ化 | |
| JP6067802B2 (ja) | 相互接続ルーティング構成及び関連技術 | |
| CN104218024B (zh) | 具有分层互连结构的桥互连 | |
| US9230900B1 (en) | Ground via clustering for crosstalk mitigation |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20181101 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20181101 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20181115 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20191129 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20200107 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20200406 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20201006 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20201104 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 6789945 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |