JP6778317B2 - マルチウエハ接合構造を形成するためのウエハスタッキング - Google Patents
マルチウエハ接合構造を形成するためのウエハスタッキング Download PDFInfo
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- JP6778317B2 JP6778317B2 JP2019503708A JP2019503708A JP6778317B2 JP 6778317 B2 JP6778317 B2 JP 6778317B2 JP 2019503708 A JP2019503708 A JP 2019503708A JP 2019503708 A JP2019503708 A JP 2019503708A JP 6778317 B2 JP6778317 B2 JP 6778317B2
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- 235000012431 wafers Nutrition 0.000 claims description 219
- 239000004593 Epoxy Substances 0.000 claims description 85
- 238000000034 method Methods 0.000 claims description 42
- 238000010438 heat treatment Methods 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 125000003700 epoxy group Chemical group 0.000 claims description 4
- 229910052738 indium Inorganic materials 0.000 claims description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 4
- 229920000647 polyepoxide Polymers 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 229910001220 stainless steel Inorganic materials 0.000 claims description 4
- 239000010935 stainless steel Substances 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- 238000005304 joining Methods 0.000 claims description 2
- 238000003303 reheating Methods 0.000 claims description 2
- 230000000694 effects Effects 0.000 claims 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 238000003892 spreading Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Description
Claims (18)
- ウエハチャックを加熱することと、
ある熱膨張係数(CTE)を有する第1のウエハを加熱することと、
前記ウエハチャック上に配置された前記第1のウエハの表面の少なくとも一部に沿って第1のエポキシを付与することと、
前記ウエハチャックを回転させて前記第1のエポキシを少なくとも部分的に前記第1のウエハにわたって広げることと、
前記第1のウエハ上に配置された前記第1のエポキシの上に、前記第1のウエハとは異なるCTEを有する第2のウエハを、該第2のウエハを受け入れる大きさにされた開口を持つセンタリングリングを用いることによって置くことであり、前記第2のウエハが前記第1のウエハの上に置かれた後、前記第2のウエハは、前記第1のエポキシから離間されたままである、置くことと、
真空下で前記第2のウエハを前記第1のエポキシに接合させて2ウエハ接合構造を形成することであり、前記第1のウエハと前記第2のウエハとの間に前記真空が適用されることの結果として、前記第2のウエハが前記第1のエポキシと接触する、形成することと、
を有する方法。 - 前記第2のウエハと同じCTEを有する第3のウエハを加熱することと、
前記ウエハチャック上に配置された前記第3のウエハの表面の少なくとも一部に沿って第2のエポキシを付与することと、
前記ウエハチャックを回転させて前記第2のエポキシを少なくとも部分的に前記第3のウエハにわたって広げることと、
前記第3のウエハに塗布された前記第2のエポキシを前記2ウエハ接合構造の前記第1のウエハと接触させることと、
真空下で前記第2のエポキシを前記第1のウエハに接合させて3ウエハ接合構造を形成することと、
を更に有する請求項1に記載の方法。 - 前記ウエハチャックを少なくとも65℃まで再加熱すること、を更に有する請求項2に記載の方法。
- 前記第3のウエハを加熱することは、前記第3のウエハを少なくとも65℃まで加熱することを有する、請求項2に記載の方法。
- 前記第3のウエハは、シリコンウエハを有する、請求項2に記載の方法。
- 前記第1のエポキシ及び前記第2のエポキシを硬化させるために、前記3ウエハ接合構造が加熱される、請求項2に記載の方法。
- 前記ウエハチャック上に配置された前記第3のウエハの表面の少なくとも一部に沿って前記第2のエポキシを付与することは、前記ウエハチャックが第1の速度で回転している間に前記第2のエポキシを付与することを有し、
前記ウエハチャックを回転させて前記第2のエポキシを少なくとも部分的に前記第3のウエハにわたって広げることは、前記ウエハチャックの速度を前記第1の速度から第2の速度まで上昇させることを有する、
請求項2に記載の方法。 - 前記第2のエポキシを付与することは、前記第1のエポキシに使用される材料を有する第2のエポキシを付与することを有する、請求項2に記載の方法。
- 前記ウエハチャックを加熱することは、前記ウエハチャックを少なくとも65℃まで加熱することを有する、請求項1に記載の方法。
- 前記第1のウエハを加熱することは、第1のウエハを少なくとも65℃まで加熱することを有する、請求項1に記載の方法。
- 前記第1のウエハは、膨張制御(CE)ウエハ、ステンレス鋼ウエハ、又はチタンウエハのうちの1つを有する、請求項1に記載の方法。
- 前記第2のウエハは、読み出し集積回路(ROIC)ウエハを有する、請求項1に記載の方法。
- 前記ROICウエハは、インジウムバンプを有するROICウエハを有する、請求項12に記載の方法。
- 前記ウエハチャック上に配置された前記第1のウエハの表面の少なくとも一部に沿って前記第1のエポキシを付与することは、前記ウエハチャックが第1の速度で回転している間に前記第1のエポキシを付与することを有する、請求項1に記載の方法。
- 前記ウエハチャックを回転させて前記第1のエポキシを少なくとも部分的に前記第1のウエハにわたって広げることは、前記ウエハチャックの速度を前記第1の速度から第2の速度まで上昇させることを有する、請求項14に記載の方法。
- ウエハチャックを加熱することと、
前記ウエハチャック上に配置された第1のウエハを加熱することと、
前記第1のウエハの表面の少なくとも一部に沿って第1のエポキシを付与することと、
前記第1のウエハの前記表面の上に、センタリングリングを介して、第2のウエハを浮かすことであり、前記センタリングリングは、第2のウエハを受け入れる大きさにされた内側開口を持ち、前記第2のウエハは、前記第1のウエハと前記第2のウエハとの間で前記センタリングリングの前記内側開口内に形成される1つ以上のエアポケットを介して、前記第1のウエハの前記表面の上に浮かされる、浮かすことと、
前記第2のウエハを前記第1のエポキシに接合させることと、
を有する方法。 - 前記第2のウエハを前記第1のエポキシに接合させることは、前記第1及び第2のウエハを真空下に置くことを有する、請求項16に記載の方法。
- 前記第1及び第2のウエハが真空下にある前、前記第2のウエハは、前記第1のウエハの前記表面の上方第1の高さに浮かされ、前記第1及び第2のウエハが真空下に置かれた後、前記第2のウエハは、前記第1のウエハの前記表面の上方に、より短い第2の高さに浮かされる、請求項17に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/258,300 | 2016-09-07 | ||
US15/258,300 US20180068843A1 (en) | 2016-09-07 | 2016-09-07 | Wafer stacking to form a multi-wafer-bonded structure |
PCT/US2017/030796 WO2018048482A1 (en) | 2016-09-07 | 2017-05-03 | Wafer stacking to form a multi-wafer-bonded structure |
Publications (2)
Publication Number | Publication Date |
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JP2019526172A JP2019526172A (ja) | 2019-09-12 |
JP6778317B2 true JP6778317B2 (ja) | 2020-10-28 |
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Application Number | Title | Priority Date | Filing Date |
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JP2019503708A Active JP6778317B2 (ja) | 2016-09-07 | 2017-05-03 | マルチウエハ接合構造を形成するためのウエハスタッキング |
Country Status (5)
Country | Link |
---|---|
US (2) | US20180068843A1 (ja) |
EP (1) | EP3510632B1 (ja) |
JP (1) | JP6778317B2 (ja) |
KR (1) | KR102225767B1 (ja) |
WO (1) | WO2018048482A1 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10847569B2 (en) | 2019-02-26 | 2020-11-24 | Raytheon Company | Wafer level shim processing |
WO2021092777A1 (zh) * | 2019-11-12 | 2021-05-20 | 深圳市汇顶科技股份有限公司 | 堆叠式的芯片、制造方法、图像传感器和电子设备 |
Family Cites Families (26)
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JPH0341715A (ja) | 1989-07-07 | 1991-02-22 | Toshiba Ceramics Co Ltd | スピンコーター |
JPH07506937A (ja) | 1993-01-19 | 1995-07-27 | ヒューズ・エアクラフト・カンパニー | 熱的に整合された読取り/検出器構造とその製造方法 |
US5672545A (en) | 1994-08-08 | 1997-09-30 | Santa Barbara Research Center | Thermally matched flip-chip detector assembly and method |
US5804771A (en) | 1996-09-26 | 1998-09-08 | Intel Corporation | Organic substrate (PCB) slip plane "stress deflector" for flip chip deivces |
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EP0886306A1 (en) | 1997-06-16 | 1998-12-23 | IMEC vzw | Low temperature adhesion bonding method for composite substrates |
US20020134503A1 (en) * | 2001-03-20 | 2002-09-26 | Accucorp Technical Services, Inc. | Silicon wafers bonded to insulator substrates by low viscosity epoxy wicking |
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JP2007308678A (ja) * | 2005-11-02 | 2007-11-29 | Shin Etsu Chem Co Ltd | 液状エポキシ樹脂組成物 |
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US7592594B2 (en) * | 2006-11-13 | 2009-09-22 | Raytheon Company | Method of construction of CTE matching structure with wafer processing and resulting structure |
KR100800214B1 (ko) * | 2006-12-13 | 2008-02-01 | 제일모직주식회사 | 반도체 조립용 접착 필름 조성물 및 접착 필름 |
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KR20120080634A (ko) * | 2009-11-13 | 2012-07-17 | 히다치 가세고교 가부시끼가이샤 | 반도체 장치, 반도체 장치의 제조 방법 및 접착제층 부착 반도체 웨이퍼 |
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WO2012118700A1 (en) | 2011-02-28 | 2012-09-07 | Dow Corning Corporation | Wafer bonding system and method for bonding and debonding thereof |
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JP5752639B2 (ja) * | 2012-05-28 | 2015-07-22 | 東京エレクトロン株式会社 | 接合システム、接合方法、プログラム及びコンピュータ記憶媒体 |
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CN109449082B (zh) * | 2013-05-29 | 2023-06-02 | Ev 集团 E·索尔纳有限责任公司 | 用以接合衬底的装置及方法 |
WO2015009801A1 (en) * | 2013-07-16 | 2015-01-22 | Dow Corning Corporation | Bonded wafer system and method for bonding and de-bonding thereof |
EP3057913A1 (en) * | 2013-10-18 | 2016-08-24 | Corning Incorporated | Methods and apparatus providing a substrate and protective coating thereon |
US9142694B2 (en) | 2013-10-25 | 2015-09-22 | Raytheon Company | Focal plane array packaging using isostatic pressure processing |
-
2016
- 2016-09-07 US US15/258,300 patent/US20180068843A1/en not_active Abandoned
-
2017
- 2017-05-03 WO PCT/US2017/030796 patent/WO2018048482A1/en unknown
- 2017-05-03 EP EP17723839.1A patent/EP3510632B1/en active Active
- 2017-05-03 JP JP2019503708A patent/JP6778317B2/ja active Active
- 2017-05-03 KR KR1020187033253A patent/KR102225767B1/ko active IP Right Grant
- 2017-11-22 US US15/820,839 patent/US10475664B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
EP3510632B1 (en) | 2023-01-25 |
KR20180135008A (ko) | 2018-12-19 |
US20180068843A1 (en) | 2018-03-08 |
KR102225767B1 (ko) | 2021-03-09 |
EP3510632A1 (en) | 2019-07-17 |
US20180096833A1 (en) | 2018-04-05 |
WO2018048482A1 (en) | 2018-03-15 |
US10475664B2 (en) | 2019-11-12 |
JP2019526172A (ja) | 2019-09-12 |
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