JP6768928B2 - アドレスを圧縮するための方法及び装置 - Google Patents

アドレスを圧縮するための方法及び装置 Download PDF

Info

Publication number
JP6768928B2
JP6768928B2 JP2019508974A JP2019508974A JP6768928B2 JP 6768928 B2 JP6768928 B2 JP 6768928B2 JP 2019508974 A JP2019508974 A JP 2019508974A JP 2019508974 A JP2019508974 A JP 2019508974A JP 6768928 B2 JP6768928 B2 JP 6768928B2
Authority
JP
Japan
Prior art keywords
memory address
cache
stored
address
tag
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2019508974A
Other languages
English (en)
Japanese (ja)
Other versions
JP2019525354A5 (enExample
JP2019525354A (ja
Inventor
カリヤナスンダラム ヴィドヒャナサン
カリヤナスンダラム ヴィドヒャナサン
ディー． ダンリー グレゴリー
ディー． ダンリー グレゴリー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2019525354A publication Critical patent/JP2019525354A/ja
Publication of JP2019525354A5 publication Critical patent/JP2019525354A5/ja
Application granted granted Critical
Publication of JP6768928B2 publication Critical patent/JP6768928B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/0647—Migration mechanisms
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0886—Variable-length word access
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/40—Specific encoding of data in memory or cache
    • G06F2212/401—Compressed data
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Mathematical Physics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
JP2019508974A 2016-08-17 2017-08-04 アドレスを圧縮するための方法及び装置 Active JP6768928B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201662376096P 2016-08-17 2016-08-17
US62/376,096 2016-08-17
US15/345,639 US10042576B2 (en) 2016-08-17 2016-11-08 Method and apparatus for compressing addresses
US15/345,639 2016-11-08
PCT/US2017/045639 WO2018034875A1 (en) 2016-08-17 2017-08-04 Method and apparatus for compressing addresses

Publications (3)

Publication Number Publication Date
JP2019525354A JP2019525354A (ja) 2019-09-05
JP2019525354A5 JP2019525354A5 (enExample) 2020-09-10
JP6768928B2 true JP6768928B2 (ja) 2020-10-14

Family

ID=61191652

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019508974A Active JP6768928B2 (ja) 2016-08-17 2017-08-04 アドレスを圧縮するための方法及び装置

Country Status (6)

Country Link
US (1) US10042576B2 (enExample)
EP (2) EP3500935A4 (enExample)
JP (1) JP6768928B2 (enExample)
KR (1) KR102219845B1 (enExample)
CN (1) CN109564545B (enExample)
WO (1) WO2018034875A1 (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10031834B2 (en) 2016-08-31 2018-07-24 Microsoft Technology Licensing, Llc Cache-based tracing for time travel debugging and analysis
US10042737B2 (en) 2016-08-31 2018-08-07 Microsoft Technology Licensing, Llc Program tracing for time travel debugging and analysis
US10489273B2 (en) 2016-10-20 2019-11-26 Microsoft Technology Licensing, Llc Reuse of a related thread's cache while recording a trace file of code execution
US10310977B2 (en) 2016-10-20 2019-06-04 Microsoft Technology Licensing, Llc Facilitating recording a trace file of code execution using a processor cache
US10310963B2 (en) 2016-10-20 2019-06-04 Microsoft Technology Licensing, Llc Facilitating recording a trace file of code execution using index bits in a processor cache
US10540250B2 (en) * 2016-11-11 2020-01-21 Microsoft Technology Licensing, Llc Reducing storage requirements for storing memory addresses and values
US10318332B2 (en) 2017-04-01 2019-06-11 Microsoft Technology Licensing, Llc Virtual machine execution tracing
CN109240944B (zh) * 2018-08-16 2021-02-19 上海天数智芯半导体有限公司 一种基于可变长缓存行的数据读写方法
US11831565B2 (en) * 2018-10-03 2023-11-28 Advanced Micro Devices, Inc. Method for maintaining cache consistency during reordering
US20210026686A1 (en) * 2019-07-22 2021-01-28 Advanced Micro Devices, Inc. Chiplet-integrated machine learning accelerators
CN111126589B (zh) * 2019-12-31 2022-05-20 昆仑芯(北京)科技有限公司 神经网络数据处理装置、方法和电子设备
KR102494444B1 (ko) * 2020-11-17 2023-02-06 성균관대학교산학협력단 어드레스 압축 방법 및 장치
JP2023079640A (ja) * 2021-11-29 2023-06-08 富士通株式会社 演算処理装置および演算処理方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0735487B1 (en) * 1995-03-31 2001-10-31 Sun Microsystems, Inc. A fast, dual ported cache controller for data processors in a packet switched cache coherent multiprocessor system
JP3413344B2 (ja) * 1997-05-16 2003-06-03 シャープ株式会社 画像演算処理装置およびその動作方法
US6477613B1 (en) 1999-06-30 2002-11-05 International Business Machines Corporation Cache index based system address bus
US6449689B1 (en) * 1999-08-31 2002-09-10 International Business Machines Corporation System and method for efficiently storing compressed data on a hard disk drive
US6795897B2 (en) 2002-05-15 2004-09-21 International Business Machines Corporation Selective memory controller access path for directory caching
US7096323B1 (en) * 2002-09-27 2006-08-22 Advanced Micro Devices, Inc. Computer system with processor cache that stores remote cache presence information
US7143238B2 (en) * 2003-09-30 2006-11-28 Intel Corporation Mechanism to compress data in a cache
US7512750B2 (en) * 2003-12-31 2009-03-31 Intel Corporation Processor and memory controller capable of use in computing system that employs compressed cache lines' worth of information
US20080229026A1 (en) 2007-03-15 2008-09-18 Taiwan Semiconductor Manufacturing Co., Ltd. System and method for concurrently checking availability of data in extending memories
US20090006757A1 (en) 2007-06-29 2009-01-01 Abhishek Singhal Hierarchical cache tag architecture
US9026568B2 (en) 2012-03-30 2015-05-05 Altera Corporation Data compression for direct memory access transfers
US9558120B2 (en) * 2014-03-27 2017-01-31 Intel Corporation Method, apparatus and system to cache sets of tags of an off-die cache memory

Also Published As

Publication number Publication date
WO2018034875A1 (en) 2018-02-22
EP4220415A2 (en) 2023-08-02
KR20190032527A (ko) 2019-03-27
KR102219845B1 (ko) 2021-02-24
EP3500935A1 (en) 2019-06-26
US10042576B2 (en) 2018-08-07
CN109564545B (zh) 2021-02-02
CN109564545A (zh) 2019-04-02
EP3500935A4 (en) 2020-04-08
EP4220415A3 (en) 2023-09-06
US20180052631A1 (en) 2018-02-22
JP2019525354A (ja) 2019-09-05

Similar Documents

Publication Publication Date Title
JP6768928B2 (ja) アドレスを圧縮するための方法及び装置
US9996466B2 (en) Apparatus, system and method for caching compressed data
US10339079B2 (en) System and method of interleaving data retrieved from first and second buffers
US7089391B2 (en) Managing a codec engine for memory compression/decompression operations using a data movement engine
US12045187B2 (en) Routing network using global address map with adaptive main memory expansion for a plurality of home agents
JP6859361B2 (ja) 中央処理ユニット（ｃｐｕ）ベースシステムにおいて複数のラストレベルキャッシュ（ｌｌｃ）ラインを使用してメモリ帯域幅圧縮を行うこと
TWI594121B (zh) 使用資料壓縮的快取技術
CN103329111B (zh) 一种基于块存储的数据处理方法、装置及系统
US20170177497A1 (en) Compressed caching of a logical-to-physical address table for nand-type flash memory
CN106126124B (zh) 一种数据处理方法及电子设备
JP2020502694A (ja) バイトアドレス可能メモリとして不揮発性メモリにアクセスする方法及び装置
JP2009032243A (ja) 取り出されたデータをメモリに直接に書き込むストレージコントローラによるバッファスペースの最適な使用
CN105408875B (zh) 在存储器接口上的分布式过程执行和文件系统
US20150347016A1 (en) Input/output virtualization (iov) host controller (hc) (iov-hc) of a flash-memory-based storage device
JPWO2014192144A1 (ja) ホストバスアダプタおよびシステム
CN117337425B (zh) 存储装置、方法及电子设备
US20180329756A1 (en) Distributed processing system, distributed processing method, and storage medium
WO2018052718A1 (en) Method and apparatus for masking and transmitting data
US20060277326A1 (en) Data transfer system and method
US20230205420A1 (en) Flexible memory system
US20070050549A1 (en) Method and system for managing cacheability of data blocks to improve processor power management

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20200731

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20200731

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20200731

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20200807

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20200825

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20200923

R150 Certificate of patent or registration of utility model

Ref document number: 6768928

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250