CN109564545B - 用于压缩地址的方法和设备 - Google Patents

用于压缩地址的方法和设备 Download PDF

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CN109564545B
CN109564545B CN201780048506.1A CN201780048506A CN109564545B CN 109564545 B CN109564545 B CN 109564545B CN 201780048506 A CN201780048506 A CN 201780048506A CN 109564545 B CN109564545 B CN 109564545B
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memory address
cache
stored
tag
storing
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CN109564545A (zh
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维德海雅娜丹·卡尔雅娜孙达拉姆
格雷戈里·D·唐利
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
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    • G06F3/0601—Interfaces specially adapted for storage systems
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    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
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    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
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    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/0647—Migration mechanisms
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0886—Variable-length word access
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/40—Specific encoding of data in memory or cache
    • G06F2212/401—Compressed data
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Mathematical Physics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
CN201780048506.1A 2016-08-17 2017-08-04 用于压缩地址的方法和设备 Active CN109564545B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201662376096P 2016-08-17 2016-08-17
US62/376,096 2016-08-17
US15/345,639 US10042576B2 (en) 2016-08-17 2016-11-08 Method and apparatus for compressing addresses
US15/345,639 2016-11-08
PCT/US2017/045639 WO2018034875A1 (en) 2016-08-17 2017-08-04 Method and apparatus for compressing addresses

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CN109564545A CN109564545A (zh) 2019-04-02
CN109564545B true CN109564545B (zh) 2021-02-02

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US (1) US10042576B2 (enExample)
EP (2) EP3500935A4 (enExample)
JP (1) JP6768928B2 (enExample)
KR (1) KR102219845B1 (enExample)
CN (1) CN109564545B (enExample)
WO (1) WO2018034875A1 (enExample)

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US10031834B2 (en) 2016-08-31 2018-07-24 Microsoft Technology Licensing, Llc Cache-based tracing for time travel debugging and analysis
US10042737B2 (en) 2016-08-31 2018-08-07 Microsoft Technology Licensing, Llc Program tracing for time travel debugging and analysis
US10489273B2 (en) 2016-10-20 2019-11-26 Microsoft Technology Licensing, Llc Reuse of a related thread's cache while recording a trace file of code execution
US10310977B2 (en) 2016-10-20 2019-06-04 Microsoft Technology Licensing, Llc Facilitating recording a trace file of code execution using a processor cache
US10310963B2 (en) 2016-10-20 2019-06-04 Microsoft Technology Licensing, Llc Facilitating recording a trace file of code execution using index bits in a processor cache
US10540250B2 (en) * 2016-11-11 2020-01-21 Microsoft Technology Licensing, Llc Reducing storage requirements for storing memory addresses and values
US10318332B2 (en) 2017-04-01 2019-06-11 Microsoft Technology Licensing, Llc Virtual machine execution tracing
CN109240944B (zh) * 2018-08-16 2021-02-19 上海天数智芯半导体有限公司 一种基于可变长缓存行的数据读写方法
US11831565B2 (en) * 2018-10-03 2023-11-28 Advanced Micro Devices, Inc. Method for maintaining cache consistency during reordering
US20210026686A1 (en) * 2019-07-22 2021-01-28 Advanced Micro Devices, Inc. Chiplet-integrated machine learning accelerators
CN111126589B (zh) * 2019-12-31 2022-05-20 昆仑芯(北京)科技有限公司 神经网络数据处理装置、方法和电子设备
KR102494444B1 (ko) * 2020-11-17 2023-02-06 성균관대학교산학협력단 어드레스 압축 방법 및 장치
JP2023079640A (ja) * 2021-11-29 2023-06-08 富士通株式会社 演算処理装置および演算処理方法

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CN1853170A (zh) * 2003-09-30 2006-10-25 英特尔公司 压缩高速缓存内数据的机制
CN101419574A (zh) * 2003-12-31 2009-04-29 英特尔公司 能在使用压缩的高速缓存行信息价值的计算系统中使用的处理器和存储器控制器

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WO2018034875A1 (en) 2018-02-22
EP4220415A2 (en) 2023-08-02
KR20190032527A (ko) 2019-03-27
KR102219845B1 (ko) 2021-02-24
JP6768928B2 (ja) 2020-10-14
EP3500935A1 (en) 2019-06-26
US10042576B2 (en) 2018-08-07
CN109564545A (zh) 2019-04-02
EP3500935A4 (en) 2020-04-08
EP4220415A3 (en) 2023-09-06
US20180052631A1 (en) 2018-02-22
JP2019525354A (ja) 2019-09-05

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