KR102219845B1 - 어드레스를 압축하기 위한 방법 및 장치 - Google Patents

어드레스를 압축하기 위한 방법 및 장치 Download PDF

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KR102219845B1
KR102219845B1 KR1020197005418A KR20197005418A KR102219845B1 KR 102219845 B1 KR102219845 B1 KR 102219845B1 KR 1020197005418 A KR1020197005418 A KR 1020197005418A KR 20197005418 A KR20197005418 A KR 20197005418A KR 102219845 B1 KR102219845 B1 KR 102219845B1
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memory address
cache
stored
tag
address
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KR20190032527A (ko
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비드히아나탄 칼야나순드하람
그레고리 디. 돈레이
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어드밴스드 마이크로 디바이시즈, 인코포레이티드
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    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0886—Variable-length word access
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/40—Specific encoding of data in memory or cache
    • G06F2212/401—Compressed data
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Mathematical Physics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
KR1020197005418A 2016-08-17 2017-08-04 어드레스를 압축하기 위한 방법 및 장치 Active KR102219845B1 (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201662376096P 2016-08-17 2016-08-17
US62/376,096 2016-08-17
US15/345,639 2016-11-08
US15/345,639 US10042576B2 (en) 2016-08-17 2016-11-08 Method and apparatus for compressing addresses
PCT/US2017/045639 WO2018034875A1 (en) 2016-08-17 2017-08-04 Method and apparatus for compressing addresses

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KR20190032527A KR20190032527A (ko) 2019-03-27
KR102219845B1 true KR102219845B1 (ko) 2021-02-24

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US (1) US10042576B2 (enExample)
EP (2) EP3500935A4 (enExample)
JP (1) JP6768928B2 (enExample)
KR (1) KR102219845B1 (enExample)
CN (1) CN109564545B (enExample)
WO (1) WO2018034875A1 (enExample)

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Publication number Priority date Publication date Assignee Title
US10031834B2 (en) 2016-08-31 2018-07-24 Microsoft Technology Licensing, Llc Cache-based tracing for time travel debugging and analysis
US10042737B2 (en) 2016-08-31 2018-08-07 Microsoft Technology Licensing, Llc Program tracing for time travel debugging and analysis
US10489273B2 (en) 2016-10-20 2019-11-26 Microsoft Technology Licensing, Llc Reuse of a related thread's cache while recording a trace file of code execution
US10310977B2 (en) 2016-10-20 2019-06-04 Microsoft Technology Licensing, Llc Facilitating recording a trace file of code execution using a processor cache
US10310963B2 (en) 2016-10-20 2019-06-04 Microsoft Technology Licensing, Llc Facilitating recording a trace file of code execution using index bits in a processor cache
US10540250B2 (en) * 2016-11-11 2020-01-21 Microsoft Technology Licensing, Llc Reducing storage requirements for storing memory addresses and values
US10318332B2 (en) 2017-04-01 2019-06-11 Microsoft Technology Licensing, Llc Virtual machine execution tracing
CN109240944B (zh) * 2018-08-16 2021-02-19 上海天数智芯半导体有限公司 一种基于可变长缓存行的数据读写方法
US11831565B2 (en) * 2018-10-03 2023-11-28 Advanced Micro Devices, Inc. Method for maintaining cache consistency during reordering
US20210026686A1 (en) * 2019-07-22 2021-01-28 Advanced Micro Devices, Inc. Chiplet-integrated machine learning accelerators
CN111126589B (zh) * 2019-12-31 2022-05-20 昆仑芯(北京)科技有限公司 神经网络数据处理装置、方法和电子设备
KR102494444B1 (ko) * 2020-11-17 2023-02-06 성균관대학교산학협력단 어드레스 압축 방법 및 장치
JP2023079640A (ja) * 2021-11-29 2023-06-08 富士通株式会社 演算処理装置および演算処理方法

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US6449689B1 (en) 1999-08-31 2002-09-10 International Business Machines Corporation System and method for efficiently storing compressed data on a hard disk drive
US6477613B1 (en) 1999-06-30 2002-11-05 International Business Machines Corporation Cache index based system address bus
US20030217237A1 (en) 2002-05-15 2003-11-20 Internation Business Machines Corporation Selective memory controller access path for directory caching
US20050144388A1 (en) 2003-12-31 2005-06-30 Newburn Chris J. Processor and memory controller capable of use in computing system that employs compressed cache lines' worth of information
WO2009006113A2 (en) 2007-06-29 2009-01-08 Intel Corporation Hierarchical cache tag architecture
US20130262538A1 (en) 2012-03-30 2013-10-03 Samplify Systems, Inc. Data compression for direct memory access transfers
US20150278096A1 (en) 2014-03-27 2015-10-01 Dyer Rolan Method, apparatus and system to cache sets of tags of an off-die cache memory
US20150363314A1 (en) 2007-03-15 2015-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. System and Method for Concurrently Checking Availability of Data in Extending Memories

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US5644753A (en) 1995-03-31 1997-07-01 Sun Microsystems, Inc. Fast, dual ported cache controller for data processors in a packet switched cache coherent multiprocessor system
US6477613B1 (en) 1999-06-30 2002-11-05 International Business Machines Corporation Cache index based system address bus
US6449689B1 (en) 1999-08-31 2002-09-10 International Business Machines Corporation System and method for efficiently storing compressed data on a hard disk drive
US20030217237A1 (en) 2002-05-15 2003-11-20 Internation Business Machines Corporation Selective memory controller access path for directory caching
US20050144388A1 (en) 2003-12-31 2005-06-30 Newburn Chris J. Processor and memory controller capable of use in computing system that employs compressed cache lines' worth of information
US20150363314A1 (en) 2007-03-15 2015-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. System and Method for Concurrently Checking Availability of Data in Extending Memories
WO2009006113A2 (en) 2007-06-29 2009-01-08 Intel Corporation Hierarchical cache tag architecture
US20130262538A1 (en) 2012-03-30 2013-10-03 Samplify Systems, Inc. Data compression for direct memory access transfers
US20150278096A1 (en) 2014-03-27 2015-10-01 Dyer Rolan Method, apparatus and system to cache sets of tags of an off-die cache memory

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Publication number Publication date
CN109564545B (zh) 2021-02-02
EP3500935A4 (en) 2020-04-08
KR20190032527A (ko) 2019-03-27
JP6768928B2 (ja) 2020-10-14
US20180052631A1 (en) 2018-02-22
WO2018034875A1 (en) 2018-02-22
US10042576B2 (en) 2018-08-07
CN109564545A (zh) 2019-04-02
JP2019525354A (ja) 2019-09-05
EP4220415A2 (en) 2023-08-02
EP4220415A3 (en) 2023-09-06
EP3500935A1 (en) 2019-06-26

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