JP2019525354A5 - - Google Patents

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Publication number
JP2019525354A5
JP2019525354A5 JP2019508974A JP2019508974A JP2019525354A5 JP 2019525354 A5 JP2019525354 A5 JP 2019525354A5 JP 2019508974 A JP2019508974 A JP 2019508974A JP 2019508974 A JP2019508974 A JP 2019508974A JP 2019525354 A5 JP2019525354 A5 JP 2019525354A5
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JP
Japan
Prior art keywords
memory address
cache
stored
tag
way
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JP2019508974A
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English (en)
Japanese (ja)
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JP6768928B2 (ja
JP2019525354A (ja
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Priority claimed from US15/345,639 external-priority patent/US10042576B2/en
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Publication of JP2019525354A5 publication Critical patent/JP2019525354A5/ja
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Publication of JP6768928B2 publication Critical patent/JP6768928B2/ja
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JP2019508974A 2016-08-17 2017-08-04 アドレスを圧縮するための方法及び装置 Active JP6768928B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201662376096P 2016-08-17 2016-08-17
US62/376,096 2016-08-17
US15/345,639 US10042576B2 (en) 2016-08-17 2016-11-08 Method and apparatus for compressing addresses
US15/345,639 2016-11-08
PCT/US2017/045639 WO2018034875A1 (en) 2016-08-17 2017-08-04 Method and apparatus for compressing addresses

Publications (3)

Publication Number Publication Date
JP2019525354A JP2019525354A (ja) 2019-09-05
JP2019525354A5 true JP2019525354A5 (enExample) 2020-09-10
JP6768928B2 JP6768928B2 (ja) 2020-10-14

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JP2019508974A Active JP6768928B2 (ja) 2016-08-17 2017-08-04 アドレスを圧縮するための方法及び装置

Country Status (6)

Country Link
US (1) US10042576B2 (enExample)
EP (2) EP3500935A4 (enExample)
JP (1) JP6768928B2 (enExample)
KR (1) KR102219845B1 (enExample)
CN (1) CN109564545B (enExample)
WO (1) WO2018034875A1 (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10031834B2 (en) 2016-08-31 2018-07-24 Microsoft Technology Licensing, Llc Cache-based tracing for time travel debugging and analysis
US10042737B2 (en) 2016-08-31 2018-08-07 Microsoft Technology Licensing, Llc Program tracing for time travel debugging and analysis
US10489273B2 (en) 2016-10-20 2019-11-26 Microsoft Technology Licensing, Llc Reuse of a related thread's cache while recording a trace file of code execution
US10310977B2 (en) 2016-10-20 2019-06-04 Microsoft Technology Licensing, Llc Facilitating recording a trace file of code execution using a processor cache
US10310963B2 (en) 2016-10-20 2019-06-04 Microsoft Technology Licensing, Llc Facilitating recording a trace file of code execution using index bits in a processor cache
US10540250B2 (en) * 2016-11-11 2020-01-21 Microsoft Technology Licensing, Llc Reducing storage requirements for storing memory addresses and values
US10318332B2 (en) 2017-04-01 2019-06-11 Microsoft Technology Licensing, Llc Virtual machine execution tracing
CN109240944B (zh) * 2018-08-16 2021-02-19 上海天数智芯半导体有限公司 一种基于可变长缓存行的数据读写方法
US11831565B2 (en) * 2018-10-03 2023-11-28 Advanced Micro Devices, Inc. Method for maintaining cache consistency during reordering
US20210026686A1 (en) * 2019-07-22 2021-01-28 Advanced Micro Devices, Inc. Chiplet-integrated machine learning accelerators
CN111126589B (zh) * 2019-12-31 2022-05-20 昆仑芯(北京)科技有限公司 神经网络数据处理装置、方法和电子设备
KR102494444B1 (ko) * 2020-11-17 2023-02-06 성균관대학교산학협력단 어드레스 압축 방법 및 장치
JP2023079640A (ja) * 2021-11-29 2023-06-08 富士通株式会社 演算処理装置および演算処理方法

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EP0735487B1 (en) * 1995-03-31 2001-10-31 Sun Microsystems, Inc. A fast, dual ported cache controller for data processors in a packet switched cache coherent multiprocessor system
JP3413344B2 (ja) * 1997-05-16 2003-06-03 シャープ株式会社 画像演算処理装置およびその動作方法
US6477613B1 (en) 1999-06-30 2002-11-05 International Business Machines Corporation Cache index based system address bus
US6449689B1 (en) * 1999-08-31 2002-09-10 International Business Machines Corporation System and method for efficiently storing compressed data on a hard disk drive
US6795897B2 (en) 2002-05-15 2004-09-21 International Business Machines Corporation Selective memory controller access path for directory caching
US7096323B1 (en) * 2002-09-27 2006-08-22 Advanced Micro Devices, Inc. Computer system with processor cache that stores remote cache presence information
US7143238B2 (en) * 2003-09-30 2006-11-28 Intel Corporation Mechanism to compress data in a cache
US7512750B2 (en) * 2003-12-31 2009-03-31 Intel Corporation Processor and memory controller capable of use in computing system that employs compressed cache lines' worth of information
US20080229026A1 (en) 2007-03-15 2008-09-18 Taiwan Semiconductor Manufacturing Co., Ltd. System and method for concurrently checking availability of data in extending memories
US20090006757A1 (en) 2007-06-29 2009-01-01 Abhishek Singhal Hierarchical cache tag architecture
US9026568B2 (en) 2012-03-30 2015-05-05 Altera Corporation Data compression for direct memory access transfers
US9558120B2 (en) * 2014-03-27 2017-01-31 Intel Corporation Method, apparatus and system to cache sets of tags of an off-die cache memory

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