JP6752843B2 - 書き換え可能なインプレースメモリを有するデータ記憶装置 - Google Patents
書き換え可能なインプレースメモリを有するデータ記憶装置 Download PDFInfo
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- Human Computer Interaction (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
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- Memory System Of A Hierarchy Structure (AREA)
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- Computer Hardware Design (AREA)
Description
Claims (16)
- データ記憶装置に常駐する不揮発性メモリを備える装置であって、前記不揮発性メモリは、読み出し−書き込み非対称性を有する書き換え可能なインプレースメモリセルを備え、前記インプレースメモリセルは、複数のセルを有し、ビットアドレス指定による前記複数のセルの各々へのアクセスが可能であり、前記不揮発性メモリは、前記データ記憶装置の選択モジュールによって、前記データ記憶装置の動作条件の変化を含む事象の前に第1の複数の階層に分割され、前記事象の後に第2の複数の階層に分割され、前記第1の複数の階層と前記第2の複数の階層とは異なっている、装置。
- 前記第1の複数の階層は、前記第2の複数の階層とは異なる数の階層を有する、請求項1に記載の装置。
- 前記第1の複数の階層及び前記第2の複数の階層は、それぞれ仮想化される、請求項1に記載の装置。
- 前記第2の複数の階層のそれぞれの階層は、物理ブロックアドレスの範囲に割り当てられる、請求項1に記載の装置。
- 前記第2の複数の階層のそれぞれの階層の範囲は、異なり、重複していない、請求項4に記載の装置。
- 方法であって、
データ記憶装置に常駐する不揮発性メモリを活性化させることであって、前記不揮発性メモリは、読み出し−書き込み非対称性を有する書き換え可能なインプレースメモリセルを備えることを含み、前記インプレースメモリセルは、複数のセルを有し、ビットアドレス指定による前記複数のセルの各々へのアクセスが可能でありと、
前記方法は、さらに、
前記不揮発性メモリを前記データ記憶装置の選択モジュールによって第1の複数の階層に分割することと、
前記不揮発性メモリを第2の複数の階層に変更することによって、前記データ記憶装置の動作条件の変化を含む事象に適合することであって、前記第1の複数の階層と前記第2の複数の階層とは異なっている、ことと、
を含む、方法。 - 前記第2の複数の階層は、階層的構造に配列される、請求項6に記載の方法。
- 前記第2の複数の階層のうちの第1の階層は、データが、前記第2の複数の階層のうちの別の階層まで動かされる前に、最初に記憶されるキャッシュである、請求項7に記載の方法。
- 前記第2の複数の階層のそれぞれの階層は、前記第2の複数の階層のそれぞれの階層に記憶されたデータのアクセス頻度に対応する、請求項7に記載の方法。
- 前記選択モジュールは、前記第2の複数の階層のそれぞれの階層のデータを動かすことを伴わずに、前記データを更新する、請求項6に記載の方法。
- 方法であって、
データ記憶装置に常駐する不揮発性メモリを活性化させることであって、前記不揮発性メモリは、読み出し−書き込み非対称性を有する書き換え可能なインプレースメモリセルを備えことを含み、前記インプレースメモリセルは、複数のセルを有し、ビットアドレス指定による前記複数のセルの各々へのアクセスが可能でありと、
前記方法は、さらに、
前記不揮発性メモリを前記データ記憶装置の選択モジュールによって第1の複数の階層に分割することと、
前記データ記憶装置の選択モジュールによって前記データ記憶装置の動作条件の変化を含む事象を予測することと、
前記不揮発性メモリを第2の複数の階層に変更することによって前記事象に率先的に適合することであって、前記第1の複数の階層と前記第2の複数の階層とは異なっている、ことと、
を含む、方法。 - 前記予測された事象は、前記データ記憶装置の性能パラメータを妨げるように前記選択モジュールによって予想される、請求項11に記載の方法。
- 前記選択モジュールは、前記予測された事象に応じて前記第2の複数の階層のうちの複数の異なる階層にデータを分割する、請求項11に記載の方法。
- 前記選択モジュールは、前記予測された事象に応じて前記第2の複数の階層のうちの複数の異なる階層にわたってデータをストライプ(stripe)する、請求項11に記載の方法。
- 前記選択モジュールは、前記不揮発性メモリの整定時間を通して読み出される前記データ記憶装置のバッファメモリにデータのシャドウコピーを書き込む、請求項11に記載の方法。
- 前記第2の複数の階層のうちのマップ階層は、前記不揮発性メモリに常駐するデータのマップからなる、請求項11に記載の方法。
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US15/607,801 | 2017-05-30 | ||
US15/607,801 US10068663B1 (en) | 2017-05-30 | 2017-05-30 | Data storage device with rewriteable in-place memory |
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JP2018206377A JP2018206377A (ja) | 2018-12-27 |
JP2018206377A5 JP2018206377A5 (ja) | 2019-05-09 |
JP6752843B2 true JP6752843B2 (ja) | 2020-09-09 |
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JP (1) | JP6752843B2 (ja) |
KR (1) | KR102095428B1 (ja) |
CN (1) | CN108984111B (ja) |
TW (1) | TWI684861B (ja) |
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US10942677B2 (en) * | 2019-01-24 | 2021-03-09 | Silicon Motion, Inc. | Method for performing access management of memory device, associated memory device and controller thereof, associated host device and associated electronic device |
Family Cites Families (45)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6438670B1 (en) | 1998-10-02 | 2002-08-20 | International Business Machines Corporation | Memory controller with programmable delay counter for tuning performance based on timing parameter of controlled memory storage device |
KR100331542B1 (ko) * | 1998-10-09 | 2002-06-20 | 윤종용 | 불량메모리셀어레이블락들을스킵할수있는어드레스디코더를구비하는반도체메모리장치및이를사용하는복합반도체장치 |
US6374323B1 (en) | 1998-11-16 | 2002-04-16 | Infineon Technologies Ag | Computer memory conflict avoidance using page registers |
KR100330164B1 (ko) * | 1999-04-27 | 2002-03-28 | 윤종용 | 무효 블록들을 가지는 복수의 플래시 메모리들을 동시에 프로그램하는 방법 |
US6795338B2 (en) | 2002-12-13 | 2004-09-21 | Intel Corporation | Memory having access devices using phase change material such as chalcogenide |
JP3795875B2 (ja) | 2003-05-22 | 2006-07-12 | 東芝マイクロエレクトロニクス株式会社 | 磁気ランダムアクセスメモリ及びそのデータ読み出し方法 |
JP4956922B2 (ja) * | 2004-10-27 | 2012-06-20 | ソニー株式会社 | 記憶装置 |
US8200887B2 (en) * | 2007-03-29 | 2012-06-12 | Violin Memory, Inc. | Memory management system and method |
US7835170B2 (en) | 2005-05-09 | 2010-11-16 | Nantero, Inc. | Memory elements and cross point switches and arrays of same using nonvolatile nanotube blocks |
US7606111B2 (en) * | 2007-04-26 | 2009-10-20 | Super Talent Electronics, Inc. | Synchronous page-mode phase-change memory with ECC and RAM cache |
JP4558054B2 (ja) * | 2008-03-11 | 2010-10-06 | 株式会社東芝 | メモリシステム |
KR20090109345A (ko) * | 2008-04-15 | 2009-10-20 | 삼성전자주식회사 | 저항체를 이용한 비휘발성 메모리 장치, 이를 포함하는메모리 시스템 |
US8225031B2 (en) | 2008-10-30 | 2012-07-17 | Hewlett-Packard Development Company, L.P. | Memory module including environmental optimization |
US8239613B2 (en) * | 2008-12-30 | 2012-08-07 | Intel Corporation | Hybrid memory device |
US8144506B2 (en) | 2009-06-23 | 2012-03-27 | Micron Technology, Inc. | Cross-point memory devices, electronic systems including cross-point memory devices and methods of accessing a plurality of memory cells in a cross-point memory array |
KR20110024147A (ko) * | 2009-09-01 | 2011-03-09 | 삼성전자주식회사 | 저항성 메모리 장치의 저항 드리프트를 보상할 수 있는 메모리 시스템 및 메모리 시스템의 데이터 처리 방법 |
US9208071B2 (en) * | 2010-12-13 | 2015-12-08 | SanDisk Technologies, Inc. | Apparatus, system, and method for accessing memory |
JP2012203936A (ja) | 2011-03-24 | 2012-10-22 | Toshiba Corp | 半導体記憶装置 |
EP3712774B1 (en) * | 2011-09-30 | 2023-02-15 | Tahoe Research, Ltd. | Apparatus and method for implementing a multi-level memory hierarchy |
BR112014013390A2 (pt) | 2011-12-20 | 2017-06-13 | Intel Corp | redução de potência parcial dinâmica de cache de lado de memória em hierarquia de memória de 2 níveis |
US9767032B2 (en) * | 2012-01-12 | 2017-09-19 | Sandisk Technologies Llc | Systems and methods for cache endurance |
CN103257830A (zh) * | 2012-02-17 | 2013-08-21 | 联想(北京)有限公司 | 存储单元的访问方法和存储单元 |
US9043530B1 (en) * | 2012-04-09 | 2015-05-26 | Netapp, Inc. | Data storage within hybrid storage aggregate |
US8675423B2 (en) | 2012-05-07 | 2014-03-18 | Micron Technology, Inc. | Apparatuses and methods including supply current in memory |
US9245926B2 (en) | 2012-05-07 | 2016-01-26 | Micron Technology, Inc. | Apparatuses and methods including memory access in cross point memory |
EP2870538B8 (en) * | 2012-07-03 | 2019-11-27 | Violin Systems LLC | Synchronization of a dispersed raid group |
US9395924B2 (en) * | 2013-01-22 | 2016-07-19 | Seagate Technology Llc | Management of and region selection for writes to non-volatile memory |
US9076530B2 (en) * | 2013-02-07 | 2015-07-07 | Seagate Technology Llc | Non-volatile write buffer data retention pending scheduled verification |
JP2014203405A (ja) * | 2013-04-09 | 2014-10-27 | 富士通株式会社 | 情報処理装置、メモリ制御装置、データ転送制御方法及びデータ転送制御プログラム |
GB2513377A (en) * | 2013-04-25 | 2014-10-29 | Ibm | Controlling data storage in an array of storage devices |
US9202578B2 (en) * | 2013-10-02 | 2015-12-01 | Conversant Intellectual Property Management Inc. | Vertical gate stacked NAND and row decoder for erase operation |
KR102254392B1 (ko) * | 2014-05-12 | 2021-05-25 | 삼성전자주식회사 | 메모리 컨트롤러의 동작 방법 및 불휘발성 메모리 장치 및 메모리 컨트롤러를 포함하는 불휘발성 메모리 시스템 |
KR102292172B1 (ko) * | 2014-06-23 | 2021-08-25 | 삼성전자주식회사 | 불휘발성 메모리 장치 및 메모리 컨트롤러의 동작 방법 |
US9471227B2 (en) * | 2014-07-15 | 2016-10-18 | Western Digital Technologies, Inc. | Implementing enhanced performance with read before write to phase change memory to avoid write cancellations |
KR102148889B1 (ko) * | 2014-08-18 | 2020-08-31 | 삼성전자주식회사 | 메모리 컨트롤러의 동작 방법 및 메모리 컨트롤러를 포함하는 불휘발성 메모리 시스템 |
GB2530043A (en) * | 2014-09-10 | 2016-03-16 | Ibm | Device and method for storing data in a plurality of multi-level cell memory chips |
CN105653199B (zh) * | 2014-11-14 | 2018-12-14 | 群联电子股份有限公司 | 数据读取方法、存储器存储装置及存储器控制电路单元 |
CN105607861A (zh) * | 2014-11-24 | 2016-05-25 | 中兴通讯股份有限公司 | 数据处理方法及装置 |
US20160232112A1 (en) | 2015-02-06 | 2016-08-11 | Futurewei Technologies, Inc. | Unified Memory Bus and Method to Operate the Unified Memory Bus |
US20160259732A1 (en) | 2015-03-04 | 2016-09-08 | Cavium, Inc. | Managing reuse information for memory pages |
US9965408B2 (en) * | 2015-05-14 | 2018-05-08 | Micron Technology, Inc. | Apparatuses and methods for asymmetric input/output interface for a memory |
CN105094709A (zh) * | 2015-08-27 | 2015-11-25 | 浪潮电子信息产业股份有限公司 | 一种固态盘存储系统的动态数据压缩方法 |
US9601193B1 (en) | 2015-09-14 | 2017-03-21 | Intel Corporation | Cross point memory control |
US20170139826A1 (en) * | 2015-11-17 | 2017-05-18 | Kabushiki Kaisha Toshiba | Memory system, memory control device, and memory control method |
US20170235681A1 (en) * | 2016-02-12 | 2017-08-17 | Kabushiki Kaisha Toshiba | Memory system and control method of the same |
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CN108984111B (zh) | 2021-09-14 |
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TWI684861B (zh) | 2020-02-11 |
US10068663B1 (en) | 2018-09-04 |
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