JP6680608B2 - Wiring board and manufacturing method thereof - Google Patents
Wiring board and manufacturing method thereof Download PDFInfo
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- JP6680608B2 JP6680608B2 JP2016087890A JP2016087890A JP6680608B2 JP 6680608 B2 JP6680608 B2 JP 6680608B2 JP 2016087890 A JP2016087890 A JP 2016087890A JP 2016087890 A JP2016087890 A JP 2016087890A JP 6680608 B2 JP6680608 B2 JP 6680608B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Description
本発明は、半導体素子を搭載するために用いられる配線基板およびその製造方法に関するものである。 The present invention relates to a wiring board used for mounting a semiconductor element and a method for manufacturing the wiring board.
図５に、半導体集積回路素子等の半導体素子Ｓを搭載するために用いられる従来の配線基板２０を示す。配線基板２０は、コア用の絶縁層１１ａの上下面にビルドアップ用の絶縁層１１ｂを複数積層して形成した絶縁基板１１と、この絶縁基板１１の内部および上下面に配設された銅から成る配線導体１２と、絶縁基板１１の上下面およびその上の配線導体１２上に被着されたソルダーレジスト層１３とを備えている。 FIG. 5 shows a conventional wiring board 20 used for mounting a semiconductor element S such as a semiconductor integrated circuit element. The wiring board 20 includes an insulating substrate 11 formed by stacking a plurality of build-up insulating layers 11b on upper and lower surfaces of the core insulating layer 11a, and copper provided inside and on the upper and lower surfaces of the insulating substrate 11. The wiring conductor 12 is formed, and the upper and lower surfaces of the insulating substrate 11 and the solder resist layer 13 deposited on the wiring conductor 12 thereon.
配線基板２０の上面中央部には、搭載部２０Ａが設けられている。搭載部２０Ａは、半導体素子Ｓを搭載するための四角形状の領域である。搭載部２０Ａには、多数の半導体素子接続パッド１４が二次元的な並びに配列されている。半導体素子接続パッド１４は、絶縁基板１１の上面に被着させた配線導体１２の一部を、上面側のソルダーレジスト層１３に設けた開口部から露出させることにより形成されている。半導体素子接続パッド１４上には、半田バンプ１５が溶着されている。半導体素子接続パッド１４には、半導体素子Ｓの電極Ｔが半田バンプ１５を介して接続される。 A mounting portion 20A is provided at the center of the upper surface of the wiring board 20. The mounting portion 20A is a rectangular area for mounting the semiconductor element S. A large number of semiconductor element connection pads 14 are two-dimensionally arranged on the mounting portion 20A. The semiconductor element connection pad 14 is formed by exposing a part of the wiring conductor 12 adhered to the upper surface of the insulating substrate 11 from an opening provided in the solder resist layer 13 on the upper surface side. Solder bumps 15 are welded on the semiconductor element connection pads 14. The electrode T of the semiconductor element S is connected to the semiconductor element connection pad 14 via the solder bump 15.
配線基板２０の下面は、外部電気回路基板との接続面となっている。配線基板２０の下面には、その略全領域にわたり多数の外部接続パッド１６が二次元的な並びに配列されている。外部接続パッド１６は、絶縁基板１１の下面に被着させた配線導体１２の一部を、下面側のソルダーレジスト層１３に設けた開口部から露出させることにより形成されている。外部接続パッド１６には、外部電気回路基板の配線導体に接続するための半田ボール１８Ｂが接続される。なお、外部接続パッド１６の表面には、半田ボール１８Ｂとの接続を良好とするために厚みが１〜２μｍ程度の錫から成る被覆層１７が被着されている。 The lower surface of the wiring board 20 is a connection surface with the external electric circuit board. A large number of external connection pads 16 are two-dimensionally arranged on the lower surface of the wiring board 20 over substantially the entire area thereof. The external connection pad 16 is formed by exposing a part of the wiring conductor 12 adhered to the lower surface of the insulating substrate 11 from an opening provided in the solder resist layer 13 on the lower surface side. Solder balls 18B for connecting to the wiring conductors of the external electric circuit board are connected to the external connection pads 16. The surface of the external connection pad 16 is coated with a coating layer 17 made of tin and having a thickness of about 1 to 2 μm in order to improve the connection with the solder balls 18B.
そして、この配線基板２０によれば、図６に示すように、半導体素子Ｓの電極Ｔを半導体素子接続パッド１４に半田バンプ１５を介して接続するとともに半導体素子Ｓと配線基板２０との間に熱硬化性樹脂から成る封止樹脂Ｕを充填して半導体素子Ｓを搭載し、最後に被覆層１７と半田ボール１８Ｂとを溶融一体化させて外部接続パッド１６に半田端子１８を形成することによって製品としての半導体装置が完成する。 Then, according to this wiring board 20, as shown in FIG. 6, the electrode T of the semiconductor element S is connected to the semiconductor element connection pad 14 via the solder bump 15, and between the semiconductor element S and the wiring board 20. By filling the sealing resin U made of a thermosetting resin to mount the semiconductor element S, and finally melting and integrating the coating layer 17 and the solder balls 18B to form the solder terminals 18 on the external connection pads 16. The semiconductor device as a product is completed.
ここで、配線基板２０において、半田バンプ１５および被覆層１７を形成するとともに、これを用いた半導体装置において半田端子１８を形成する方法を説明する。 Here, a method of forming the solder bumps 15 and the coating layer 17 on the wiring board 20 and forming the solder terminals 18 in the semiconductor device using the same will be described.
まず、図７Ａに要部拡大断面図で示すように、上面に配線導体１２の一部を半導体素子接続パッド１４として露出させるソルダーレジスト層１３が被着されており、下面に配線導体１２の一部を外部接続パッド１６として露出させるソルダーレジスト層１３が被着された絶縁基板１１を準備する。 First, as shown in FIG. 7A with an enlarged cross-sectional view of an essential part, a solder resist layer 13 that exposes a part of the wiring conductor 12 as a semiconductor element connection pad 14 is applied on the upper surface, and one surface of the wiring conductor 12 is exposed on the lower surface. The insulating substrate 11 to which the solder resist layer 13 exposing the portions as the external connection pads 16 is applied is prepared.
次に、図７Ｂに示すように、半導体素子接続パッド１４の表面および外部接続パッド１６の表面に錫めっき層１７Ｐを無電解錫めっきにより形成する。このとき、無電解錫めっきと銅との置換反応により半導体素子接続パッド１４用および外部接続パッド１６用の配線導体１２の一部がその表面側から若干抉られた状態となる。 Next, as shown in FIG. 7B, a tin plating layer 17P is formed on the surfaces of the semiconductor element connection pads 14 and the external connection pads 16 by electroless tin plating. At this time, a part of the wiring conductor 12 for the semiconductor element connection pad 14 and the external connection pad 16 is slightly hollowed from the surface side by the substitution reaction of the electroless tin plating and the copper.
次に、図７Ｃに示すように、半導体素子接続パッド１４に被着された錫めっき層１７Ｐ上にフラックスＦを介して半田ボール１５Ｂを載置する。 Next, as shown in FIG. 7C, the solder balls 15B are placed on the tin-plated layer 17P attached to the semiconductor element connection pads 14 via the flux F.
次に、図７Ｄに示すように、半田ボール１５Ｂを錫めっき層１７Ｐとともに加熱溶融することにより半導体素子接続パッド１４上に半田バンプ１５を形成する。このとき、外部接続パッド１６に被着された錫めっき層１７Ｐも溶融する。外部接続パッド１６上で溶融した錫めっき層１７Ｐは、厚みが１〜２μｍ程度と薄いことから、その表面張力により部分的に凝集塊が形成されて不均一な厚みとなる。このようにして、半導体素子接続パッド１４に半田バンプ１５が形成されているとともに外部接続パッド１６に錫めっき層１７Ｐが溶融固化した被覆層１７が被着した配線基板２０が形成される。 Next, as shown in FIG. 7D, the solder balls 15B are heated and melted together with the tin plating layer 17P to form the solder bumps 15 on the semiconductor element connection pads 14. At this time, the tin plating layer 17P deposited on the external connection pad 16 also melts. Since the thickness of the tin-plated layer 17P melted on the external connection pad 16 is as thin as about 1 to 2 μm, the surface tension of the tin-plated layer 17P partially forms agglomerates, resulting in an uneven thickness. In this way, the wiring board 20 is formed in which the solder bumps 15 are formed on the semiconductor element connection pads 14 and the coating layers 17 formed by melting and solidifying the tin plating layers 17P are attached to the external connection pads 16.
そして、図７Ｅに示すように、配線基板２０に半導体素子Ｓを搭載した後、外部接続パッド１６に被着させた被覆層１７上にフラックスＦを介して半田ボール１８Ｂを載置し、最後に、被覆層１７および半田ボール１８Ｂを溶融固化させて図６で示したような半田端子１８を形成する。 Then, as shown in FIG. 7E, after mounting the semiconductor element S on the wiring board 20, the solder balls 18B are placed on the coating layer 17 adhered to the external connection pads 16 via the flux F, and finally. Then, the coating layer 17 and the solder balls 18B are melted and solidified to form the solder terminals 18 as shown in FIG.
しかしながら、図７Ｆに示すように、被覆層１７と半田ボール１８Ｂとが溶融一体化せずに半田端子１８が形成されない場合がある。このような事象は、外部接続パッド１６上の溶融固化した被覆層１７に半田ボール１８Ｂを載置した際に、半田ボール１８Ｂが接触する部位の被覆層１７の厚みが薄い場合に発生しやすい傾向にある。被覆層１７の厚みが薄い部分では、錫めっき層１７Ｐが溶融した際に形成される錫と銅との金属間化合物が表面に露出しやすく、この金属間化合物と半田ボール１８Ｂとの濡れ性が良好でないことから、被覆層１７と半田ボール１８Ｂとが溶融一体化しにくいものと考えられる。 However, as shown in FIG. 7F, the coating layer 17 and the solder ball 18B may not be melt-integrated and the solder terminal 18 may not be formed. Such a phenomenon tends to occur when the solder ball 18B is placed on the molten and solidified coating layer 17 on the external connection pad 16, and the thickness of the coating layer 17 at the portion where the solder ball 18B contacts is thin. It is in. In the portion where the coating layer 17 is thin, the intermetallic compound of tin and copper formed when the tin plating layer 17P is melted is easily exposed on the surface, and the wettability between this intermetallic compound and the solder ball 18B is high. Since it is not good, it is considered that the coating layer 17 and the solder balls 18B are difficult to melt and integrate.
なお、外部接続パッドに錫めっき層を被着させた後、その上に半田ペーストを印刷し、錫めっき層と半田ペーストとを共に溶融させることにより、外部接続パッドに均一な半田層を形成することが提案されているが、この場合、錫めっき層を被着するのに加えて半田ペーストを印刷する必要があり、配線基板の製造が煩雑なものとなってしまう。 After depositing a tin plating layer on the external connection pad, a solder paste is printed on the tin plating layer and the tin plating layer and the solder paste are melted together to form a uniform solder layer on the external connection pad. However, in this case, it is necessary to print the solder paste in addition to depositing the tin plating layer, which complicates the manufacturing of the wiring board.
本発明が解決しようとする課題は、外部接続パッド上に半田端子を確実に形成することが可能な配線基板およびその製造方法を提供することにある。 The problem to be solved by the present invention is to provide a wiring board capable of reliably forming a solder terminal on an external connection pad, and a manufacturing method thereof.
本発明側の配線基板は、絶縁基板の上面に銅から成る複数の半導体素子接続パッドが形成されているとともに前記絶縁基板の下面に銅から成る複数の外部接続パッドが形成されており、前記半導体素子接続パッドの表面に半田バンプが形成されているとともに前記外部接続パッドの表面に錫を含有する被覆層が形成されて成る配線基板であって、前記被覆層は、平坦な表面を有し、該表面に形成された錫の酸化層と、該酸化層の下に形成された厚みが均一な錫の溶融固化層とを含むことを特徴とするものである。
In the wiring board of the present invention, a plurality of semiconductor element connection pads made of copper are formed on the upper surface of the insulating substrate, and a plurality of external connection pads made of copper are formed on the lower surface of the insulating substrate. A wiring board comprising a solder bump formed on the surface of an element connection pad and a coating layer containing tin formed on the surface of the external connection pad, wherein the coating layer has a flat surface, It is characterized in that it includes a tin oxide layer formed on the surface and a tin solidification layer having a uniform thickness formed under the oxide layer.
本発明の配線基板の製造方法は、上面に銅から成る複数の半導体素子接続パッドが形成されているとともに、下面に銅から成る複数の外部接続パッドが形成されている絶縁基板を準備する工程と、前記半導体素子接続パッドの表面および前記外部接続パッドの表面に平坦な表面の錫めっき層を被着させる工程と、前記外部接続パッドに被着させた前記錫めっき層の表面に熱処理により錫の酸化層を形成する工程と、前記半導体素子接続パッドの前記錫めっき層上に半田を供給した後、前記錫めっき層および前記半田を溶融固化させて、前記半導体素子接続パッドの錫めっき層および半田が一体となった半田バンプを形成するとともに、前記外部接続パッドにおける前記酸化層の下に厚みが均一な錫の溶融固化層を形成する工程と、を行うことを特徴とするものである。 A method of manufacturing a wiring board according to the present invention includes a step of preparing an insulating substrate having a plurality of semiconductor element connection pads made of copper formed on an upper surface thereof and a plurality of external connection pads made of copper formed on a lower surface thereof. A step of depositing a flat surface tin plating layer on the surface of the semiconductor element connection pad and the surface of the external connection pad, and a step of heat treating the surface of the tin plating layer deposited on the external connection pad with tin. A step of forming an oxide layer, and supplying solder onto the tin plating layer of the semiconductor element connection pad, and then melting and solidifying the tin plating layer and the solder to form a tin plating layer and solder of the semiconductor element connection pad. There be performed to form a solder bump together, the steps of thickness under the oxide layer in the external connection pads to form a fused solidified layer having a uniform tin, It is an feature.
本発明の配線基板によれば、外部接続パッドの表面に形成された被覆層は、表面が平坦であり、その表面に形成された錫の酸化層と、この錫の酸化層の下に形成された錫の溶融固化層とから成ることから、錫の溶融固化層の厚みが均一なものとなる。その結果、錫の溶融固化層が部分的に薄くなることがなく、銅と錫との金属間化合物が錫の溶融固化層の表面に露出することがない。したがって、外部接続パッドの被覆層上にフラックスを介して半田ボールを載置し、溶融固化層および半田ボールを溶融させると、フラックスにより錫の酸化層が除去されるとともに溶融した溶融固化層と半田ボールとが良好に濡れて両者が溶融一体化した半田端子を確実に形成することが可能となる。 According to the wiring board of the present invention, the coating layer formed on the surface of the external connection pad has a flat surface and is formed under the tin oxide layer formed on the surface and the tin oxide layer. And the tin melt-solidified layer, the thickness of the tin melt-solidified layer becomes uniform. As a result, the molten and solidified layer of tin is not partially thinned, and the intermetallic compound of copper and tin is not exposed on the surface of the molten and solidified layer of tin. Therefore, when the solder ball is placed on the coating layer of the external connection pad via the flux and the molten solidified layer and the solder ball are melted, the oxide layer of tin is removed by the flux and the molten molten solidified layer and the solder are melted. It is possible to reliably form a solder terminal in which the ball is well wetted and both are melted and integrated.
また、本発明の配線基板の製造方法によれば、外部接続パッドに被着させた錫めっき層の平坦な表面に熱処理により錫の酸化層を形成した後、半導体素子接続パッドの錫めっき層上に半田を供給し、次に錫めっき層および半田を溶融固化させて、半導体素子接続パッドの錫めっき層および半田が一体となった半田バンプを形成するとともに、外部接続パッドにおける被覆層の酸化層の下に錫の溶融固化層を形成することから、外部接続パッドの錫めっき層を溶融固化させる際に、錫めっき層の表面に形成された錫の酸化層は融点が高いので溶融することはなく、平坦な状態を維持したままでその下の錫めっき層を溶融固化させることができる。その結果、錫の溶融固化層が部分的に薄くなることがなく、銅と錫との金属間化合物が錫の溶融固化層の表面に露出することがない。したがって、外部接続パッドの被覆層上にフラックスを介して半田ボールを載置し、錫の溶融固化層および半田ボールを溶融させると、フラックスにより錫の酸化層が除去されるとともに溶融した錫の溶融固化層と半田ボールとが良好に濡れて両者が溶融一体化した半田端子を確実に形成することが可能な配線基板を提供することができる。 According to the method for manufacturing a wiring board of the present invention, a tin oxide layer is formed on the flat surface of the tin plating layer deposited on the external connection pad by heat treatment, and then the tin plating layer on the semiconductor element connection pad is formed. Solder to the tin plating layer and then to solidify the solder to form a solder bump in which the tin plating layer of the semiconductor element connection pad and the solder are integrated, and the oxide layer of the coating layer on the external connection pad. Since the tin melt-solidified layer is formed underneath, when the tin plated layer of the external connection pad is melt-solidified, the tin oxide layer formed on the surface of the tin plated layer has a high melting point and therefore cannot be melted. Instead, it is possible to melt and solidify the tin plating layer thereunder while maintaining the flat state. As a result, the molten and solidified layer of tin is not partially thinned, and the intermetallic compound of copper and tin is not exposed on the surface of the molten and solidified layer of tin. Therefore, when the solder ball is placed on the coating layer of the external connection pad via the flux to melt the molten and solidified layer of tin and the solder ball, the oxide layer of tin is removed by the flux and the molten tin is melted. It is possible to provide a wiring board capable of reliably forming a solder terminal in which the solidified layer and the solder ball are well wetted and melted and integrated.
次に、本発明の配線基板の実施形態例を添付の図１を参照して説明する。図１に示す配線基板１０は、コア用の絶縁層１ａの上下面にビルドアップ用の絶縁層１ｂを複数積層して形成した絶縁基板１と、この絶縁基板１の内部および上下面に配設された銅から成る配線導体２と、絶縁基板１の上下面およびその上の配線導体２上に被着されたソルダーレジスト層３とを備えている。 Next, an embodiment of the wiring board of the present invention will be described with reference to the attached FIG. The wiring substrate 10 shown in FIG. 1 is an insulating substrate 1 formed by stacking a plurality of build-up insulating layers 1b on upper and lower surfaces of a core insulating layer 1a, and is provided inside and on the upper and lower surfaces of the insulating substrate 1. A wiring conductor 2 made of copper, and a solder resist layer 3 deposited on the upper and lower surfaces of the insulating substrate 1 and the wiring conductor 2 thereon.
コア用の絶縁層１ａは、ガラスクロス入りの熱硬化性樹脂から成る。熱硬化性樹脂としては、エポキシ樹脂やビスマレイミドトリアジン樹脂等が用いられている。絶縁層１ａの厚みは、１００〜８００μｍ程度である。絶縁層１ａには、複数のスルーホール１ｃが形成されている。スルーホール１ｃの直径は、１００〜２００μｍ程度である。絶縁層１ａの上下面およびスルーホール１ｃの内壁には、配線導体２が被着されている。 The insulating layer 1a for the core is made of a thermosetting resin containing glass cloth. An epoxy resin, a bismaleimide triazine resin, or the like is used as the thermosetting resin. The thickness of the insulating layer 1a is about 100 to 800 μm. A plurality of through holes 1c are formed in the insulating layer 1a. The diameter of the through hole 1c is about 100 to 200 μm. Wiring conductors 2 are attached to the upper and lower surfaces of the insulating layer 1a and the inner walls of the through holes 1c.
ビルドアップ用の絶縁層１ｂは、ガラスクロス無しの熱硬化性樹脂から成る。熱硬化性樹脂としては、エポキシ樹脂等が用いられている。各絶縁層１ｂの厚みは、１０〜５０μｍ程度である。各絶縁層１ｂには、複数のビアホール１ｄが形成されている。ビアホール１ｄの直径は、３０〜１００μｍ程度である。各絶縁層１ｂの表面およびビアホール１ｄ内には、配線導体２が被着されている。 The build-up insulating layer 1b is made of a thermosetting resin without glass cloth. An epoxy resin or the like is used as the thermosetting resin. The thickness of each insulating layer 1b is about 10 to 50 μm. A plurality of via holes 1d are formed in each insulating layer 1b. The diameter of the via hole 1d is about 30 to 100 μm. A wiring conductor 2 is deposited on the surface of each insulating layer 1b and in the via hole 1d.
配線導体２は、絶縁層１ａの上下面においては、銅箔および銅めっき層から成り、それ以外においては、銅めっき層から成る。配線導体２の厚みは、５〜５０μｍ程度である。 The wiring conductor 2 is made of a copper foil and a copper plating layer on the upper and lower surfaces of the insulating layer 1a, and is made of a copper plating layer otherwise. The thickness of the wiring conductor 2 is about 5 to 50 μm.
ソルダーレジスト層３は、感光性の熱硬化性樹脂から成る。感光性の熱硬化性樹脂としては、アクリル変性エポキシ樹脂等が用いられる。 The solder resist layer 3 is made of a photosensitive thermosetting resin. An acrylic modified epoxy resin or the like is used as the photosensitive thermosetting resin.
配線基板１０の上面中央部には、搭載部１０Ａが設けられている。搭載部１０Ａは、半導体素子Ｓを搭載するための四角形状の領域である。搭載部１０Ａには、多数の半導体素子接続パッド４が二次元的な並びに配列されている。半導体素子接続パッド４は、絶縁基板１の上面に被着させた配線導体２の一部を、上面側のソルダーレジスト層３に設けた開口部から露出させることにより形成されている。半導体素子接続パッド４の直径は、５０〜１００μｍ程度である。半導体素子接続パッド４上には、半田バンプ５が溶着されている。半導体素子接続パッド４には、半導体素子Ｓの電極Ｔが半田バンプ５を介して接続される。 A mounting portion 10A is provided in the center of the upper surface of the wiring board 10. The mounting portion 10A is a rectangular area for mounting the semiconductor element S. A large number of semiconductor element connection pads 4 are two-dimensionally arranged on the mounting portion 10A. The semiconductor element connection pad 4 is formed by exposing a part of the wiring conductor 2 adhered to the upper surface of the insulating substrate 1 from an opening provided in the solder resist layer 3 on the upper surface side. The semiconductor element connection pad 4 has a diameter of about 50 to 100 μm. Solder bumps 5 are welded onto the semiconductor element connection pads 4. The electrode T of the semiconductor element S is connected to the semiconductor element connection pad 4 via the solder bump 5.
配線基板１０の下面は、外部電気回路基板との接続面となっている。配線基板１０の下面には、その略全領域にわたり多数の外部接続パッド６が二次元的な並びに配列されている。外部接続パッド６は、絶縁基板１の下面に被着させた配線導体２の一部を、下面側のソルダーレジスト層３に設けた開口部から露出させることにより形成されている。外部接続パッド６の直径は、２５０〜６５０μｍ程度である。外部接続パッド６には、外部電気回路基板の配線導体に接続するための半田ボール８Ｂが接続される。なお、外部接続パッド６の表面には、半田ボール８Ｂとの接続を良好とするために錫を含有する厚みが１〜２μｍ程度の被覆層７が形成されている。 The lower surface of the wiring board 10 is a connection surface with the external electric circuit board. A large number of external connection pads 6 are two-dimensionally arranged on the lower surface of the wiring board 10 over substantially the entire area thereof. The external connection pad 6 is formed by exposing a part of the wiring conductor 2 adhered to the lower surface of the insulating substrate 1 from an opening provided in the solder resist layer 3 on the lower surface side. The external connection pad 6 has a diameter of about 250 to 650 μm. Solder balls 8B for connecting to the wiring conductors of the external electric circuit board are connected to the external connection pads 6. A coating layer 7 containing tin and having a thickness of about 1 to 2 μm is formed on the surface of the external connection pad 6 in order to improve the connection with the solder ball 8B.
外部接続パッド６の表面に形成された被覆層７は、平坦な表面を有している。その平坦な表面には、錫の酸化層７ａが形成されている。酸化層７ａの厚みは、３〜５ｎｍ程度である。酸化層７ａの下には、錫の溶融固化層７ｂが形成されている。溶融固化層７ｂの厚みは、１〜２μｍ程度である。 The coating layer 7 formed on the surface of the external connection pad 6 has a flat surface. A tin oxide layer 7a is formed on the flat surface. The thickness of the oxide layer 7a is about 3 to 5 nm. A molten and solidified layer 7b of tin is formed below the oxide layer 7a. The thickness of the melt-solidified layer 7b is about 1 to 2 μm.
このように、本例の配線基板１０においては、外部接続パッド６の表面に形成された被覆層７は、表面が平坦であり、その表面に形成された錫の酸化層７ａと、この錫の酸化層７ａの下に形成された錫の溶融固化層７ｂとから成ることから、錫の溶融固化層７ｂの厚みが均一なものとなる。その結果、錫の溶融固化層７ｂが部分的に薄くなることがなく、銅と錫との金属間化合物が錫の溶融固化層７ｂの表面に露出することがない。 As described above, in the wiring board 10 of this example, the coating layer 7 formed on the surface of the external connection pad 6 has a flat surface, and the tin oxide layer 7a formed on the surface and the tin oxide layer 7a. Since the tin melt-solidified layer 7b is formed under the oxide layer 7a, the tin melt-solidified layer 7b has a uniform thickness. As a result, the molten and solidified layer 7b of tin is not partially thinned, and the intermetallic compound of copper and tin is not exposed on the surface of the molten and solidified layer 7b of tin.
そして、本例の配線基板１０によれば、図２に示すように、半導体素子Ｓの電極Ｔを半導体素子接続パッド４に半田バンプ５を介して接続するとともに半導体素子Ｓと配線基板１０との間に熱硬化性樹脂から成る封止樹脂Ｕを充填して半導体素子Ｓを搭載し、最後に外部接続パッド６の被覆層７上にフラックスを介して半田ボール８Ｂを搭載するとともに被覆層７と半田ボール８Ｂとを溶融一体化させて外部接続パッド６に半田端子８を形成することによって製品としての半導体装置が完成する。 Then, according to the wiring board 10 of this example, as shown in FIG. 2, the electrode T of the semiconductor element S is connected to the semiconductor element connection pad 4 via the solder bump 5 and the semiconductor element S and the wiring board 10 are connected. A semiconductor element S is mounted by filling a sealing resin U made of a thermosetting resin between them, and finally, a solder ball 8B is mounted on the coating layer 7 of the external connection pad 6 via a flux and a coating layer 7 is formed. The semiconductor device as a product is completed by melting and integrating the solder balls 8B and forming the solder terminals 8 on the external connection pads 6.
このとき、外部接続パッド６に形成された被覆層７における錫の酸化層７ａの下の錫の溶融固化層７ｂの厚みが均一であり、錫の溶融固化層７ｂの表面に銅と錫との金属間化合物が露出することがないことから、外部接続パッド６の被覆層７上にフラックスを介して半田ボール８Ｂを載置し、溶融固化層７ｂおよび半田ボール８Ｂの溶融温度以上に加熱すると、フラックスにより錫の酸化層７ａが除去されるとともに、溶融固化層７ｂと半田ボール８Ｂとが良好に濡れて両者が溶融一体化した半田端子８が確実に形成される。 At this time, the thickness of the tin melt-solidified layer 7b under the tin oxide layer 7a in the coating layer 7 formed on the external connection pad 6 is uniform, and the surface of the tin melt-solidified layer 7b contains copper and tin. Since the intermetallic compound is not exposed, when the solder ball 8B is placed on the coating layer 7 of the external connection pad 6 via the flux and heated to the melting temperature of the melting and solidifying layer 7b and the solder ball 8B, The oxide layer 7a of tin is removed by the flux, and the melted and solidified layer 7b and the solder ball 8B are well wetted, and the solder terminal 8 in which both are melted and integrated is reliably formed.
次に、上述した配線基板１０において、半田バンプ５および被覆層７を形成する本発明の配線基板の製造方法の実施形態例を説明する。 Next, an example of an embodiment of a method for manufacturing a wiring board of the present invention in which the solder bumps 5 and the coating layer 7 are formed on the wiring board 10 described above will be described.
まず、図３Ａに要部拡大断面図で示すように、上面に配線導体２の一部を半導体素子接続パッド４として露出させるソルダーレジスト層３が被着されており、下面に配線導体２の一部を外部接続パッド６として露出させるソルダーレジスト層３が被着された絶縁基板１を準備する。 First, as shown in an enlarged cross-sectional view of a main part in FIG. 3A, a solder resist layer 3 that exposes a part of the wiring conductor 2 as a semiconductor element connection pad 4 is deposited on the upper surface, and one surface of the wiring conductor 2 is formed on the lower surface. The insulating substrate 1 to which the solder resist layer 3 exposing the portions as the external connection pads 6 is adhered is prepared.
次に、図３Ｂに示すように、半導体素子接続パッド４の表面および外部接続パッド６の表面に平坦な表面の錫めっき層７Ｐを無電解錫めっき法により被着する。このとき、無電解錫めっきと銅との置換反応により半導体素子接続パッド４用および外部接続パッド６用の配線導体２の一部がその表面側から若干抉られた状態となる。錫めっき層７Ｐの厚みは１〜２μｍ程度とする。 Next, as shown in FIG. 3B, a tin-plated layer 7P having a flat surface is deposited on the surface of the semiconductor element connection pad 4 and the surface of the external connection pad 6 by an electroless tin plating method. At this time, a part of the wiring conductor 2 for the semiconductor element connection pad 4 and the external connection pad 6 is slightly hollowed from the surface side by the substitution reaction of the electroless tin plating and copper. The thickness of the tin plating layer 7P is about 1 to 2 μm.
次に、図３Ｃに示すように、錫めっき層７Ｐの表面に熱処理により錫の酸化層７ａを形成する。酸化層７ａの厚みは、３〜５ｎｍ程度とする。このような酸化層７ａは、例えば空気中において１５０〜２００℃の温度で１〜３時間程度熱処理することにより形成することができる。 Next, as shown in FIG. 3C, a tin oxide layer 7a is formed on the surface of the tin plating layer 7P by heat treatment. The thickness of the oxide layer 7a is about 3 to 5 nm. Such an oxide layer 7a can be formed, for example, by heat treatment in air at a temperature of 150 to 200 ° C. for about 1 to 3 hours.
次に、図３Ｄに示すように、半導体素子接続パッド４に被着された錫めっき層７Ｐ上にフラックスＦを介して半田ボール５Ｂを載置する。 Next, as shown in FIG. 3D, the solder balls 5B are placed on the tin-plated layer 7P attached to the semiconductor element connection pads 4 via the flux F.
次に、図３Ｅに示すように、半田ボール５Ｂおよび錫めっき層７Ｐの溶融温度以上に加熱して半導体素子接続パッド４の錫めっき層７Ｐと半田ボール５Ｂとが溶融一体化した半田バンプ５を形成する。このとき、半導体素子接続パッド４の錫めっき層７Ｐ上の酸化層７ａはフラックスにより除去される。同時に、外部接続パッド６に被着された錫めっき層７Ｐも酸化層７ａの下で溶融して溶融固化層７ｂとなる。このとき、外部接続パッド６においては、錫の酸化層７ａは融点が高いので溶融することはなく、平坦な状態が維持され、その下の錫めっき層７Ｐのみが溶融する。したがって、外部接続パッド６における錫の溶融固化層７ｂの厚みが均一なものとなる。その結果、錫の溶融固化層７ｂが部分的に薄くなることがなく、銅と錫との金属間化合物が錫の溶融固化層７ｂの表面に露出することがない。 Next, as shown in FIG. 3E, the solder bump 5 in which the tin plating layer 7P of the semiconductor element connection pad 4 and the solder ball 5B are fused and integrated by heating the solder ball 5B and the tin plating layer 7P at a melting temperature or higher. Form. At this time, the oxide layer 7a on the tin plating layer 7P of the semiconductor element connection pad 4 is removed by the flux. At the same time, the tin-plated layer 7P deposited on the external connection pad 6 also melts under the oxide layer 7a to become the melt-solidified layer 7b. At this time, in the external connection pad 6, since the tin oxide layer 7a has a high melting point, it does not melt, the flat state is maintained, and only the tin plating layer 7P thereunder melts. Therefore, the thickness of the molten and solidified layer 7b of tin in the external connection pad 6 becomes uniform. As a result, the molten and solidified layer 7b of tin is not partially thinned, and the intermetallic compound of copper and tin is not exposed on the surface of the molten and solidified layer 7b of tin.
このようにして、半導体素子接続パッド４に半田バンプ５が形成されているとともに外部接続パッド６に被覆層７が形成された配線基板１０が形成される。 In this way, the wiring board 10 in which the solder bumps 5 are formed on the semiconductor element connection pads 4 and the coating layer 7 is formed on the external connection pads 6 is formed.
そして、図３Ｆに示すように、配線基板１０に半導体素子Ｓを搭載した後、外部接続パッド６に被着させた被覆層７上にフラックスＦを介して半田ボール８Ｂを載置する。 Then, as shown in FIG. 3F, after mounting the semiconductor element S on the wiring board 10, the solder balls 8B are mounted on the coating layer 7 adhered to the external connection pads 6 via the flux F.
最後に、図３Ｇに示すように、半田ボール８Ｂおよび錫の溶融固化層７ｂの溶融温度以上に加熱して両者を溶融させる。このとき、酸化層７ａはフラックスＦにより除去される。また、錫の溶融固化層７ｂの表面には銅と錫との金属間化合物が露出していないことから、この溶融固化層７ｂと半田ボール８Ｂとが良好に濡れて両者が溶融一体化した半田端子８が確実に形成される。 Finally, as shown in FIG. 3G, the solder balls 8B and the molten and solidified layer 7b of tin are heated to a melting temperature or higher to melt them. At this time, the oxide layer 7a is removed by the flux F. In addition, since the intermetallic compound of copper and tin is not exposed on the surface of the molten and solidified layer 7b of tin, the molten and solidified layer 7b and the solder ball 8B are well wetted and the melted and integrated solder is formed. The terminal 8 is reliably formed.
四角平板状の絶縁基板の上面に４７４９個の半導体素子接続パッドが形成されているとともに、この絶縁基板の下面に７７３個の外部接続パッドが形成された評価用の配線基板を１００００個準備した。 14,000 wiring boards for evaluation were prepared in which 4749 semiconductor element connection pads were formed on the upper surface of a rectangular plate-shaped insulating substrate and 773 external connection pads were formed on the lower surface of this insulating substrate.
絶縁基板には、厚みが４００μｍのコア用の絶縁層の上下面に厚みが３０μｍのビルドアップ用の絶縁層をそれぞれ２層ずつ積層したものを用いた。絶縁基板の１辺の長さは２３ｍｍとした。 The insulating substrate used was one in which two build-up insulating layers each having a thickness of 30 μm were laminated on the upper and lower surfaces of the core insulating layer having a thickness of 400 μm. The length of one side of the insulating substrate was 23 mm.
コア用の絶縁層は、ガラスクロス入りのエポキシ樹脂により形成した。ビルドアップ用の絶縁層はガラスクロス無しのエポキシ樹脂により形成した。 The insulating layer for the core was formed of an epoxy resin containing glass cloth. The insulating layer for buildup was formed of epoxy resin without glass cloth.
各絶縁層の表面には銅から成る配線導体を配置した。配線導体の厚みは、コア用の絶縁層上で２０μｍ、ビルドアップ用の絶縁層上で１５μｍとした。 A wiring conductor made of copper was arranged on the surface of each insulating layer. The thickness of the wiring conductor was 20 μm on the insulating layer for core and 15 μm on the insulating layer for buildup.
最表層の絶縁層および最表層の配線導体の上には、ソルダーレジスト層を形成した。ソルダーレジスト層は感光性のエポキシ樹脂により形成した。ソルダーレジスト層の厚みは２０μｍとした。 A solder resist layer was formed on the outermost insulating layer and the outermost wiring conductor. The solder resist layer was formed of a photosensitive epoxy resin. The thickness of the solder resist layer was 20 μm.
半導体素子接続パッドは、上面側の最表層の配線導体の一部をソルダーレジスト層に設けた開口部から露出させることにより形成した。半導体素子接続パッドの直径は、８５μｍとした。半導体素子接続パッドの縦横の配列ピッチは１６０μｍとした。 The semiconductor element connection pad was formed by exposing a part of the wiring conductor of the uppermost surface layer on the upper surface side from the opening provided in the solder resist layer. The diameter of the semiconductor element connection pad was 85 μm. The vertical and horizontal arrangement pitch of the semiconductor element connection pads was 160 μm.
外部接続パッドは、下面側の最表層の配線導体の一部をソルダーレジスト層に設けた開口部から露出させることにより形成した。外部接続パッドの直径は、３５０μｍとした。外部接続パッドの縦横の配列ピッチは８００μｍとした。 The external connection pad was formed by exposing a part of the outermost wiring conductor on the lower surface side through an opening provided in the solder resist layer. The diameter of the external connection pad was 350 μm. The vertical and horizontal arrangement pitch of the external connection pads was 800 μm.
半導体素子接続パッドおよび外部接続パッドの表面には、無電解錫めっき層を形成した。錫めっき層の厚みは、１．５μｍとした。 An electroless tin plating layer was formed on the surfaces of the semiconductor element connection pad and the external connection pad. The thickness of the tin plating layer was 1.5 μm.
この評価用の配線基板１００００個のうち半数を本発明による評価用として使い、残りの半数を比較のための評価用として使った。 Half of 10000 wiring boards for evaluation were used for evaluation according to the present invention, and the other half were used for evaluation for comparison.
（本発明による評価用試料の作製）
本発明による評価用の配線基板を、空気雰囲気のオーブンに入れ、１６５℃の温度で２時間、熱処理した。このとき、錫めっき層の表面に厚みが３〜５ｎｍの錫の酸化層が形成された。
(Preparation of evaluation sample according to the present invention)
The wiring board for evaluation according to the present invention was placed in an oven in an air atmosphere and heat-treated at a temperature of 165 ° C. for 2 hours. At this time, a tin oxide layer having a thickness of 3 to 5 nm was formed on the surface of the tin plating layer.
次に、評価用の配線基板を酸素濃度８２ｐｐｍの窒素雰囲気中のトンネル炉を用いてピーク温度２３８℃でリフロー処理して錫めっき層を溶融固化させた。 Next, the wiring board for evaluation was subjected to reflow treatment at a peak temperature of 238 ° C. using a tunnel furnace in a nitrogen atmosphere having an oxygen concentration of 82 ppm to melt and solidify the tin plating layer.
（比較のための評価用試料の作製）
評価用の配線基板に熱処理を施さない以外は、本発明による評価用試料と同様にして比較のための評価用試料を作成した。比較のための評価用試料においては、錫めっき層の表面に酸化層は見られなかった。
(Preparation of evaluation sample for comparison)
An evaluation sample for comparison was prepared in the same manner as the evaluation sample according to the present invention, except that the wiring board for evaluation was not subjected to heat treatment. In the evaluation sample for comparison, no oxide layer was found on the surface of the tin-plated layer.
次に、これらの評価用試料の外部接続パッドにおける錫めっき層の表面を観察した。その結果、本発明による評価用試料では、図４Ａに示すように、溶融した錫めっきによる凝集塊は見られず、平坦な表面を有していた。これに対し、比較のための評価用試料では、図４Ｂに示すように、溶融した錫めっきによる凝集塊（黒く見える部分）が部分的に形成されていた。 Next, the surface of the tin plating layer in the external connection pads of these evaluation samples was observed. As a result, in the evaluation sample according to the present invention, as shown in FIG. 4A, no agglomerates due to the molten tin plating were found and the sample had a flat surface. On the other hand, in the evaluation sample for comparison, as shown in FIG. 4B, agglomerates (portions that appeared black) due to the molten tin plating were partially formed.
次に、これらの評価用試料の外部接続パッドにフラックスを介して半田ボールを搭載した。半田ボールは、直径が４００μｍの錫−銀−銅合金とした。フラックスは、ＲＭＡタイプを用いた。 Next, solder balls were mounted on the external connection pads of these evaluation samples via flux. The solder ball was a tin-silver-copper alloy having a diameter of 400 μm. The flux used was an RMA type.
次に、これらの評価用試料を酸素濃度８２ｐｐｍの窒素雰囲気中のトンネル炉を用いてピーク温度２３８℃でリフロー処理して外部接続パッドに半田端子を形成した。 Next, these evaluation samples were subjected to reflow treatment at a peak temperature of 238 ° C. using a tunnel furnace in a nitrogen atmosphere having an oxygen concentration of 82 ppm to form solder terminals on the external connection pads.
次に、これらの評価用試料における半田端子の有無を確認した。その結果、本発明による評価用試料においては、半田端子無しの発生が５０００個中０個（発生率０％）であったのに対し、比較のための評価用試料においては、半田端子無しの発生が５０００個中３５個（発生率０．７％）であった。 Next, the presence or absence of solder terminals in these evaluation samples was confirmed. As a result, in the evaluation sample according to the present invention, the number of occurrence of no solder terminal was 0 out of 5000 (occurrence rate: 0%), whereas in the evaluation sample for comparison, no solder terminal was generated. The number of occurrence was 35 out of 5000 (occurrence rate 0.7%).
以上の結果より、本発明の評価用試料においては、外部接続パッドに半田端子を確実に形成できることが分かる。 From the above results, it can be seen that the solder sample can be reliably formed on the external connection pad in the evaluation sample of the present invention.
１ 絶縁基板
４ 半導体素子接続パッド
５ 半田バンプ
６ 外部接続パッド
７ 被覆層
７ａ 錫の酸化層
７ｂ 錫の溶融固化層
７Ｐ 錫めっき層
DESCRIPTION OF SYMBOLS 1 Insulating substrate 4 Semiconductor element connection pad 5 Solder bump 6 External connection pad 7 Covering layer 7a Tin oxide layer 7b Tin melting and solidifying layer 7P Tin plating layer
Claims (2)
前記半導体素子接続パッドの前記錫めっき層上に半田を供給した後、前記錫めっき層および前記半田を溶融固化させて、前記半導体素子接続パッドの錫めっき層および半田が一体となった半田バンプを形成するとともに、前記外部接続パッドにおける前記酸化層の下に厚みが均一な錫の溶融固化層を形成する工程と、を行うことを特徴とする配線基板の製造方法。 A step of preparing an insulating substrate on which a plurality of semiconductor element connection pads made of copper are formed on the upper surface and a plurality of external connection pads made of copper on the lower surface; Depositing a flat surface tin plating layer on the surface of the external connection pad, and forming a tin oxide layer by heat treatment on the surface of the tin plating layer deposited on the external connection pad,
After supplying solder onto the tin plating layer of the semiconductor element connection pad, the tin plating layer and the solder are melted and solidified to form a solder bump in which the tin plating layer of the semiconductor element connection pad and the solder are integrated. And a step of forming a molten and solidified layer of tin having a uniform thickness under the oxide layer in the external connection pad.
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