JP2009239128A - Method of manufacturing wiring board - Google Patents

Method of manufacturing wiring board Download PDF

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Publication number
JP2009239128A
JP2009239128A JP2008085065A JP2008085065A JP2009239128A JP 2009239128 A JP2009239128 A JP 2009239128A JP 2008085065 A JP2008085065 A JP 2008085065A JP 2008085065 A JP2008085065 A JP 2008085065A JP 2009239128 A JP2009239128 A JP 2009239128A
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Prior art keywords
solder
solder connection
plating layer
layer
connection pads
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Japanese (ja)
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Masateru Shimogai
昌輝 下雅意
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Kyocera SLC Technologies Corp
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Kyocera SLC Technologies Corp
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Priority to JP2008085065A priority Critical patent/JP2009239128A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board which has a tin layer uniformly deposited on recognition marks for positioning a semiconductor device, thereby allowing an image recognition apparatus to accurately recognize the recognition marks so that electrodes of the semiconductor device and solder connection pads are normally connected through solder bumps. <P>SOLUTION: A method of manufacturing a wiring board includes: a step of forming solder connection pads 3 and recognition marks 5 on an upper surface of an insulating substrate 1 having wiring conductors; a step of depositing a tin plating layer 7 on the solder connection pads 3 and the recognition marks 5; a step of applying a solder paste 21 to the tin plating layer 7 on the solder connection pads 3, and of applying a flux 22 to the tin plating layer 7 on the recognition marks 5; a step of heating and melting the tin plating layer 7 and the solder paste 21 so as to form solder bumps 8 on the solder connection pads 3 and to form a tin layer 7T subjected to heating and melting on the recognition marks 5. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、半導体集積回路素子等の半導体素子を搭載するために用いられる配線基板の製造方法に関する。   The present invention relates to a method of manufacturing a wiring board used for mounting a semiconductor element such as a semiconductor integrated circuit element.

従来、半導体集積回路素子等の半導体素子を搭載するために用いられる配線基板は、例えばガラス−エポキシ板等から成る絶縁板やエポキシ樹脂等から成る絶縁層を複数層積層して成る絶縁基板の内部および表面に銅箔や銅めっき層等の導体層から成る配線導体を設けて成る。このような配線基板においては、絶縁基板の表面に設けた導体層の一部が半導体素子の電極が半田バンプを介して接続される複数の半導体素子接続用の半田接続パッドを形成している。さらに、半導体素子接続用の半田接続パッド上には半田バンプが予め溶着されており、それにより半導体素子接続用の半田接続パッドと半導体素子の電極との半田バンプを介した接続を容易なものとしている。   2. Description of the Related Art Conventionally, a wiring board used for mounting a semiconductor element such as a semiconductor integrated circuit element is an interior of an insulating substrate formed by laminating a plurality of insulating layers made of, for example, an insulating plate made of a glass-epoxy plate or an epoxy resin. And the wiring conductor which consists of conductor layers, such as copper foil and a copper plating layer, is provided in the surface. In such a wiring board, a part of the conductor layer provided on the surface of the insulating substrate forms a plurality of solder connection pads for connecting semiconductor elements to which the electrodes of the semiconductor elements are connected via solder bumps. Further, solder bumps are pre-welded on the solder connection pads for connecting the semiconductor elements, thereby facilitating connection between the solder connection pads for connecting the semiconductor elements and the electrodes of the semiconductor elements via the solder bumps. Yes.

なお、このような配線基板において半導体素子接続用の半田接続パッドに半田バンプを溶着するには、銅箔や銅めっき層等の導体層から成る半導体素子接続用の半田接続パッドの露出表面に、半田ペーストをスクリーン印刷法により印刷した後、その半田ペーストを溶融させて溶着する方法が採用されている。   In order to weld a solder bump to a solder connection pad for connecting a semiconductor element in such a wiring board, on the exposed surface of the solder connection pad for connecting a semiconductor element made of a conductor layer such as a copper foil or a copper plating layer, A method is employed in which after solder paste is printed by screen printing, the solder paste is melted and welded.

そして、この配線基板は、半田バンプが溶着された半導体素子接続用の半田接続パッドに半導体素子の電極を位置合わせした後、半導体素子の電極と半導体素子接続用の半田接続パッドとを半田バンプを溶融させて接合することにより配線基板上に半導体素子が搭載された半導体装置となる。   In this wiring board, after aligning the electrodes of the semiconductor element with the solder connection pads for connecting the semiconductor elements to which the solder bumps are welded, the solder bumps are connected to the electrodes of the semiconductor elements and the solder connection pads for connecting the semiconductor elements. By melting and joining, a semiconductor device having a semiconductor element mounted on a wiring board is obtained.

なお、このような配線基板において、半導体素子の電極を対応する半田接続パッドに位置合わせするには、一般的には画像認識装置を備えた自動機が用いられており、絶縁基板の上面に半導体素子の電極とこれに対応する半田接続パッドとを位置合わせするための基準となる半導体素子位置決め用の認識マークを設けておくとともに、この認識マークを自動機の画像認識装置で認識し、その情報を基にして自動で位置合わせする方法が採用されている。なお、半導体素子位置決め用の認識マークは、絶縁基板の表面に半田接続パッドと同じ導体層で形成されており、通常、その表面には接続パッドと同様の方法で半田が溶着されている。マークの表面に半田を溶着させることによりマークの酸化や変色を防止することができる。   In such a wiring board, in order to align the electrode of the semiconductor element with the corresponding solder connection pad, an automatic machine equipped with an image recognition device is generally used, and the semiconductor is formed on the upper surface of the insulating substrate. A recognition mark for positioning the semiconductor element is provided as a reference for aligning the electrode of the element and the corresponding solder connection pad, and this recognition mark is recognized by the image recognition device of the automatic machine, and the information A method of automatically aligning based on this is adopted. The recognition mark for positioning the semiconductor element is formed on the surface of the insulating substrate with the same conductor layer as the solder connection pad, and solder is usually welded to the surface in the same manner as the connection pad. By welding solder to the surface of the mark, the mark can be prevented from being oxidized or discolored.

ところで、近年、環境への配慮から、半導体素子の電極と配線基板の半田接続パッドとを接続する半田バンプとして鉛を含まない鉛フリー半田が使用されるようになってきている。しかしながら、鉛フリー半田は、従来の鉛含有半田に比べて銅から成る半田接続パッドに対する濡れ性が劣っており、そのため半田接続パッドの全面に良好に濡れ広がりにくい。そこで、銅から成る半田接続パッドの表面に錫めっき層を被着させ、その錫めっき層上に半田ペーストを塗布して加熱溶融させることにより半田接続パッド上に半田を良好に濡れ広がらせて半田バンプを形成する技術が採用されるようになってきている。なお、半田接続パッドの表面に錫めっき層を被着させるには一般的に置換めっき法が用いられ、これと同時に半導体素子位置決め用の認識マーク上にも錫めっき層が被着される。この場合、認識マークの表面には錫めっき層が被着され、この錫めっき層により認識マークの酸化や変色が防止されるので、認識マーク上にはあえて半田を溶着する必要はない。   In recent years, lead-free solder containing no lead has been used as a solder bump for connecting an electrode of a semiconductor element and a solder connection pad of a wiring board in consideration of the environment. However, the lead-free solder is inferior in wettability to the solder connection pad made of copper as compared with the conventional lead-containing solder, and therefore, the lead-free solder is not easily spread over the entire surface of the solder connection pad. Therefore, a tin plating layer is deposited on the surface of a solder connection pad made of copper, and a solder paste is applied on the tin plating layer and heated and melted, so that the solder is wetted and spread well on the solder connection pad. A technique for forming bumps has been adopted. In general, a displacement plating method is used to deposit the tin plating layer on the surface of the solder connection pad. At the same time, the tin plating layer is also deposited on the recognition mark for positioning the semiconductor element. In this case, a tin plating layer is deposited on the surface of the recognition mark, and oxidation or discoloration of the recognition mark is prevented by this tin plating layer, so there is no need to dare solder on the recognition mark.

しかしながら、認識マーク上に半田を溶着させない場合、錫めっき層が被着された半田接続パッド上に半田ペーストを塗布し、これを加熱溶融させて半田バンプを形成する際の熱により認識マーク上の錫めっき層が不均一に溶融してしまい、認識マーク上の錫めっき層がまだら模様となってしまいやすい。認識マーク上の錫めっき層にそのようなまだら模様があると、画像認識装置による認識マークの認識が困難となってしまうという問題を誘発した。
特開２００４−２２８１５１号公報 特開２００５−５７２３３号公報 However, when solder is not deposited on the recognition mark, a solder paste is applied on the solder connection pad to which the tin plating layer is applied, and this is heated and melted to form solder bumps by heat on the recognition mark. The tin plating layer is melted unevenly, and the tin plating layer on the recognition mark is likely to have a mottled pattern. When such a mottled pattern is present on the tin plating layer on the recognition mark, a problem that the recognition of the recognition mark by the image recognition device becomes difficult is induced.
JP 2004-228151 A JP 2005-57233 A

本発明は、かかる従来の問題点に鑑み案出されたものであり、その目的は、半導体素子位置決め用の認識マークを画像認識装置で正確に認識して半導体素子の電極と半田接続パッドとを半田バンプを介して正常に接続することが可能な配線基板の製造方法を提供することにある。   The present invention has been devised in view of such conventional problems, and an object of the present invention is to accurately recognize a recognition mark for positioning a semiconductor element with an image recognition device and to connect the electrode of the semiconductor element and the solder connection pad. An object of the present invention is to provide a method of manufacturing a wiring board that can be normally connected via solder bumps.

本発明の配線基板の製造方法は、配線導体を有する絶縁基板の上面に半導体素子の電極が半田を介して接続される半田接続パッドおよび前記半導体素子と前記半田接続パッドとの間の位置決めを行なうための認識マークを有し、前記半田接続パッドに半田バンプが溶着されているとともに前記認識マークに錫層が被着されて成る配線基板の製造方法であって、前記絶縁基板の上面に前記半田接続パッドおよび前記認識マークを形成する工程と、前記半田接続パッドおよび前記認識マークに錫めっき層を被着する工程と、前記半田接続パッド上の錫めっき層に半田ペーストを塗布するとともに前記認識マーク上の錫めっき層にフラックスを塗布する工程と、前記錫めっき層および前記半田ペーストを加熱溶融させ、前記半田接続パッド上に半田バンプを形成するとともに前記認識マーク上に加熱溶融処理された錫層を形成する工程とを有することを特徴とするものである。   In the method for manufacturing a wiring board according to the present invention, a solder connection pad in which an electrode of a semiconductor element is connected to an upper surface of an insulating substrate having a wiring conductor via solder, and positioning between the semiconductor element and the solder connection pad is performed. And a solder bump is welded to the solder connection pad, and a tin layer is attached to the recognition mark, wherein the solder is formed on an upper surface of the insulating substrate. Forming a connection pad and the recognition mark; applying a tin plating layer to the solder connection pad and the recognition mark; applying a solder paste to the tin plating layer on the solder connection pad; A step of applying a flux to the upper tin-plated layer, and heating and melting the tin-plated layer and the solder paste, and soldering on the solder connection pads It is characterized in that a step of forming a tin layer which is heated melting treatment on the recognition mark to form a pump.

本発明の配線基板の製造方法によれば、半田接続パッド上の錫めっき層に半田ペーストを塗布し、これを加熱溶融させて半田バンプを形成する際、認識マーク上の錫めっき層にフラックスを塗布しているので、このフラックスの作用により認識マーク上の錫めっき層が均一に溶融し、まだら模様となることがない。したがって画像認識装置で半導体素子位置決め用の認識マークを正確に認識することができ、半導体素子の電極と半田接続パッドとを半田バンプを介して正常に接続することが可能な配線基板を提供することができる。   According to the method for manufacturing a wiring board of the present invention, when a solder paste is applied to a tin plating layer on a solder connection pad and this is heated and melted to form a solder bump, a flux is applied to the tin plating layer on the recognition mark. Since it is applied, the tin plating layer on the recognition mark is uniformly melted by the action of the flux, and does not become a mottled pattern. Accordingly, it is possible to provide a wiring board capable of accurately recognizing a recognition mark for positioning a semiconductor element with an image recognition apparatus and capable of normally connecting the electrode of the semiconductor element and a solder connection pad via a solder bump. Can do.

次に、本発明の配線基板の製造方法の一実施形態を添付の図面に基づき説明する。図１は、本実施形態により製造される配線基板に半導体素子を搭載した場合を示す概略断面図であり、図中、１は絶縁板１ａおよび絶縁層１ｂから成る絶縁基板、２は配線導体、３は半導体素子接続用の半田接続パッド、４は外部接続用の半田接続パッド、５は半導体素子位置決め用の認識マーク、６はソルダーレジスト層、７Ｔは錫層、８は半田バンプである。なお、本例では、ガラス織物に熱硬化性樹脂を含浸させて成る絶縁板１ａの上下面に熱硬化性樹脂から成る絶縁層１ｂを２層ずつ積層して絶縁基板１を形成しており、最表層の絶縁層１ｂ上にソルダーレジスト層６が積層されている。また、絶縁基板１の上面にはそれぞれ半導体素子Ｓの電極が半田バンプ８を介して電気的に接続される半導体素子接続用の半田接続パッド３が形成されているとともに半導体素子Ｓの電極と半田接続パッド３との間に位置決めを行うための認識マーク５が形成されている。さらに絶縁基板１の下面にはそれぞれ外部電気回路基板に半田ボール（不図示）を介して電気的に接続される外部接続用の半田接続パッド４が形成されており、絶縁基板１の上面から下面にかけてはそれぞれ対応する半導体素子接続用の半田接続パッド３と外部接続用の半田接続パッド４とを互いに電気的に接続する配線導体２が絶縁板１ａおよび各絶縁層１ｂの表面に配設されている。また、絶縁板１ａおよび各絶縁層１ｂにはそれぞれ複数の貫通孔９および１１が形成されており、これらの貫通孔９および１１内に配線導体２の一部が被着されることにより上下の配線導体２が電気的に接続されている。なお、貫通孔９の内部は、穴埋め樹脂１０により充填されている。そして、半導体素子接続用の半田接続パッド３には半田バンプ８が溶着されており外部接続用の半田接続パッド４および認識マーク５には加熱溶融処理された錫層７Ｔが被着されている。   Next, an embodiment of a method for manufacturing a wiring board according to the present invention will be described with reference to the accompanying drawings. FIG. 1 is a schematic cross-sectional view showing a case where a semiconductor element is mounted on a wiring board manufactured according to the present embodiment, in which 1 is an insulating substrate composed of an insulating plate 1a and an insulating layer 1b, 2 is a wiring conductor, 3 is a solder connection pad for connecting a semiconductor element, 4 is a solder connection pad for external connection, 5 is a recognition mark for positioning the semiconductor element, 6 is a solder resist layer, 7T is a tin layer, and 8 is a solder bump. In this example, the insulating substrate 1 is formed by laminating two insulating layers 1b made of thermosetting resin on the upper and lower surfaces of an insulating plate 1a made by impregnating glass fabric with thermosetting resin, A solder resist layer 6 is laminated on the outermost insulating layer 1b. Further, on the upper surface of the insulating substrate 1, there are formed solder connection pads 3 for connecting semiconductor elements, to which the electrodes of the semiconductor elements S are electrically connected via the solder bumps 8, and the electrodes of the semiconductor elements S and the solder A recognition mark 5 for positioning between the connection pad 3 and the connection pad 3 is formed. Furthermore, solder connection pads 4 for external connection are formed on the lower surface of the insulating substrate 1 to be electrically connected to the external electric circuit substrate via solder balls (not shown). The wiring conductors 2 that electrically connect the corresponding solder connection pads 3 for connecting semiconductor elements and the solder connection pads 4 for external connection are disposed on the surfaces of the insulating plate 1a and the respective insulating layers 1b. Yes. A plurality of through holes 9 and 11 are formed in the insulating plate 1a and each insulating layer 1b, and a part of the wiring conductor 2 is attached in the through holes 9 and 11 so The wiring conductor 2 is electrically connected. The inside of the through hole 9 is filled with a hole filling resin 10. Then, solder bumps 8 are welded to the solder connection pads 3 for connecting the semiconductor elements, and a soldered tin layer 7T is attached to the solder connection pads 4 and the recognition marks 5 for external connection.

次に、上述の配線基板を本実施形態により製造する方法を説明する。まず、図２（ａ）示すように、貫通孔９を有する絶縁板１ａの上下面に貫通孔１１を有する絶縁層１ｂを２層ずつ積層して成り、絶縁板１ａの表面および貫通孔９内および各絶縁層１ｂの表面および貫通孔１１内に銅から成る配線導体２が被着された絶縁基板１の上面に、半導体素子Ｓの電極が半田バンプ８を介して電気的に接続される半導体素子接続用の半田接続パッド３および半導体素子Ｓと半田接続パッド３との位置決めを行うための認識マーク５を形成するとともに絶縁基板１の下面に外部接続用の半田接続パッド４を形成し、さらにその上にこれらの半田接続パッド３および４ならびに認識マーク５を所定の形状に露出させるソルダーレジスト層６を設ける。   Next, a method for manufacturing the above-described wiring board according to the present embodiment will be described. First, as shown in FIG. 2A, two layers of insulating layers 1b having through holes 11 are laminated on the upper and lower surfaces of the insulating plate 1a having through holes 9, and the surface of the insulating plate 1a and the inside of the through holes 9 are formed. A semiconductor in which the electrodes of the semiconductor element S are electrically connected via solder bumps 8 to the surface of each insulating layer 1b and the upper surface of the insulating substrate 1 on which the wiring conductor 2 made of copper is deposited in the through hole 11 A solder connection pad 3 for element connection and a recognition mark 5 for positioning the semiconductor element S and the solder connection pad 3 are formed, and a solder connection pad 4 for external connection is formed on the lower surface of the insulating substrate 1. A solder resist layer 6 for exposing the solder connection pads 3 and 4 and the recognition mark 5 to a predetermined shape is provided thereon.

絶縁板１ａは、例えばガラス繊維束を縦横に織り込んだガラス織物にエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂を含浸させて成り、厚みが０．３〜１．５ｍｍ程度であり、その上面から下面にかけて形成された貫通孔９は直径が０．１〜１ｍｍ程度である。このような絶縁板１ａは、ガラス織物に未硬化の熱硬化性樹脂を含浸させた絶縁シートを熱硬化させた後、これに上面から下面にかけてドリル加工を施すことにより製作される。なお、絶縁板１ａ上下面の配線導体２は、絶縁板１ａ用の絶縁シートの上下全面に厚みが３〜５０μｍ程度の銅箔を貼着しておくとともにこの銅箔を絶縁シートの硬化後にエッチング加工することにより所定のパターンに形成される。また、貫通孔９内面の配線導体２は、絶縁板１ａに貫通孔９を設けた後に、この貫通孔９内面に無電解めっき法および電解めっき法により厚みが３〜５０μｍ程度の銅めっき層を析出させることにより形成される。   The insulating plate 1a is formed, for example, by impregnating a glass fabric woven with glass fiber bundles vertically and horizontally with a thermosetting resin such as epoxy resin or bismaleimide triazine resin, and has a thickness of about 0.3 to 1.5 mm. The through hole 9 formed from the upper surface to the lower surface has a diameter of about 0.1 to 1 mm. Such an insulating plate 1a is manufactured by thermally curing an insulating sheet in which a glass fabric is impregnated with an uncured thermosetting resin, and then drilling the insulating sheet from the upper surface to the lower surface. In addition, the wiring conductor 2 on the upper and lower surfaces of the insulating plate 1a has a copper foil having a thickness of about 3 to 50 [mu] m attached to the entire upper and lower surfaces of the insulating sheet for the insulating plate 1a and is etched after the insulating sheet is cured. A predetermined pattern is formed by processing. The wiring conductor 2 on the inner surface of the through hole 9 is provided with a copper plating layer having a thickness of about 3 to 50 μm on the inner surface of the through hole 9 by an electroless plating method and an electrolytic plating method after the through hole 9 is provided in the insulating plate 1a. Formed by precipitation.

なお、貫通孔９の内部にはエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂から成る孔埋め樹脂１０が充填されている。孔埋め樹脂１０は、貫通孔９を塞ぐことにより貫通孔９の直上および直下に配線導体２および各絶縁層１ｂを形成可能とするためのものであり、未硬化のペースト状の熱硬化性樹脂を貫通孔９内にスクリーン印刷法により充填し、それを熱硬化させた後、その上下面を平坦に研磨することにより形成される。   The through hole 9 is filled with a hole filling resin 10 made of a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin. The hole-filling resin 10 is for making it possible to form the wiring conductor 2 and each insulating layer 1b immediately above and below the through-hole 9 by closing the through-hole 9, and is an uncured paste-like thermosetting resin Is filled in the through-holes 9 by screen printing, thermally cured, and then the upper and lower surfaces thereof are polished flat.

絶縁板１ａの上下面に積層された各絶縁層１ｂは、それぞれの厚みが２０〜６０μｍ程度であり、各層の上面から下面にかけて形成された貫通孔１１は直径が３０〜１００μｍ程度である。これらの各絶縁層１ｂは、配線導体２を高密度に配線するための絶縁間隔を提供するためのものである。そして、上層の配線導体２と下層の配線導体２とを貫通孔１１を介して電気的に接続することにより高密度配線が立体的に形成可能となっている。このような各絶縁層１ｂは、厚みが２０〜６０μｍ程度の未硬化の熱硬化性樹脂から成る絶縁フィルムを絶縁板１ａの上下面に貼着し、これを熱硬化させるとともにレーザ加工により貫通孔１１を穿孔し、さらにその上に同様にして次の絶縁層１ｂを順次積み重ねることによって形成される。なお、各絶縁層１ｂの表面および貫通孔１１内に被着された配線導体２は、各絶縁層１ｂを形成する毎に各絶縁層１ｂの表面および貫通孔１１内に５〜５０μｍ程度の厚みの銅めっき層を公知のセミアディティブ法等のパターン形成法により所定のパターンに被着させることによって形成される。   Each insulating layer 1b laminated on the upper and lower surfaces of the insulating plate 1a has a thickness of about 20 to 60 μm, and the through-hole 11 formed from the upper surface to the lower surface of each layer has a diameter of about 30 to 100 μm. Each of these insulating layers 1b is for providing an insulating interval for wiring the wiring conductor 2 with high density. A high-density wiring can be three-dimensionally formed by electrically connecting the upper wiring conductor 2 and the lower wiring conductor 2 via the through hole 11. Each of such insulating layers 1b has an insulating film made of an uncured thermosetting resin having a thickness of about 20 to 60 [mu] m attached to the upper and lower surfaces of the insulating plate 1a. 11 is perforated, and the next insulating layer 1b is sequentially stacked thereon in the same manner. The wiring conductor 2 deposited in the surface of each insulating layer 1b and in the through hole 11 has a thickness of about 5 to 50 μm in the surface of each insulating layer 1b and in the through hole 11 every time each insulating layer 1b is formed. These copper plating layers are formed by depositing them in a predetermined pattern by a pattern forming method such as a known semi-additive method.

また、絶縁基板１の上面に形成された半導体素子接続用の半田接続パッド３および認識マーク５ならびに絶縁基板１の下面に形成された外部接続用の半田接続パッド４は、厚みが３〜５０μｍ程度の銅めっき層から成り、半導体素子接続用の半田接続パッド３および外部接続用の半田接続パッド４は最表層の配線導体２の一部として外部に露出するように形成されている。また認識マーク５は配線導体２の一部または配線導体２から独立したパターンとして外部に露出するように形成されている。そして、半導体素子接続用の半田接続パッド３は半導体素子を接続するための端子として機能し、外部接続用の半田接続パッド４は外部電気回路に接続するための端子として機能する。また、認識マーク５は、半導体素子を搭載する際に半導体素子の電極と半田接続パッド３とを位置合わせするための基準となるものであり、例えば上面視で十字形やＬ字形、Ｔ字形、円形をしている。このような半導体素子接続用の半田接続パッド３および外部接続用の半田接続パッド４ならびに認識マーク５は、最外層の絶縁層１ｂの表面に配線導体２を形成する際にセミアディティブ法による銅めっき層を所定のパターンに被着させることにより形成される。   Further, the solder connection pads 3 and the recognition marks 5 for connecting semiconductor elements formed on the upper surface of the insulating substrate 1 and the solder connection pads 4 for external connection formed on the lower surface of the insulating substrate 1 have a thickness of about 3 to 50 μm. The solder connection pads 3 for connecting semiconductor elements and the solder connection pads 4 for external connection are formed so as to be exposed to the outside as part of the outermost wiring conductor 2. The recognition mark 5 is formed so as to be exposed to the outside as a part of the wiring conductor 2 or a pattern independent of the wiring conductor 2. The solder connection pads 3 for connecting semiconductor elements function as terminals for connecting the semiconductor elements, and the solder connection pads 4 for external connection function as terminals for connecting to an external electric circuit. The recognition mark 5 is a reference for aligning the electrode of the semiconductor element and the solder connection pad 3 when the semiconductor element is mounted. For example, the recognition mark 5 has a cross shape, an L shape, a T shape, It is circular. Such a solder connection pad 3 for connecting a semiconductor element, a solder connection pad 4 for external connection, and a recognition mark 5 are plated by a semi-additive method when the wiring conductor 2 is formed on the surface of the outermost insulating layer 1b. It is formed by depositing the layer in a predetermined pattern.

また、最表層の絶縁層１ｂの上に積層されたソルダーレジスト層６は、例えばアクリル変性エポキシ樹脂等の感光性を有する熱硬化性樹脂にシリカやタルク等のフィラーを含有させて成り、上面側のソルダーレジスト層６であれば、半導体素子接続用の半田接続パッド３および認識マーク５を所定の形状に露出させる開口部を有しているとともに、下面側のソルダーレジスト層６であれば、外部接続用の半田接続パッド４を所定の形状に露出させる開口部を有している。これらのソルダーレジスト層６は、半導体素子接続用の半田接続パッド３同士や外部接続用の半田接続パッド４同士の電気的な絶縁信頼性を高めるとともに、半導体素子接続用の半田接続パッド３や外部接続用の半田接続パッド４の絶縁層１ｂへの接合強度を大きなものとする作用をなす。このようなソルダーレジスト層６は、その厚みが１０〜５０μｍ程度であり、感光性を有するソルダーレジスト層６用の未硬化樹脂ペーストをロールコーター法やスクリーン印刷法を採用して最表層の絶縁層１ｂ上に塗布し、これを乾燥させた後、露光および現像処理を行なって半導体素子接続用の半田接続パッド３および認識マーク５や外部接続用の半田接続パッド４を所定の形状に露出させる開口部を形成した後、これを熱硬化させることによって形成される。   Further, the solder resist layer 6 laminated on the outermost insulating layer 1b is formed by adding a filler such as silica or talc to a thermosetting resin having photosensitivity such as an acrylic-modified epoxy resin. The solder resist layer 6 has an opening for exposing the solder connection pads 3 and the recognition marks 5 for connecting the semiconductor elements to a predetermined shape, and the solder resist layer 6 on the lower surface side is external. An opening for exposing the solder connection pad 4 for connection to a predetermined shape is provided. These solder resist layers 6 increase the electrical insulation reliability between the solder connection pads 3 for connecting semiconductor elements and between the solder connection pads 4 for external connection, and also for connecting the solder connection pads 3 for connecting the semiconductor elements and the outside. The bonding strength of the connecting solder connection pads 4 to the insulating layer 1b is increased. Such a solder resist layer 6 has a thickness of about 10 to 50 μm, and an uncured resin paste for the solder resist layer 6 having photosensitivity is applied to the outermost insulating layer by employing a roll coater method or a screen printing method. An opening that is applied onto 1b and dried, and then exposed and developed to expose the solder connection pads 3 for semiconductor element connection, the recognition marks 5 and the solder connection pads 4 for external connection in a predetermined shape. After the part is formed, it is formed by thermosetting it.

次に、図２（ｂ）に示すように、半導体素子接続用の半田接続パッド３および外部接続用の半田接続パッド４ならびに認識マーク５上に錫めっき層７を従来周知の置換錫めっき法により１〜２μｍの厚みにそれぞれ被着させる。   Next, as shown in FIG. 2B, a tin plating layer 7 is formed on the solder connection pads 3 for semiconductor element connection, the solder connection pads 4 for external connection, and the recognition marks 5 by a conventionally known substitution tin plating method. Each is deposited to a thickness of 1-2 μm.

次に、図３（ｃ）に示すように、半導体素子接続用の半田接続パッド３上の錫めっき層７に半田ペースト２１を塗布するとともに、外部接続用の半田接続パッド４上の錫めっき層７および認識マーク５上の錫めっき層７にフラックス２２を塗布する。半田ペースト２１およびフラックス２２の塗布には従来周知のスクリーン印刷法を用いればよい。半田ペースト２１はロジン系のフラックスおよび直径が２０μｍ以下の錫−銀合金や錫−銀−銅合金等の鉛フリー半田粉末を含んでいる。また、フラックス２２はロジン系のフラックスが好適である。なお、フラックス２２はロジン系に限らず、水溶性のものであってもよい。   Next, as shown in FIG. 3C, a solder paste 21 is applied to the tin plating layer 7 on the solder connection pads 3 for connecting the semiconductor elements, and the tin plating layer on the solder connection pads 4 for external connection. 7 and a flux 22 is applied to the tin plating layer 7 on the recognition mark 5. A conventionally well-known screen printing method may be used for applying the solder paste 21 and the flux 22. The solder paste 21 contains rosin-based flux and lead-free solder powder such as tin-silver alloy or tin-silver-copper alloy having a diameter of 20 μm or less. The flux 22 is preferably a rosin flux. The flux 22 is not limited to the rosin type and may be water-soluble.

次に、図３（ｄ）に示すように、錫めっき層７および半田ペースト２１を加熱溶融させ、半導体素子接続用の半田接続パッド３に半田バンプ８を形成するとともに外部接続用の半田接続パッド４および認識マーク５上に加熱溶融処理された錫層７Ｔを形成した後、フラックスを除去することにより本発明の製造方法による配線基板が完成する。なお、錫めっき層７および半田ペースト２１の加熱溶融は、酸素濃度が１００ｐｐｍ以下の窒素雰囲気中、２２０〜２５０℃の温度に加熱することにより行なわれる。このとき、外部接続用の半田接続パッド４上および認識マーク５上の錫めっき層７はフラックス２２で被覆されており、フラックス２２の活性によりその溶融が均一化され、その結果、錫めっき層７が加熱溶融処理された錫層７Ｔがまだら模様となることはない。したがって、本発明の配線基板の製造方法によれば、画像認識装置で認識マーク５を正確に認識することができ、半導体素子Ｓの電極と半田接続パッド３とを半田バンプ８を介して正常に接続することが可能な配線基板を提供することができる。   Next, as shown in FIG. 3 (d), the tin plating layer 7 and the solder paste 21 are heated and melted to form solder bumps 8 on the solder connection pads 3 for connecting the semiconductor elements and solder connection pads for external connection. After the tin layer 7T heated and melted is formed on the 4 and the recognition mark 5, the wiring board according to the manufacturing method of the present invention is completed by removing the flux. The tin-plated layer 7 and the solder paste 21 are heated and melted by heating to a temperature of 220 to 250 ° C. in a nitrogen atmosphere having an oxygen concentration of 100 ppm or less. At this time, the tin plating layer 7 on the solder connection pad 4 for external connection and the recognition mark 5 is covered with the flux 22, and its melting is made uniform by the activity of the flux 22, and as a result, the tin plating layer 7. The tin layer 7T that has been heat-melted is not mottled. Therefore, according to the method for manufacturing a wiring board of the present invention, the recognition mark 5 can be accurately recognized by the image recognition apparatus, and the electrodes of the semiconductor element S and the solder connection pads 3 can be normally connected via the solder bumps 8. A wiring board that can be connected can be provided.

本発明の製造方法により製造される配線基板の例を示す概略断面図である。It is a schematic sectional drawing which shows the example of the wiring board manufactured by the manufacturing method of this invention. （ａ），（ｂ）は、図１に示す配線基板を本発明により製造する方法を説明するための工程毎の概略断面図である。(A), (b) is a schematic sectional drawing for every process for demonstrating the method to manufacture the wiring board shown in FIG. 1 by this invention. （ｃ），（ｄ）は、図１に示す配線基板を本発明により製造する方法を説明するための工程毎の概略断面図である。(C), (d) is a schematic sectional drawing for every process for demonstrating the method to manufacture the wiring board shown in FIG. 1 by this invention.

符号の説明Explanation of symbols

１：絶縁基板
２：配線導体
３：半導体素子接続用の半田接続パッド
５：認識マーク
７：錫めっき層
７Ｔ：加熱溶融処理された錫層
８：半田バンプ
２１：半田ペースト
２２：フラックス 1: Insulating substrate 2: Wiring conductor 3: Solder connection pad 5 for connecting semiconductor elements 5: Recognition mark 7: Tin plating layer 7T: Heat-melted tin layer 8: Solder bump 21: Solder paste 22: Flux

Claims (1)

配線導体を有する絶縁基板の上面に半導体素子の電極が半田を介して接続される半田接続パッドおよび前記半導体素子と前記半田接続パッドとの間の位置決めを行なうための認識マークを有し、前記半田接続パッドに半田バンプが溶着されているとともに前記認識マークに錫層が被着されて成る配線基板の製造方法であって、前記絶縁基板の上面に前記半田接続パッドおよび前記認識マークを形成する工程と、前記半田接続パッドおよび前記認識マークに錫めっき層を被着する工程と、前記半田接続パッド上の錫めっき層に半田ペーストを塗布するとともに前記認識マーク上の錫めっき層にフラックスを塗布する工程と、前記錫めっき層および前記半田ペーストを加熱溶融させ、前記半田接続パッド上に半田バンプを形成するとともに前記認識マーク上に加熱溶融処理された錫層を形成する工程とを有することを特徴とする配線基板の製造方法。   A solder connection pad to which an electrode of a semiconductor element is connected via solder on an upper surface of an insulating substrate having a wiring conductor; and a recognition mark for positioning between the semiconductor element and the solder connection pad. A method of manufacturing a wiring board in which a solder bump is welded to a connection pad and a tin layer is attached to the recognition mark, wherein the solder connection pad and the recognition mark are formed on an upper surface of the insulating substrate. Applying a tin plating layer to the solder connection pad and the recognition mark; and applying a solder paste to the tin plating layer on the solder connection pad and applying a flux to the tin plating layer on the recognition mark Heating and melting the tin plating layer and the solder paste to form solder bumps on the solder connection pads and Method for manufacturing a wiring substrate characterized by having a step of forming a tin layer which is heated melting treatment on the mark.
JP2008085065A 2008-03-28 2008-03-28 Method of manufacturing wiring board Pending JP2009239128A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017199751A (en) * 2016-04-26 2017-11-02 京セラ株式会社 Wiring board and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017199751A (en) * 2016-04-26 2017-11-02 京セラ株式会社 Wiring board and method of manufacturing the same

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