JP6673354B2 - キャリア基板、積層体、電子デバイスの製造方法 - Google Patents
キャリア基板、積層体、電子デバイスの製造方法 Download PDFInfo
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- JP6673354B2 JP6673354B2 JP2017527403A JP2017527403A JP6673354B2 JP 6673354 B2 JP6673354 B2 JP 6673354B2 JP 2017527403 A JP2017527403 A JP 2017527403A JP 2017527403 A JP2017527403 A JP 2017527403A JP 6673354 B2 JP6673354 B2 JP 6673354B2
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Classifications
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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Description
また、本発明は、上記キャリア基板を含む積層体、および、電子デバイスの製造方法に関する。
コンパクション:第1ガラス基板を室温より100℃/時間で昇温し600℃で80分間の加熱処理をしてから、100℃/時間で室温まで冷却した場合の収縮率
また、第1の態様において、第1ガラス基板の歪点が700℃以上であることが好ましい。
SiO2:50〜73%
Al2O3:10.5〜24%
B2O3:0〜5%
MgO:0〜10%
CaO:0〜14.5%
SrO:0〜24%
BaO:0〜13.5%
MgO+CaO+SrO+BaO:8〜29.5%
また、第2の態様において、基板が第2ガラス基板であることが好ましい。
電子デバイス用部材付き積層体からキャリア基板を除去し、基板と電子デバイス用部材とを有する電子デバイスを得る分離工程と、を備える電子デバイスの製造方法である。
また、第3の態様において、電子デバイス用部材を形成する際にプロセス温度が450℃以上である工程を含むことが好ましい。
また、本発明によれば、上記キャリア基板を含む積層体、および、該積層体を用いた電子デバイスの製造方法を提供することもできる。
本発明者らは、キャリア基板を複数回再利用した際に、電子デバイスの歩留まりが低下していく理由について検討を行ったところ、キャリア基板の熱収縮(コンパクション)が影響していることを知見している。
図2に示すように、積層体100は、第1ガラス基板12の層と基板16の層とそれらの間に密着層14が存在する積層体である。密着層14は、その一方の面が第1ガラス基板の層に接すると共に、その他方の面が基板16の第1主面16aに接している。なお、基板16は、剥離可能に密着層14上に積層されている。
第1ガラス基板12および密着層14からなるキャリア基板10は、液晶パネルなどの電子デバイス用部材を製造する部材形成工程において、基板16を補強する補強板として機能する。
この実施態様の場合、図3に示すように、第1ガラス基板112上に基板116が配置されて、積層体110が形成される。
表面粗さ(Ra)はJIS B 0601(2001年改正)に従って測定される。
なお、積層体110中の第1ガラス基板112および基板116は、上記第1ガラス基板12および基板16と同様の構成であるため、説明を省略する。
第1ガラス基板12は、基板16を支持して補強し、後述する部材形成工程(電子デバイス用部材を製造する工程)において電子デバイス用部材の製造の際に基板16の変形、傷付き、破損などを防止する。
コンパクションが80ppm超の場合、電子デバイスの製造歩留まりが劣る。
ガラス基板の表面を研磨加工して100mm×20mmの試料を得る。該試料の表面に点状の圧痕を長辺方向に2箇所、間隔A(A=95mm)で打つ。
次に該試料を室温から600℃まで昇温速度100℃/時(=1.6℃/分)で加熱し、600℃で80分間保持した後、降温速度100℃/時で室温まで冷却する。そして、再度、圧痕間距離を測定し、その距離をBとする。このようにして得たA、Bから下記式を用いてコンパクションを算出する。なお、A、Bは光学顕微鏡を用いて測定する。
コンパクション[ppm]=(A−B)/A×106
SiO2:50〜73%
Al2O3:10.5〜24%
B2O3:0〜5%
MgO:0〜10%
CaO:0〜14.5%
SrO:0〜24%
BaO:0〜13.5%
MgO+CaO+SrO+BaO:8〜29.5%
SiO2は50%(酸化物基準の質量百分率表示、特記しないかぎり以下同じ)未満では、歪点が充分に上がらず、かつ、熱膨張係数が増大し、密度が上昇するので、50%以上が好ましい。53%以上がより好ましく、55%以上がさらに好ましく、57%以上が特に好ましい。73%超では、溶解性が低下し、脱泡性が低下するため、73%以下が好ましい。70%以下がより好ましく、67%以下がさらに好ましく、65%以下が特に好ましい。
ここで、MgO含有量は0%以上10%以下であることが好ましいが、1%以上がより好ましい。10%を超えると、失透温度が上昇するおそれがあるので、10%以下が好ましく、7%以下がより好ましく、6%以下がさらに好ましい。
ここで、CaOの含有量は0%以上14.5%以下であることが好ましいが、1%以上であることがより好ましく、3%以上がさらに好ましい。14.5%を超えると、失透温度が上昇するおそれがある。10%以下がより好ましく、7%以下がさらに好ましい。
ここで、SrO含有量は0%以上24%以下であることが好ましいが、1%以上がより好ましい。24%を超えると膨脹係数が増大するおそれがある。12%以下がより好ましく、9%以下がさらに好ましい。
一方、耐失透性を重視する場合には、1%以上が好ましく、3%以上がより好ましく、5%以上がさらに好ましい。
また、具体的な冷却手段は特に限定されず、従来公知の冷却方法であってよい。例えば温度勾配を持った加熱炉を用いる方法が挙げられる。
基板16は、第1主面16aが密着層14と接し、密着層14側とは反対側の第2主面16bに電子デバイス用部材が設けられる。つまり、基板16は、後述する電子デバイスの形成するために使用される基板である。
基板16の種類は特に制限されず、ガラス基板、樹脂基板、金属基板などが挙げられる。
また、基板16の厚さは、基板16の製造が容易であること、基板16の取り扱いが容易であることなどの理由から、0.03mm以上であることが好ましい。
密着層14は、基板16と第1ガラス基板12とを分離する操作が行われるまで基板16の位置ずれを防止すると共に、基板16などが分離操作によって破損するのを防止する。密着層14の基板16と接する表面14aは、基板16の第1主面16aに剥離可能に積層(密着)する。上述したように、密着層14は基板16の第1主面16aに弱い結合力で結合しており、その界面の剥離強度(y)は、密着層14と第1ガラス基板12との間の界面の剥離強度(x)よりも低い。
有機層としては、所定の樹脂を含む樹脂層であることが好ましい。樹脂層を形成する樹脂の種類は特に限定されず、例えば、シリコーン樹脂、ポリイミド樹脂、アクリル樹脂、ポリオレフィン樹脂、ポリウレタン樹脂、またはフッ素系樹脂等が挙げられる。いくつかの種類の樹脂を混合して用いることもできる。中でもシリコーン樹脂、ポリイミド樹脂、フッ素系樹脂が好ましい。
白金族金属系触媒(ヒドロシリル化用白金族金属触媒)は、上記オルガノアルケニルポリシロキサン中のアルケニル基と、上記オルガノハイドロジェンポリシロキサン中の水素原子とのヒドロシリル化反応を、進行・促進させるための触媒である。白金族金属系触媒としては、白金系、パラジウム系、ロジウム系などの触媒が挙げられ、特に白金系触媒として用いることが経済性、反応性の点から好ましい。
この縮合反応型シリコーンを用いて、加水分解・縮合反応(ゾルゲル反応)を進行させることにより、シリコーン樹脂を形成することができる。
ポリイミド樹脂の構造は特に制限されないが、下記式(1)で表される、テトラカルボン酸類の残基(X)とジアミン類の残基(A)とを有する繰り返し単位からなることが好ましい。
無機層を構成する材料は特に制限されないが、例えば、酸化物、窒化物、酸窒化物、炭化物、炭窒化物、珪化物および弗化物からなる群から選ばれる少なくとも1つを含むことが好ましい。なかでも、基板16の剥離性がより優れる点で、酸化物を含むことが好ましい。
なお、炭化物としては、いわゆるカーボン材料であってもよく、例えば、フェノール樹脂などの樹脂成分を焼結して得られる炭化物であってもよい。
弗化物(好ましくは、金属弗化物)としては、例えば、Mg、Y、La、Baから選ばれる1種以上の元素の弗化物が挙げられる。例えば、弗化マグネシウム(MgF2)などが挙げられる。
RaはJIS B 0601(2001年改正)に従って測定される。
本発明の第1実施態様の積層体100の製造方法は特に制限されず、公知の方法を採用できるが、通常、第1ガラス基板12上に密着層14を形成する密着層形成工程と、密着層14上に基板16を積層して積層体100とする積層工程とを有する。なお、上記密着層形成工程は、キャリア基板の製造工程に該当する。
以下、密着層形成工程、および、積層工程について詳述する。
密着層形成工程は、第1ガラス基板12上に密着層14を形成する工程である。密着層14を形成する方法は特に制限されず、公知の方法を採用でき、密着層14を構成する材料の種類によって異なる。
硬化方法は特に制限されず、使用される樹脂によって最適な硬化条件が選択される。通常、硬化方法としては、加熱処理が採用される。
例えば、フッ素系樹脂を含む密着層を作製する方法は特に制限されず、フッ素系樹脂を含む組成物を用いて密着層を作製する方法や、フッ素系のガスを用いてプラズマを照射することで対象物表面に密着層を作製する方法が挙げられる。
製造条件は、使用される材料に応じて、適宜最適な条件が選択される。
積層工程は、上記の密着層形成工程で得られた密着層14の面上に基板16を積層し、第1ガラス基板12と密着層14と基板16とをこの順で備える積層体100を得る工程である。
例えば、常圧環境下で密着層14の表面上に基板16を重ねる方法が挙げられる。なお、必要に応じて、密着層14の表面上に基板16を重ねた後、ロールやプレスを用いて密着層14に基板16を圧着させてもよい。ロールまたはプレスによる圧着により、密着層14と基板16の層との間に混入している気泡が比較的容易に除去されるので好ましい。
基板16を積層する際には、密着層14に接触する基板16の表面を十分に洗浄し、クリーン度の高い環境で積層することが好ましい。クリーン度が高いほど、基板16の平坦性は良好となるので好ましい。
本発明の積層体(上述した第1実施態様の積層体100および第2実施態様の積層体110)は、種々の用途に使用することができ、例えば、後述する表示装置用パネル、PV、薄膜2次電池、表面に回路が形成された半導体ウェハ等の電子部品を製造する用途などが挙げられる。なお、該用途では、積層体100が高温条件(例えば、500℃以上)で曝される(例えば、20分以上)場合が多い。つまり、電子デバイスを形成する際にプロセス温度が500℃以上である工程が含まれる場合が多い。
本発明においては、上述した積層体を用いて、基板と電子デバイス用部材とを含む電子デバイス(以後、適宜「部材付き基板」とも称する)が製造される。
以下では、上述した密着層を有する積層体を用いた電子デバイスの製造方法について詳述する。
以下に、各工程で使用される材料および手順について詳述する。
部材形成工程は、上記積層工程において得られた積層体100中の基板16上に電子デバイス用部材を形成する工程である。より具体的には、図4(A)に示すように、基板16の第2主面16b(露出表面)上に電子デバイス用部材20を形成し、電子デバイス用部材付き積層体22を得る。
まず、本工程で使用される電子デバイス用部材20について詳述し、その後工程の手順について詳述する。
電子デバイス用部材20は、積層体100中の基板16上に形成され電子デバイスの少なくとも一部を構成する部材である。より具体的には、電子デバイス用部材20としては、表示装置用パネル、太陽電池、薄膜2次電池、または、表面に回路が形成された半導体ウェハ等の電子部品などに用いられる部材(例えば、表示装置用部材、太陽電池用部材、薄膜2次電池用部材、電子部品用回路)が挙げられる。
上述した電子デバイス用部材付き積層体22の製造方法は特に限定されず、電子デバイス用部材の構成部材の種類に応じて従来公知の方法にて、積層体100の基板16の第2主面16b上に、電子デバイス用部材20を形成する。
なお、TFTやCFを形成する前に、必要に応じて、基板16の第2主面16bを洗浄してもよい。洗浄方法としては、周知のドライ洗浄やウェット洗浄を用いることができる。
分離工程は、図4(B)に示すように、上記部材形成工程で得られた電子デバイス用部材付き積層体22から、密着層14と基板16との界面を剥離面として、電子デバイス用部材20が積層した基板16(部材付き基板)と、キャリア基板10とに分離して、電子デバイス用部材20および基板16を含む部材付き基板(電子デバイス)24を得る工程である。
剥離時の基板16上の電子デバイス用部材20が必要な全構成部材の形成の一部である場合には、分離後、残りの構成部材を基板16上に形成することもできる。
また、キャリア基板10は、新たなガラス基板と積層して、本発明の積層体100を製造することができる。
表1は、12種類の組成のガラス基板のコンパクション等を示した表である。各成分の原料を以下に示す目標組成になるように調合し、白金坩堝を用いて1500〜1600℃の温度で溶解して溶融ガラスを得た。溶解にあたっては、白金スターラを用い撹拌しガラスの均質化を行った。次いで溶融ガラスを流し出し、板厚0.3mmの板状に成形後徐冷し、第1ガラス基板を製造した。なお、徐冷条件としては、表1に記載の平均冷却速度(℃/min)にて冷却を行った。
また、上記表中のコンパクションは100℃/時間で室温より昇温し、600℃で80分間の加熱処理を施し、100℃/時間で室温まで冷却した際のコンパクション(収縮率)を表す。これは、以下で述べる方法にて得られた計算値を示すが、上述した方法にて測定される実測値も上記表中の計算値とほぼ同じであった。
コンパクションCの計算は、ガラスの構造緩和を定式化した、以下の式を利用し、微小温度変化を与え、逐次計算することにより求めた。なお、各種パラメータ(β、τ)については、当該組成のガラスを用いて実測して得られたものを使用した。
(V(ξ)−V0)/(V∞―V0)=exp[−(ξ/τ)β]
C=106×ΔL/L=106×[1−(V(ξ)/V0)1/3]
ここで、V0は、処理時間0におけるガラスのモル体積、V∞は処理温度における平衡モル体積、V(ξ)は換算時間ξにおけるガラスのモル体積、Cはコンパクション(単位:ppm)、Lはガラスの長さ、ΔLはガラス長の処理前後における変化量、τは緩和時定数、βは緩和時定数の広がりを示すパラメータを示す。
表2は、表1のガラス基板に対して複数回(3回)の加熱処理を施してコンパクションを測定した結果を示す表である。第1ガラス基板1〜12を用いて、以下の加熱条件による加熱処理を複数回実施した際の各加熱処理後におけるガラス基板のコンパクションを計算した。1回目欄は、以下の加熱処理を1回実施した後のガラス基板のコンパクション(ppm)を表す。2回目欄は、1回目の加熱処理をしたガラス基板を室温まで冷却してから、2回目の加熱処理を実施後のコンパクションを示す。3回目欄は、2回目の加熱処理をしたガラス基板を室温まで冷却してから、3回目の加熱処理を実施後のコンパクションを示す。
ガラス基板を室温から450℃まで5分間で昇温し、その後、450℃で20分間保持した後、室温となるまで5分間で冷却し、さらに、ガラス基板を室温から600℃まで5分間で昇温し、その後、600℃で5分間保持した後、室温となるまで5分間で冷却した。
アルケニル基含有オルガノポリシロキサン(数平均分子量:2000、アルケニル基の数:2個以上)(100質量部)と、ハイドロジェンポリシロキサン(数平均分子量:2000、ハイドロシリル基の数:2個以上)(6.7質量部)と配合した。なお、アルケニル基含有オルガノポリシロキサン中のアルケニル基と、ハイドロジェンポリシロキサン中のハイドロシリル基との混合モル比(ハイドロシリル基のモル数/アルケニル基のモル数)は0.4/1であった。さらに、触媒(白金触媒)を、アルケニル基含有オルガノポリシロキサンおよびハイドロジェンポリシロキサンの合計質量(100質量部)に対し、300ppm添加した。この液を、硬化性樹脂組成物Xとする。この硬化性樹脂組成物Xを、ダイコーターを用いて第1ガラス基板1の第1主面上に塗布して、未硬化のアルケニル基含有オルガノポリシロキサンおよびハイドロジェンポリシロキサンを含む層を第1ガラス基板1上に設けた。
その後、第2ガラス基板と、シリコーン樹脂層面とを、室温下で真空プレスにより貼り合わせ、ガラス積層体Aを得た。
この際、第2ガラス基板として、無アルカリホウケイ酸ガラスからなるガラス板(縦200mm、横200mm、板厚0.2mm、線膨張係数38×10―7/℃、旭硝子社製商品名「AN100」)を使用した。
得られたガラス積層体Aにおいては、第1ガラス基板と第2ガラス基板は、シリコーン樹脂層と気泡を発生することなく密着しており、歪み状欠点もなかった。また、ガラス積層体Aにおいて、シリコーン樹脂層と第1ガラス基板の層との界面の剥離強度は、第2ガラス基板の層とシリコーン樹脂層との界面の剥離強度よりも大きかった。
電子デバイスの製造方法としては、エキシマレーザアニール法を使用した、LTPSプロセスを使用した。まず、第2ガラス基板上に保護層を形成したのち、アモルファスシリコンを成膜した。脱水素工程、レーザー照射、活性化工程を行い、かつゲート電極、ソース、ドレイン電極等の各種配線を成膜、パターニングし、層間絶縁膜等の成膜を行い、薄膜トランジスタ回路を形成した。
なお、上記電子デバイスの製造工程において、製造プロセス温度が500℃以上の工程が含まれていた。
なお、シリコーン樹脂層は第1ガラス基板と共に第2ガラス基板から分離され、該結果より、第1ガラス基板の層とシリコーン樹脂層の界面の剥離強度(x)が、シリコーン樹脂層と第2ガラス基板の界面の剥離強度(y)よりも高いことが確認された。
この処理を2回繰り返して、電子デバイスの製造を行った。
なお、複数枚のガラス積層体Aを用意して、上記処理をそれぞれ実施した。
キャリア基板の2回目および3回目の使用時の電子デバイスの製造歩留まりが1回目と同等程度の場合は「A」、製造歩留まりが低下するが実用上許容範囲内である場合は「B」、製造歩留まりが大きく低下して実用上許容できない場合を「C」とした。
12,112 第1ガラス基板
14 密着層
16,116 基板
20 電子デバイス用部材
22 電子デバイス用部材付き積層体
24 部材付き基板(電子デバイス)
100,110 積層体
Claims (13)
- 基板の表面に電子デバイス用部材を製造する際に、前記基板に貼り合せられて用いられるキャリア基板であって、
前記キャリア基板は、少なくとも第1ガラス基板を含み、
前記第1ガラス基板は、下記コンパクションが80ppm以下である、キャリア基板であって、
前記第1ガラス基板の歪点が770℃以下であり、
前記第1ガラス基板が、酸化物基準の質量百分率表示において、下記を含有するガラスからなる、キャリア基板。
SiO 2 :50〜73%
Al 2 O 3 :10.5〜24%
B 2 O 3 :0〜5%
MgO:0〜10%
CaO:0〜14.5%
SrO:0〜24%
BaO:0〜13.5%
MgO+CaO+SrO+BaO:8〜29.5%
コンパクション:前記第1ガラス基板を室温より100℃/時間で昇温し600℃で80分間の加熱処理をしてから、100℃/時間で室温まで冷却した場合の収縮率 - 前記コンパクションが70ppm以下である、請求項1に記載のキャリア基板。
- 前記第1ガラス基板の歪点が700℃以上である、請求項1または2に記載のキャリア基板。
- 前記第1ガラス基板の300nmの外部透過率が、0.5mm厚み換算で、50%以上である、請求項1〜3のいずれか1項に記載のキャリア基板。
- 前記第1ガラス基板に用いられるガラスのヤング率が77GPa以上である、請求項1〜4のいずれか1項に記載のキャリア基板。
- 前記第1ガラス基板に用いられるガラスのビッカーズ硬度が580以上である、請求項1〜5のいずれか1項に記載のキャリア基板。
- さらに、前記第1ガラス基板上に配置された密着層を含む、請求項1〜6のいずれか1項に記載のキャリア基板。
- 請求項1〜7のいずれか1項に記載のキャリア基板と、前記キャリア基板上に配置された基板とを有する、積層体。
- 前記基板が第2ガラス基板である、請求項8に記載の積層体。
- 前記基板が樹脂基板である、請求項8に記載の積層体。
- 請求項8〜10のいずれか1項に記載の積層体の前記基板の表面上に電子デバイス用部材を形成し、電子デバイス用部材付き積層体を得る部材形成工程と、
前記電子デバイス用部材付き積層体から前記キャリア基板を除去し、前記基板と前記電子デバイス用部材とを有する電子デバイスを得る分離工程と、を備える電子デバイスの製造方法。 - 前記電子デバイス用部材が低温ポリシリコン(LTPS)を含む、請求項11に記載の電子デバイスの製造方法。
- 前記電子デバイス用部材を形成する際にプロセス温度が450℃以上である工程を含む、請求項12に記載の電子デバイスの製造方法。
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