JP6672747B2 - Electronic unit, imaging device and flexible substrate - Google Patents

Description

  The present invention relates to an electronic unit, an imaging device, and a flexible substrate.

Conventionally, an electronic element module including an electronic element mounted on a substrate has been known.
However, the conventional electronic element module has a problem that noise cannot be removed.
[Prior art documents]
[Patent Document]
[Patent Document 1] Japanese Patent Application Laid-Open No. 2010-45082

  In a first aspect, an electronic unit includes a substrate, an electronic component provided on the substrate, a first wiring provided on the substrate, and configured to flow a current supplied from the first power supply to the electronic component in a first direction. A current supplied to the electronic component through the first wiring and returned from the electronic component to the first power supply is provided on the substrate along the first wiring, and a second current substantially opposite to the first direction in the vicinity of the first wiring. And a second wiring flowing in the direction of.

  In a second aspect, an electronic unit is provided on a substrate, an electronic component provided on the substrate, a first wiring provided on the substrate and flowing a current supplied from the first power supply to the electronic component, and an electronic unit provided on the substrate. A second wiring for supplying a current supplied from the electronic component to the electronic component through the first wiring and returning to the first power supply. The second wiring includes a magnetic field and an electric field due to the current flowing through the second wiring and returning to the first power supply. Is provided along the first wiring so as to face at least one of a magnetic field and an electric field caused by a current flowing through the first wiring and supplied to the electronic component.

  In a third aspect, an electronic unit includes a substrate, an image sensor provided on the substrate, the pixel device outputting a pixel signal, and an image sensor having a vertical signal line transmitting the pixel signal, and a surface of the substrate provided with the image sensor. And a wiring that flows a current supplied from a capacitor to at least one of the image sensor and another electronic component provided on the substrate in a direction substantially perpendicular to a direction in which a vertical signal line transmits a pixel signal. Is provided.

  In a fourth aspect, an imaging device includes the above electronic unit.

  In a fifth aspect, the flexible substrate is provided along the first wiring adjacent to the first wiring and a first wiring for flowing a current supplied from the first power supply to the electronic component in a first direction, And a second wiring for flowing a current supplied to the electronic component through the first wiring and returned from the electronic component to the first power supply in a second direction substantially opposite to the first direction.

  In the sixth aspect, the flexible substrate allows the first wiring to flow the current supplied from the first power supply to the electronic component, and the current supplied to the electronic component through the first wiring and returning from the electronic component to the first power supply. And a second wiring, wherein at least one of a magnetic field and an electric field due to a current flowing through the second wiring and returning to the first power supply is a magnetic field and an electric field due to a current flowing through the first wiring and supplied to the electronic component. Are provided along the first wiring so that at least one of them is canceled.

  The above summary of the present invention does not list all of the necessary features of the present invention. Further, a sub-combination of these feature groups can also be an invention.

FIG. 2 is a cross-sectional view schematically illustrating the camera 10. FIG. 2 is a top view schematically illustrating the imaging unit 40 according to the first embodiment. FIG. 4 is a cross-sectional view schematically illustrating an AA cross section of the imaging unit 40. FIG. 3 is a cross-sectional view schematically illustrating a BB cross section of the imaging unit 40. An example of a power supply pattern included in the wiring layer 214 and an example of a ground pattern included in the wiring layer 216 are schematically illustrated. FIG. 2 is a bottom view schematically showing the imaging chip 100. FIG. 2 is a diagram schematically illustrating a configuration of a circuit block formed in the imaging chip 100. It is sectional drawing which represents typically the imaging unit 2040 which concerns on 2nd Embodiment. It is sectional drawing which represents typically the imaging unit 3040 which concerns on 3rd Embodiment. It is sectional drawing which represents typically the imaging unit 4040 which concerns on 4th Embodiment. It is sectional drawing which represents typically the imaging unit 5040 which concerns on 5th Embodiment. FIG. 9 is a bottom view schematically showing the mounting board 120 on which the flexible board 600 is mounted. FIG. 4 is a cross-sectional view schematically illustrating the imaging unit 40 in a state where a flexible substrate 600 is mounted. FIG. 3 is a cross-sectional view schematically illustrating a flexible substrate 700 and an imaging unit 40. FIG. 4 is a cross-sectional view schematically illustrating a flexible substrate 800 and an imaging unit 40. FIG. 11 is a bottom view schematically showing a mounting board 6120 on which a flexible board 900 is mounted.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all combinations of the features described in the embodiments are necessarily essential to the solution of the invention.

  FIG. 1 is a cross-sectional view schematically illustrating a camera 10 according to the embodiment. The camera 10 is a single-lens reflex camera which is an example of an imaging device. The camera 10 includes a lens unit 20 and a camera body 30. The lens unit 20 is mounted on the camera body 30. The lens unit 20 has an optical system arranged along the optical axis 22 in its lens barrel, and guides an incident subject light beam to the imaging unit 40 of the camera body 30.

  In the present embodiment, the direction along the optical axis 22 is defined as the z-axis direction. That is, the direction in which the subject light beam enters the imaging chip 100 included in the imaging unit 40 is defined as the z-axis direction. Specifically, the direction in which the subject light beam enters is defined as the z-axis minus direction, and the opposite direction is defined as the z-axis plus direction. The longitudinal direction of the imaging chip 100 is defined as the x-axis direction. The lateral direction of the imaging chip 100 is defined as the y-axis direction. Specifically, the x-axis direction and the y-axis direction are determined in the directions shown in FIG. The x-axis, y-axis, and z-axis are right-handed rectangular coordinate systems. For convenience of description, the plus direction of the z-axis may be referred to as a front side, a front side, an upper side, an upper side, or the like. Also, the z-axis minus direction may be referred to as a rear side, a rear side, a lower side, a rear side, or the like. In addition, a diagram viewed from the position in the z-axis plus direction in the z-axis minus direction may be called a top view or the like. Also, a diagram viewed from the position in the z-axis minus direction in the z-axis plus direction may be called a bottom view or the like.

  The camera body 30 has a mirror unit 31 at a position in the negative z-axis direction with respect to the body-side mount 26 coupled to the lens-side mount 24. The mirror unit 31 includes a main mirror 32 and a sub mirror 33. The main mirror 32 is rotatably supported between an entrance position where the main unit 32 enters the optical path of the subject light beam emitted from the lens unit 20 and a retracted position where the main mirror 32 retreats from the optical path of the subject light beam. The sub mirror 33 is rotatably supported on the main mirror 32. The sub-mirror 33 enters the entry position together with the main mirror 32, and retreats to the retreat position together with the main mirror 32. In this way, the mirror unit 31 has an entering state in which the light beam enters the optical path of the subject light beam and a retracting state in which the mirror unit 31 is retracted from the object light beam.

  When the mirror unit 31 is in the entering state, a part of the subject light beam incident on the main mirror 32 is reflected by the main mirror 32 and guided to the focus plate 80. The focus plate 80 is arranged at a position conjugate with the imaging surface of the imaging chip 100 included in the imaging unit 40, and visualizes a subject image formed by the optical system of the lens unit 20. The subject image formed on the focus plate 80 is observed from a finder window 86 through a pentaprism 82 and a finder optical system 84.

  When the mirror unit 31 is in the entering state, of the subject light beams incident on the main mirror 32, light beams other than the subject light beam reflected by the main mirror 32 enter the sub mirror 33. Specifically, the main mirror 32 has a half mirror area, and the subject light flux transmitted through the half mirror area of the main mirror 32 enters the sub mirror 33. The sub-mirror 33 reflects the light beam incident from the half mirror area toward the imaging optical system 70. The imaging optical system 70 guides the incident light beam to a focus detection sensor 72 for detecting a focus position. The focus detection sensor 72 outputs a detection result of the focus position to the MPU 51.

  The focus plate 80, the pentaprism 82, the main mirror 32, the sub mirror 33, and the finder optical system 84 are supported by a mirror box 60 as a support member. When the mirror unit 31 is in the retracted state and the front curtain and the rear curtain of the shutter unit 38 are in the open state, the subject light flux transmitted through the lens unit 20 reaches the imaging surface of the imaging chip 100.

  The substrate 62 and the display unit 88 are sequentially arranged at a position in the z-axis minus direction of the imaging unit 40. As the display unit 88, for example, a liquid crystal panel or the like can be applied. The display surface of the display unit 88 appears on the back of the camera body 30. The display unit 88 displays an image generated from an output signal from the imaging chip 100.

  Electronic circuits such as the MPU 51 and the ASIC 52 are mounted on the board 62. The MPU 51 controls the entire camera 10. An output signal from the imaging chip 100 is output to the ASIC 52 via a flexible board such as a flexible printed board. The ASIC 52 processes an output signal output from the imaging chip 100.

  The ASIC 52 generates display image data based on an output signal from the imaging chip 100. The display unit 88 displays an image based on the display image data generated by the ASIC 52. The ASIC 52 generates recording image data based on an output signal from the imaging chip 100. The ASIC 52 generates image data for recording by performing, for example, image processing or compression processing on the output signal of the imaging chip. The image data for recording generated by the ASIC 52 is recorded on a recording medium mounted on the camera body 30. The camera body 30 has a configuration in which a recording medium can be attached and detached.

  FIG. 2 is a top view schematically illustrating the imaging unit 40 according to the first embodiment. FIG. 3 is a cross-sectional view schematically illustrating an AA cross section of the imaging unit 40. FIG. 4 is a cross-sectional view schematically illustrating a BB cross section of the imaging unit 40. The imaging unit 40 includes the imaging chip 100, the mounting board 120, the frame 140, and the cover glass 160.

  The imaging chip 100 is a CMOS image sensor or a CCD image sensor. The imaging chip 100 includes an imaging area 101 and a peripheral area 102. The imaging region 101 is formed at a central portion of the imaging chip 100 in a plane parallel to xy. In an imaging region 101 of the imaging chip 100, an imaging surface is formed by a plurality of photoelectric conversion elements that photoelectrically convert subject light. The peripheral area 102 of the imaging chip 100 is located around the imaging area 101. The peripheral region 102 of the imaging chip 100 includes a processing circuit that reads out a pixel signal obtained by photoelectric conversion in the photoelectric conversion element and performs signal processing. The processing circuit includes a circuit that converts the output pixel signal into a digital signal. The imaging chip 100 has a rectangular shape in the xy plane. The imaging chip 100 has a first short side 105a and a second short side 105b, and a first long side 106a and a second long side 106b. The first short side 105a is located in the x-axis plus direction from the second short side 105b. The first long side 106a is located in the positive y-axis direction from the second long side 106b.

  The imaging chip 100 is provided on the mounting board 120. The imaging chip 100 is mounted on the mounting substrate 120. The imaging chip 100 is mounted on a mounting board 120 by COB (Chip On Board). The imaging chip 100 is mounted on the first main surface 111 of the mounting substrate 120. The imaging chip 100 is mounted by being bonded to a mounting substrate 120.

  Specifically, the imaging chip 100 is bonded to the solder resist layer 201 of the mounting board 120. The imaging chip 100 is bonded to the solder resist layer 201 with an adhesive. The adhesive that bonds the imaging chip 100 to the mounting substrate 120 is, for example, a thermosetting adhesive. The imaging chip 100 is adhered and fixed to the mounting substrate 120 by, for example, thermally curing a thermosetting adhesive.

  The imaging chip 100 is electrically connected to the mounting substrate 120 via bonding wires including the bonding wires 110a, 110b, 110c, and 110d. The plurality of bonding wires may be collectively referred to as a bonding wire 110.

  The bonding wires 110 are mounted on the bonding leads 240 of the mounting board 120 and the imaging chip 100. The bonding wires 110 electrically connect the imaging chip 100 and the bonding leads 240 through a wire bonding step (bonding wire mounting step). The pixel signal converted into a digital signal by the processing circuit of the imaging chip 100 is output to the mounting substrate 120 via the bonding wire 110.

  The mounting substrate 120 mounts the imaging chip 100. The mounting substrate 120 includes a first layer 121, a core layer 209, and a second layer 122. The first layer 121 includes a solder resist layer 201, a wiring layer 202, an insulating layer 203, a wiring layer 204, an insulating layer 205, and a wiring layer 206. The second layer 122 includes a wiring layer 216, an insulating layer 215, a wiring layer 214, an insulating layer 213, a wiring layer 212, and a solder resist layer 211. The mounting substrate 120 is a multilayer core substrate having a core layer 209 as a core layer.

  In the mounting substrate 120, the imaging chip 100, the first layer 121, the core layer 209, and the second layer 122 are arranged along the optical axis 22 in the order of the imaging chip 100, the first layer 121, the core layer 209, and the second layer 122. It is arranged in. Specifically, on the mounting substrate 120, along the optical axis 22, the imaging chip 100, the solder resist layer 201, the wiring layer 202, the insulating layer 203, the wiring layer 204, the insulating layer 205, the wiring layer 206, the core layer 209, The wiring layer 216, the insulating layer 215, the wiring layer 214, the insulating layer 213, the wiring layer 212, and the solder resist layer 211 are arranged in this order.

  The insulating layers 203, 205, 215, and 213 are, for example, resin layers. The thickness of each of the insulating layers 203, 205, 215, and 213 is 20 μm to 50 μm. The thickness is a length in the z-axis direction.

  The wiring layer 202, the wiring layer 204, the wiring layer 206, the wiring layer 216, the wiring layer 214, and the wiring layer 212 include a wiring pattern. As a material of the wiring layers 202, 204, 206, 216, 214 and 212, an alloy of nickel and iron (for example, 42 alloy, 56 alloy), copper, aluminum, or the like can be used. The thickness of each of the wiring patterns included in the wiring layers 202, 204, 206, 216, 214, and 212 is about 10 μm to 50 μm.

  The core layer 209 is formed of a resin. When the core layer 209 is formed of a resin, the core layer 209 may be formed using, for example, FR4 or a material having a higher elastic modulus than FR4. The thickness of the core layer 209 is larger than the thickness of any of the wiring layers 202, 204, 206, 216, 214, and 212. The thickness of the core layer 209 is larger than the thickness of any of the insulating layers 203, 205, 215, and 213. Specifically, the thickness of the core layer 209 is about 0.1 mm to 0.8 mm. The rigidity of the core layer 209 is higher than the rigidity of any of the wiring layers 202, 204, 206, 216, 214 and 212. The rigidity of the core layer 209 may be higher than the rigidity of the first layer 121. The rigidity of the core layer 209 may be higher than the rigidity of the second layer 122.

  Thus, the mounting substrate 120 is a multilayer core substrate having a resin core. The thickness of the mounting substrate 120 may be about 0.3 mm to 1.0 mm as a whole.

  At least a part of the wiring layer 202 is used for a wiring pattern that receives a pixel signal output from the imaging chip 100 via the bonding wire 110. At least a part of the wiring layer 202 is used for a wiring pattern for supplying a power supply current supplied to the imaging chip 100 to the bonding wires 110. At least a part of the wiring layer 202 is used as a wiring pattern that is supplied to the imaging chip 100 as a power supply current and receives a return current output from the imaging chip 100 via the bonding wires 110.

  The wiring layer 202 includes a bonding lead 240 to which the bonding wire 110 is connected. The wiring layer 202 receives the pixel signal output from the imaging chip 100 via the bonding wire 110 by the bonding lead 240. Further, the wiring layer 202 outputs a power supply current to the imaging chip 100 to the bonding wire 110 via the bonding lead 240. In addition, the wiring layer 202 receives the return current output from the imaging chip 100 via the bonding wire 110 by the bonding lead 240.

  The wiring layer 202 is electrically connected to each of the wiring layers 204, 206, 216, 214, and 212 and vias including vias 131a, 131b, 131c, 131d, and 131e. Connected. For example, the bonding lead 240 is electrically connected to each of the wiring layer 204, the wiring layer 206, the wiring layer 216, the wiring layer 214, and the wiring layer 212 via a via.

  For example, a pixel signal output from the imaging chip 100 is transmitted to the bonding lead 240 of the wiring layer 202 via the bonding wire 110c and the bonding wire 110d, and the via electrically connects the wiring layer 202 and the wiring layer 212. The signal is transmitted to the wiring layer 212 via the via 131d and the via 131e.

  The wiring pattern included in the wiring layer 204, the wiring pattern included in the wiring layer 206, the wiring pattern included in the wiring layer 216, and the wiring pattern included in the wiring layer 214 are, for example, a part of a ground line, a power line, Can be used for some parts. That is, the wiring pattern included in the wiring layer 204, the wiring pattern included in the wiring layer 206, the wiring pattern included in the wiring layer 216, and the wiring pattern included in the wiring layer 214 are used as a ground wiring pattern and a power supply wiring pattern. Is done.

  Electronic components are mounted on the second main surface 112 of the mounting substrate 120 opposite to the first main surface 111. For example, an electronic component mounted on second main surface 112 is provided on solder resist layer 211. The electronic component mounted on second main surface 112 and wiring layer 212 are electrically connected by a lead member. The lead member is fixed to the wiring layer 212 with solder or the like. A part of the wiring layer 212 is exposed to the outside through an opening formed in the solder resist layer 211 to provide an electrode such as a land for connecting the lead member. The electronic components provided on the second main surface 112 include, for example, mechanical components such as a connector 181, passive components such as a capacitor 182 and a resistor 183, and active components such as a transistor 184 and a regulator.

  The connector 181 is electrically connected to the wiring layer 212. For example, a pixel signal transmitted from the imaging chip 100 to the wiring layer 212 via the bonding wire 110, the wiring layer 202, and the via is transmitted to the connector 181 through the wiring layer 212. For example, a flexible board is mounted on the connector 181. The flexible substrate mounted on the connector 181 transmits the pixel signal transmitted to the connector 181 to the ASIC 52.

  The flexible board attached to the connector 181 outputs power supplied to the imaging chip 100 to the connector 181. Power supplied by the flexible substrate is supplied from a battery unit included in the camera body 30. The power output from the flexible substrate to the connector 181 is output to the power supply wiring pattern directly through the wiring layer 212 or through a power supply circuit such as a regulator, and supplied to the imaging chip 100. The flexible substrate will be described later with reference to FIGS.

  In the imaging unit 40, the wiring pattern included in the wiring layer 204 and the wiring pattern included in the wiring layer 216 are used as ground wiring patterns. The wiring pattern included in the wiring layer 214 is used as a power supply wiring pattern.

  The wiring layer 204 has a ground pattern 490. The ground pattern 490 is electrically connected to the bonding wire 110a via the via 131a. The ground pattern 490 is a solid pattern.

  The wiring layer 216 has a ground pattern 400 and a ground pattern 480. The ground pattern 400 is electrically connected to the bonding wire 110b via the via 131b. The ground pattern 480 is a planar pattern. The ground pattern 480 is a substantially solid pattern. The ground pattern 480 may be electrically connected to the ground pattern 490 via a via.

  As shown in FIGS. 3 and 4, the wiring layer 214 includes a power supply pattern 300, a power supply pattern 310, a power supply pattern 320, a power supply pattern 330, a power supply pattern 340, a power supply pattern 350, and a power supply pattern 360. Have. The power supply pattern 300, the power supply pattern 310, the power supply pattern 320, the power supply pattern 330, the power supply pattern 340, the power supply pattern 350, and the power supply pattern 360 are power supply patterns independent of each other. The power supply pattern 300 is electrically connected to a bonding wire 110 for power supply current via a via. The power supply pattern 310 is electrically connected to another power supply current bonding wire 110 via another via. Similarly, the power supply pattern 320, the power supply pattern 330, the power supply pattern 340, the power supply pattern 350, and the power supply pattern 360 are electrically connected to the corresponding power supply current bonding wires 110 via vias.

  The power transmitted from the flexible board mounted on the connector 181 to the wiring layer 212 is supplied to the power supply pattern via a via 131c that electrically connects the wiring layer 212 and the power supply pattern 300 directly or via a power supply circuit. 300. The power supplied to the power supply pattern 300 is supplied to the wiring layer 202 through a via that electrically connects the power supply pattern 300 and the wiring layer 202, and is supplied to the imaging chip 100 through the bonding wire 110. Therefore, the power supply current to the imaging chip 100 is transmitted from the power supply pattern 300 to the imaging chip 100 via the via for electrically connecting the power supply pattern 300 and the wiring layer 202, the wiring layer 202, and the bonding wire 110. Supplied.

  A return current supplied from the power supply pattern 300 to the imaging chip 100 as a power supply current, and a return current output from the imaging chip 100 is output to the wiring layer 202 via the bonding wire 110b to electrically connect the wiring layer 202 and the ground pattern 400. The signal is output to the ground pattern 400 via the connecting via 131b. The return current output to the ground pattern 400 is output to the wiring layer 212 via a via that electrically connects the ground pattern 400 and the wiring layer 212.

  The power supplied from the power supply pattern 310 is supplied to the wiring layer 202 via a via that electrically connects the power supply pattern 310 and the wiring layer 202, and is supplied to the imaging chip 100 via the bonding wire 110. The return current supplied from the power supply pattern 310 to the imaging chip 100 as a power supply current and output from the imaging chip 100 is output to the ground pattern 480 or the ground pattern 490 via the via. Similarly, for the power supplied from the power supply pattern 320, the power supply pattern 330, the power supply pattern 340, the power supply pattern 350, and the power supply pattern 360 to the imaging chip 100, the return current output from the imaging chip 100 is the ground pattern 480 or the ground pattern. 490.

  The instantaneous value of the power supply current supplied from the power supply pattern 300 to the imaging chip 100 is relatively large. During the read operation of the imaging chip 100, the power supply current from the power supply pattern 300 to the imaging chip 100 changes greatly with time. For example, a power supply current supplied from the power supply pattern 300 to the imaging chip 100 is supplied to a processing circuit for CDS (correlated double sampling) of the imaging chip 100 which performs a CDS (correlated double sampling) process. The processing circuit for the CDS repeats operation and non-operation at high speed during the read operation of the imaging chip 100. The current flowing through the power supply pattern 300 and the ground pattern 400 changes according to the operation state of the processing circuit for CDS. When the processing circuit for CDS switches from the non-operation state to the operation state, a rush current flows through the power supply pattern 300 and the ground pattern 400.

  Here, the ground pattern 400 is provided corresponding to the power supply pattern 300 such that the electromagnetic wave generated by the current flowing through the power supply pattern 300 is weakened by the electromagnetic wave generated by the current flowing through the ground pattern 400. Examples of the ground pattern 400 and the power supply pattern 300 will be described later.

  The imaging chip 100 is housed in the opening 138 of the frame 140. The frame 140 is an example of a surrounding member that surrounds the imaging chip 100. The frame 140 is bonded to the mounting substrate 120. Specifically, the frame 140 is bonded to the solder resist layer 201 of the mounting board 120. The frame 140 is bonded with, for example, an adhesive. The adhesive for bonding the frame 140 to the mounting board 120 is, for example, a thermosetting adhesive. The frame 140 is adhesively mounted on the mounting substrate 120 by thermosetting a thermosetting adhesive. When mounting the frame 140 on the mounting substrate 120 in the frame mounting step, the frame 140 is mounted on the heated mounting substrate 120 by thermocompression bonding.

  The frame 140 has a first surface 141, a second surface 142, a third surface 143, a fourth surface 144, a fifth surface 145, and a sixth surface 146. The sixth surface 146 forms an opening 138. The sixth surface 146 forms an inner wall surface of the frame 140. The opening 138 is formed, for example, at a central portion in the xy plane.

  The first surface 141 is a surface that is bonded to the cover glass 160. The first surface 141 is a surface that is in contact with an end of the sixth surface 146. The first surface 141 is formed along the outer edge of the sixth surface 146. The first surface 141 is a surface substantially parallel to the xy plane.

  The second surface 142 is a surface that is in contact with an end of the first surface 141. The second surface 142 is a surface formed along the outer edge of the first surface 141. The second surface 142 has a surface substantially parallel to the yz plane and a surface substantially parallel to the xz plane.

  The third surface 143 is a surface that contacts the end of the second surface 142. The third surface 143 is a surface substantially parallel to the xy plane, and is a surface substantially parallel to the first surface 141.

  The fourth surface 144 is a surface that is in contact with the end of the third surface 143. The fourth surface 144 is a surface formed along the outer edge of the third surface 143. The fourth surface 144 has a surface substantially parallel to the yz plane and a surface substantially parallel to the xz plane.

  The fifth surface 145 is a surface that is in contact with an end of the fourth surface 144. The fifth surface 145 is a surface formed along the outer edge of the fourth surface 144. The fifth surface 145 is a surface substantially parallel to the xy plane. The fifth surface 145 is a surface substantially parallel to the first surface 141 and the third surface 143. The fifth surface 145 is a surface that is bonded to the solder resist layer 201 of the mounting board 120. The fifth surface 145 is a surface that is in contact with an end of the sixth surface 146. The fifth surface 145 is formed along the outer edge of the sixth surface 146.

  The frame 140 has a step formed by the first surface 141, the second surface 142, and the third surface 143. The frame 140 has a mounting hole 148 as a mounting portion. The frame 140 has, for example, three mounting holes 148. Each of the three mounting holes 148 is a hole penetrating from the third surface 143 to the fifth surface 145. All three mounting holes 148 are used to mount the imaging unit 40 to another structure such as the mirror box 60.

  The frame 140 is fixed to the bracket 150 by being screwed, for example, with screws via three mounting holes 148. The bracket 150 is fixed to the mirror box 60 by, for example, being screwed. Therefore, the imaging unit 40 is fixed to the mirror box 60.

  When the frame 140 and the bracket 150 are screwed with, for example, a metal screw using the mounting hole 148, heat generated when the imaging chip 100 is operating is transferred to the mirror box 60 through the screw. A heat transfer path for allowing the heat to escape can be formed.

  The frame 140 has a positioning hole 147. The frame 140 has, for example, two positioning holes 147. Each of the two positioning holes 147 is a hole penetrating from the third surface 143 to the fifth surface 145. All the positioning holes 147 are used for positioning the imaging unit 40 with respect to the imaging unit 40. One of the two positioning holes 147 is formed by a fitting hole, and the other positioning hole 147 is formed by an elongated hole.

  The frame 140 is positioned with respect to the bracket 150 using two positioning holes 147. For example, the two positioning pins provided on the bracket 150 are inserted into the two positioning holes 147, whereby the frame 140 and the bracket 150 are positioned. The frame 140 is fixed while being positioned with respect to the bracket 150. Therefore, the imaging unit 40 is fixed in a state where it is positioned on the mirror box 60. The frame 140 and the bracket 150 may be fixed to a structure other than the mirror box 60.

  Note that the imaging unit 40 may be fixed to the mirror box 60 without using the bracket 150. The imaging unit 40 may be fixed to the mirror box 60 by, for example, being screwed through three mounting holes 148.

  The cover glass 160 is used to seal the imaging chip 100. The cover glass 160 is fixed to the frame 140 so as to cover the opening 138 of the frame 140. The cover glass 160 makes the opening 138 a sealed space together with the frame 140 and the mounting board 120.

  The cover glass 160 is bonded to the frame 140. The cover glass 160 is adhered to the frame 140 with an adhesive. The adhesive for bonding the cover glass 160 to the frame 140 is, for example, a photo-curable adhesive. The photo-curable adhesive for bonding the cover glass 160 to the frame 140 is, for example, an ultraviolet-curable adhesive. The cover glass 160 is adhered and fixed to the frame 140 by curing an ultraviolet curable adhesive with ultraviolet light. As a material of the cover glass 160, borosilicate glass, quartz glass, non-alkali glass, heat-resistant glass, or the like can be used. The cover glass 160 has translucency. The thickness of the cover glass 160 is 0.5 mm to 0.8 mm.

  The cover glass 160 is fixed to the frame 140 after the imaging chip 100, the bonding wires 110, and the frame 140 are mounted on the mounting substrate 120. Since the cover glass 160 has a light-transmitting property, the cover glass 160 and the frame 140 can be bonded to each other using a photocurable adhesive. Note that the cover glass 160 is an example of a translucent member. As the translucent member, quartz or the like can be applied in addition to glass.

  Thus, a sealed space is formed by the mounting substrate 120, the frame 140, and the cover glass 160. The imaging chip 100 is disposed in a sealed space formed by the mounting substrate 120, the frame 140, and the cover glass 160. This makes the imaging chip 100 less susceptible to the external environment. For example, the imaging chip 100 is less likely to be affected by moisture existing outside the sealed space. Therefore, deterioration of the imaging chip 100 can be prevented.

  FIG. 5 schematically illustrates an example of a power supply pattern included in the wiring layer 214 and a ground pattern included in the wiring layer 216. FIG. 5A schematically shows a power supply pattern included in the wiring layer 214. FIG. 5A is a top view when the insulating layer 213 and the wiring layer 214 are taken out from the imaging unit 40. FIG. 5B schematically shows a ground pattern included in the wiring layer 216. FIG. 5B is a top view when the insulating layer 215 and the wiring layer 216 are taken out of the imaging unit 40.

  FIG. 6 is a bottom view schematically showing the mounting board 120. FIG. 6 is intended to schematically show the positional relationship between the connector 181 and the capacitor 182, and in FIG. 6, illustration of electronic components other than the connector 181 and the capacitor 182, the wiring layer 212, and the like is omitted. The connector 181 includes n terminals as lead members. Specifically, the connector 181 includes a first terminal 281, a second terminal 282, an (n-1) th terminal 283, and an nth terminal 284. The first terminal 281 and the second terminal 282 are terminal pairs located on the most positive side in the y-axis direction among the terminals of the connector 181. The (n−1) th terminal 283 and the nth terminal 284 are terminal pairs located on the most negative side in the y-axis direction among the terminals of the connector 181.

  The ground pattern 400 functions as a ground for the power supply pattern 300. The ground pattern 480 functions as a ground for the power pattern 310, the power pattern 320, the power pattern 330, the power pattern 340, the power pattern 350, and the power pattern 360.

  As shown in FIG. 5A, the power supply pattern 300 has a power supply connection part 302, a current flow part 301, and a chip connection part 303. The power supply connection portion 302 is electrically connected to the first terminal 281 of the connector 181 via a via. The chip connection part 303 is connected to the wiring layer 202 via a via.

  The current flow portion 301 is a portion between the power supply connection portion 302 and the chip connection portion 303. The current passage portion 301 extends along the y-axis direction. Specifically, the current flow portion 301 is a rectangular pattern portion having a long side along the y-axis and a short side along the x-axis. The current flow section 301 is connected to the power supply connection section 302 on the positive side of the y-axis, and connected to the chip connection section 303 on the negative side of the y-axis. That is, the plus side of the current passage portion 301 is connected to the minus side of the power supply connection portion 302, and the minus side of the current passage portion 301 is connected to the plus side of the chip connection portion 303. I do.

  At least a part of the power supply pattern 300 is located below the imaging region 101. Specifically, at least a part of the current flow part 301 is located below the imaging region 101. More specifically, when the current flow part 301 and the imaging region 101 are projected on the xy plane, at least a part of the current flow part 301 overlaps a part of the imaging region 101.

  The ground pattern 400 has a power supply connection section 402, a current flow section 401, and a chip connection section 403. The power supply connection section 402 is electrically connected to the second terminal 282 of the connector 181 via a via. The chip connection unit 403 is connected to the wiring layer 202 via a via.

  The power connection 402 is a pattern portion corresponding to the power connection 302. The chip connection unit 403 is a pattern portion corresponding to the chip connection unit 303. The current flow portion 401 is a pattern portion corresponding to the current flow portion 301.

  The current flow portion 401 is a portion between the power supply connection portion 402 and the chip connection portion 403. The current flow portion 401 extends in a direction substantially parallel to the direction in which the current flow portion 301 extends. Specifically, the current flow portion 401 extends along the y-axis direction. The current flow portion 401 is a rectangular pattern portion having a long side along the y-axis and a short side along the x-axis. The current flow portion 401 is connected to the power supply connection portion 402 on the positive side of the y-axis, and is connected to the chip connection portion 403 on the negative side of the y-axis. That is, the plus side of the current passage 401 is connected to the minus side of the power supply connection section 402, and the minus side of the current passage 401 is connected to the plus side of the chip connection 403. I do.

  At least a part of the ground pattern 400 is located below the imaging region 101. Specifically, at least a part of the current passage unit 401 is located below the imaging region 101. More specifically, when the current flow part 401 and the imaging region 101 are projected on the xy plane, at least a part of the current flow part 401 overlaps a part of the imaging region 101.

  A current supplied from the first terminal 281 of the connector 181 is supplied to the power supply pattern 300 via a via that electrically connects the first terminal 281 of the connector 181 and the first terminal 281 to the power supply connection portion 302. It flows into the power supply connection part 302. The current that has flowed into the power supply connection part 302 flows out of the power supply connection part 302 from the negative side of the y-axis, and flows into the current flow part 301 into the positive side of the y-axis. The current that has flowed into the current flow part 301 flows through the current flow part 301 in the negative y-axis direction, flows out of the current flow part 301 from the negative side of the y-axis, and flows into the chip connection part 303. The current flowing into the chip connection unit 303 is supplied to the peripheral region 102 of the imaging chip 100 via a via connecting the chip connection unit 303 and the wiring layer 202, the wiring layer 202, and the bonding wires 110. Specifically, the current flowing into the chip connection unit 303 is supplied to a processing circuit provided in the peripheral region 102, and the processing circuit is driven by the current supplied through the chip connection unit 303. The processing circuit will be described later. The return current supplied to the peripheral region 102 and returned from the peripheral region 102 flows into the chip connecting portion 403 via the via connecting the wiring layer 202 and the chip connecting portion 303.

  The current that has flowed into the chip connection portion 403 flows out from the plus side of the y-axis of the chip connection portion 403 and flows into the minus side of the y-axis of the current flow portion 401. The current that has flowed into the current flow part 401 flows through the current flow part 401 in the plus direction of the y-axis, flows out from the plus side of the current flow part 401 along the y-axis, and flows into the power supply connection part 402. The current flowing into the power supply connection portion 402 flows into the second terminal 282 via a via connecting the power supply connection portion 402 and the second terminal 282.

  As shown in FIGS. 3, 4, and 5, the current passage portion 401 is provided along the current passage portion 301, and the current passage portion 301 and the current passage portion 401 are provided substantially in parallel. I have. The current passage section 401 is provided such that at least a part of the surface of the current passage section 401 and at least a part of the surface of the power supply pattern face each other. Specifically, when the current passage 401 and the current passage 301 are projected on the xy plane, a region occupied by the current passage 401 in the xy plane and a region occupied by the current passage 301 in the xy plane are as follows. At least some overlap. When projected on the xy plane, the region where the current passage portion 401 and the current passage portion 301 overlap each other is at least one of the y-axis plus side of the current passage portion 301 and the current passage portion 401, and the current passage portion 301 and A region extending between at least one of the current flow portions 401 and the negative side of the y-axis is formed. In addition, when the current flow part 401, the current flow part 301, and the imaging area 101 are projected on the xy plane, a part of the area occupied by the current flow part 401 and a part of the area occupied by the current flow part 301 And a part of the area occupied by the imaging area 101 overlaps with each other.

  As described above, the current flow part 301 and the current flow part 401 are in a positional relationship where at least a part thereof overlaps when projected on the xy plane. The current passage 301 and the current passage 401 extend in parallel. The direction in which the current flows through the current flow section 401 is opposite to the direction in which the current flows through the current flow section 301, and the magnitude of the current flowing through the current flow section 301 is the magnitude of the current flowing through the current flow section 401. Substantially equal to size. Therefore, the current flow section 301 and the power supply connection section 302 have a pattern configuration that provides a pair of balanced differential lines. In addition, the current flow portion 301 and the current flow portion 401 are provided in adjacent wiring layers. Thus, the current flow section 301 and the current flow section 401 provide a pair of tightly coupled balanced differential lines. Therefore, it is possible to suppress the effect of the electromagnetic field generated by the current flowing through the current flow part 301 and the current flowing through the current flow part 401 on the imaging chip 100.

  More specifically, concentric magnetic lines of force are generated from each of the current passage portions 301 and 401 in a plane parallel to the xz plane. However, as described above, since the pair of balanced differential lines are provided by the current flow portion 301 and the current flow portion 401, the concentric magnetic fields generated by the current flow portion 301 and the current flow portion 401, respectively. Works in the direction of cancellation. That is, the magnetic field generated by the current flowing through the current flow section 301 is strongly canceled by the magnetic field generated by the current flowing through the current flow section 401.

  Further, as described above, the current supplied by the power supply pattern 300 changes greatly with time. Here, in general, a fringe electric field in which lines of electric force are freely dissipated is formed from a line provided alone. However, since the current flow part 301 and the current flow part 401 provide a pair of balanced differential lines that are tightly coupled, the lines of electric force dissipated from each work to combine, and the combined electric field causes the current flow. It does not propagate beyond the vicinity of the flow portion 301 and the current flow portion 401. The floating fringe electric field can reach relatively far, but its electromagnetic energy is very small. Further, since the wiring layer 204 has a solid ground pattern, it is possible to suppress the floating fringe electric field from reaching the imaging chip 100. Therefore, the electromagnetic field energy transmitted to the imaging chip 100 can be remarkably reduced as compared with the case where, for example, each of the current flow portion 301 and the current flow portion 401 is provided as a single line or a single solid pattern. Therefore, for example, noise superimposed on the pixel signal of the imaging chip 100 can be reduced.

  The current flow portion 301 is an example of a wiring provided on the mounting substrate 120 and flowing a current supplied from the power supply to the imaging chip 100 in the first direction. In addition, the current passing unit 401 is provided on the mounting substrate 120 along the current passing unit 301, and supplies a current supplied to the imaging chip 100 through the current passing unit 301 and returned from the imaging chip 100 to the power supply to the first. This is an example of a wiring flowing in a second direction substantially opposite to the direction.

  The current supplied from the power supply pattern 310 to the wiring layer 202 via the via is supplied to the imaging chip 100 via the bonding wire 110, and the return current from the imaging chip 100 is supplied to the ground via the bonding wire 110. The signal is output to the wiring layer 202 to which the pattern 480 is connected. The return current output to the wiring layer 202 is returned to the ground pattern 480 via the via. Similarly, the current supplied to the imaging chip 100 from the power supply pattern 320, the power supply pattern 330, the power supply pattern 340, the power supply pattern 350, and the power supply pattern 360 is also returned to the ground pattern 480.

  The ground pattern 480 is a pattern formed in a planar shape and does not have a pattern configuration for providing a specific line. Further, the power supply pattern 320 and the power supply pattern 350 are also formed in a planar shape, and do not substantially provide a unidirectional current path. The power patterns 310, 330, and 340 are not planar patterns, but do not substantially provide a unidirectional current path.

  However, the magnitude of the instantaneous value of the current supplied from the power supply pattern 310, the power supply pattern 320, the power supply pattern 330, the power supply pattern 340, the power supply pattern 350, and the power supply pattern 360 to the imaging chip 100 is different from the power supply pattern 300 to the imaging chip 100. The magnitude of the instantaneous value of the supplied current is small, and the temporal change rate is small. Therefore, the energy of the electromagnetic field generated by the current flowing through the power supply pattern 310, the power supply pattern 320, the power supply pattern 330, the power supply pattern 340, the power supply pattern 350 and the power supply pattern 360, and the current flowing through the ground pattern 480 and transmitted to the imaging chip 100 is: Relatively small. Therefore, noise superimposed on a pixel signal or the like of the imaging chip 100 due to a power supply current from these power supply patterns is relatively small.

  Note that a capacitor 182 is electrically connected between the current flow part 301 and the current flow part 401. Specifically, the capacitor 182 electrically connects the current flow portion 301 and the current flow portion 401 in the vicinity of the y-axis minus end of the current flow portion 301 and the current flow portion 401. I do. More specifically, one terminal of the capacitor 182 is electrically connected to the current flow part 301 via a via near the boundary between the current flow part 301 and the chip connection part 303. The other terminal of the capacitor 182 is electrically connected to the current flow portion 401 via a via near the boundary between the current flow portion 401 and the chip connection portion 403.

  Capacitor 182 accumulates electric charge supplied from a power supply via connector 181. When the processing circuit unit 540 in the peripheral region 102 starts operating, charge can be promptly supplied from the capacitor 182 to the processing circuit unit 540. Immediately after the processing circuit unit 540 in the peripheral area 102 starts operating, most of the current supplied to the processing circuit unit 540 is supplied by discharging the capacitor 182. The electric charge corresponding to the discharge of the capacitor 182 is gradually supplied to the capacitor 182 by the current supplied from the connector 181.

  As described above, according to the imaging unit 40, since the capacitor 182 is provided near the chip connection unit 303 and the chip connection unit 403, the path through which a large current flows can be shortened. Therefore, noise superimposed on a pixel signal or the like of the imaging chip 100 can be suppressed.

  FIG. 7 is a diagram schematically illustrating a configuration of a circuit block formed on the imaging chip 100. In the imaging area 101 of the imaging chip 100, a pixel portion 500 is formed. In the peripheral region 102, a peripheral circuit section 570 is formed. The peripheral circuit section 570 includes a processing circuit section 540, a drive signal generation section 560, a scanning circuit section 580a, a scanning circuit section 580b, and an output circuit section 590.

  The pixel portion 500 has N × M unit cells 501. The unit cells 501 are two-dimensionally arranged in the xy plane. For example, the unit cells 501 are arranged in a matrix in the xy plane. Each of the unit cells 501 is provided at a position corresponding to a corresponding one of columns 1 to M in a corresponding one of rows 1 to N. Each of the unit cells 501 includes a circuit such as a photoelectric conversion element and a transistor that performs a reset operation and a read operation of accumulated charge accumulated in the photoelectric conversion element. An imaging unit is formed by the photoelectric conversion region formed by the N × M unit cells 501.

  The scanning circuit portion 580a and the scanning circuit portion 580b perform read-out scanning of the pixel portion 500. The scanning circuit portion 580b drives the unit cell 501 and the processing circuit portion 540 to output a signal obtained by photoelectric conversion of a photoelectric conversion element included in the unit cell 501. The unit cell 501 outputs a pixel signal of an analog signal indicating the amount of light received by the unit cell 501.

  The processing circuit unit 540 performs signal processing on a signal output from the unit cell 501 under the control of the scanning circuit unit 580a. The processing circuit unit 540 has a conversion circuit 550 including a comparator 551 and a counter 552. The conversion circuit 550 performs CDS and AD conversion processing. The processing circuit unit 540 performs so-called digital CDS. The output circuit unit 590 outputs the pixel signal of the digital signal obtained by the processing circuit unit 540 to the mounting board 120.

  Specifically, the scanning circuit unit 580b is electrically connected to the plurality of unit cells 501 via the row reset lines 510-1 to 510-N. The scanning circuit unit 580b is electrically connected to the plurality of unit cells 501 via the row selection lines 520-1 to 520-N. The scanning circuit unit 580b includes a shift register and the like.

  The processing circuit unit 540 includes comparators 551-1 to 551-M and counters 552-1 to 552-M. The analog signal output from the unit cell 501 is input to the comparators 551-1 to 551-M via the vertical signal lines 530-1 to 530-M. Further, a ramp voltage as a reference voltage is input to the comparators 551-1 to 551-M.

  Each of the unit cells 501 is connected to a row reset line 510 of a row corresponding to each unit cell 501 among the row reset lines 510-1 to 510-N. Each of the unit cells 501 is connected to a row selection line 520 of a row corresponding to each of the unit cells 501 among the row selection lines 520-1 to 520-N. Each of the unit cells 501 is connected to a vertical signal line 530 in a column corresponding to each of the unit cells 501 among the vertical signal lines 530-1 to 530-M.

  The row reset lines 510-1 to 510 -N and the row selection lines 520-1 to 520 -N supply signals for controlling reading of the unit cells 501 to the unit cells 501 provided in the corresponding rows. To be transmitted. The row reset lines 510-1 to 510-N transmit a reset signal generated by a shift register included in the scanning circuit portion 580b to the unit cells 501 provided in the corresponding row. The unit cell 501 resets the charge stored in the photoelectric conversion element included in the unit cell 501 according to a reset signal. The unit cell 501 outputs, to the row selection line 520, an output signal of the photoelectric conversion element in a state where the accumulated charge has been reset. This output signal is an analog signal indicating the reset level.

  The row selection lines 520-1 to 520-N transmit a row selection signal generated by a shift register included in the scanning circuit unit 580 to the unit cell 501 provided in a corresponding row. The unit cell 501 outputs an output signal of a photoelectric conversion element included in the unit cell 501 to the vertical signal line 530 according to a row selection signal. This output signal is an analog signal indicating the signal level of the pixel signal. The vertical signal line 530 transmits the output signal to the processing circuit unit 540 along the y-axis direction.

  The drive signal generation unit 560 controls the operation timing of each circuit such as the scanning circuit unit 580a, the scanning circuit unit 580b, the processing circuit unit 540, the output circuit unit 590, and the like. And a reference signal generation circuit for generating the ramp voltage of

  Comparator 551 compares the voltage level of the ramp voltage input from drive signal generation section 560 to comparator 551 with the voltage level of the output signal from unit cell 501 in the corresponding column, and compares the comparison result with the corresponding counter. 552. While the comparator 551 compares the voltage level of the lamp voltage with the reset level, the counter 552 keeps down until a comparison result indicating that the voltage level of the lamp voltage of the unit cell 501 matches the reset level is input. Perform a count. In addition, while the comparator 551 compares the voltage level of the lamp voltage with the signal level of the unit cell 501, the counter 552 keeps inputting a comparison result indicating that the voltage level of the lamp voltage matches the signal level. , Up count. The count value obtained by the counter 552 corresponds to the digital value of the pixel signal.

  As a result, the conversion circuit 550 generates a digital pixel signal from which the influence of the reset level has been removed from the input signal level. In this manner, the conversion circuit 550 can generate a digital pixel signal in which noise such as fixed pattern noise is reduced. The digital pixel signal generated by the conversion circuit 550 is input to the output circuit unit 590, and is output to the mounting substrate 120 via the bonding wire 110.

  Here, the current flow section 301 and the current flow section 401 are located below the pixel section 500 included in the imaging chip 100. Specifically, when the current flow part 301 and the pixel part 500 are projected on the xy plane, at least a part of the current flow part 301 overlaps a part of the pixel part 500. Further, when the current flow portion 401 is projected on the xy plane, at least a portion of the current flow portion 401 overlaps a portion of the pixel portion 500. Further, the current supplied through the power supply pattern 300 is supplied to the counter 552 of the conversion circuit 550. On the other hand, the current supplied via the power supply pattern 310, the power supply pattern 320, the power supply pattern 330, the power supply pattern 340, the power supply pattern 350 and the power supply pattern 360 is a circuit other than the counter 552 among the circuits formed in the peripheral area 102. It is supplied to the circuit and the pixel portion 500.

  The counter 552 instantaneously requires a relatively large current during the counting operation. The counter 552 repeatedly performs a count operation and a non-operation. A relatively large current is intermittently and periodically supplied to the counter 552. Therefore, a large electromagnetic field may be generated by the current supplied to the counter 552. In particular, in order to increase the number of pixels of the imaging chip or to enable high-speed reading in moving image shooting, it is necessary to increase the reading speed of pixel signals. In order to increase the reading speed, for example, the driving cycle of the counter 552 is shortened. Accordingly, the supply cycle of the power supply current supplied to the counter 552 is shortened, and a large electromagnetic field may be generated.

  In general, the shorter the current supply period, the greater the electromagnetic radiation generated by the current. When the electromagnetic field radiation increases, the operation of electronic components such as an imaging chip may be affected. For example, in an imaging unit, large noise may be mixed in a pixel signal generated by an imaging chip. For example, when a power supply pattern is formed below the imaging chip and crosses the substrate along the y-axis, noise is superimposed on pixel signals due to an electromagnetic field generated from the power supply pattern at the time of reading, and an image including a fixed pattern of vertical stripes is formed. May be generated.

  On the other hand, according to the imaging unit 40, as described above, the power supply pattern 300 and the ground pattern 400 provide a pair of balanced differential lines, so that the electromagnetic field emission caused by the current supplied to the counter 552 is suppressed. it can. Therefore, the influence on the operation of the imaging chip 100 can be suppressed. For example, noise superimposed on a pixel signal generated by the imaging chip 100 due to electromagnetic field radiation generated by a current supplied to the counter 552 can be suppressed.

  As described above, the capacitor 182 is electrically connected to the vicinity of the chip connection portion 303 and the chip connection portion 403. A change in current when the counter 552 switches between the operating state and the non-operating state is absorbed by the capacitor 182. Therefore, in the power supply pattern 300 and the ground pattern 400, a current path through which a large current flows to the counter 552 driven at high speed is substantially limited to the chip connection portion 303 and the chip connection portion 403. In particular, a sharp current change when the operation state of the counter 552 is switched mainly appears in the chip connection unit 303 and the chip connection unit 403.

  Here, the effect of the current flowing along the y-axis tends to appear in the pixel signal via the vertical signal line 530 arranged along the y-axis. In the imaging unit 40, as shown in FIG. 5, since the chip connecting portion 303 and the chip connecting portion 403 extend in the x-axis direction as a whole, the y-axis is provided between the capacitor 182 and the wiring layer 202. Has substantially no current path along. Therefore, according to the imaging unit 40, it is possible to suppress the noise from being superimposed on the pixel signal via the vertical signal line 530 due to the effect of the current supplied to the counter 552. The chip connection portion 303 and the chip connection portion 403 are provided substantially in parallel with the surface of the mounting substrate 120 on which the imaging chip 100 is provided, and supply a current supplied from the capacitor 182 to the imaging chip 100 and supply a vertical signal line 530 to the pixel signal. 1 is an example of wiring flowing in a direction substantially orthogonal to the direction in which data is transmitted. Specifically, the chip connecting section 303 is located between the current flowing section 301 and the imaging chip 100 in the current path between the current flowing section 301 and the imaging chip 100, and is connected between the capacitor 182 and the imaging chip 100. Is supplied in a direction substantially perpendicular to the transmission direction in which the vertical signal line 530 transmits the pixel signal. The chip connection unit 403 is located between the chip connection unit 403 and the imaging chip 100 in a current path between the chip connection unit 403 and the imaging chip 100, and is supplied from the capacitor 182 to the imaging chip 100. The current returning from 100 flows in a direction substantially perpendicular to the transmission direction in which the vertical signal line 530 transmits the pixel signal.

  If a board that is sufficiently wider than the imaging chip is used as a mounting substrate for the imaging chip or a substrate on which the imaging chip itself is mounted, a board may be provided outside the imaging chip or a power supply pattern may be formed outside the imaging chip. Design becomes possible. In particular, regarding a power supply pattern through which a large power supply flows, if the shape is a solid pattern, there is a possibility that the influence of electromagnetic radiation from the power supply pattern can be relatively reduced. However, in order to apply this board design, a large-area board is required. Therefore, when this board design is applied, it is difficult to reduce the size of the camera. Further, since electronic components such as connectors cannot be arranged near the imaging chip 100, it is not easy to reduce the number of electronic components. Further, it is not easy to reduce the weight of the imaging unit. In addition, the degree of freedom in substrate design is reduced.

  On the other hand, according to the imaging unit 40, even when the connector 181 and the power supply pattern 300 are provided at a position below the imaging chip 100, the influence of noise on the imaging chip 100 can be suppressed. Therefore, it is possible to suppress the deterioration of the imaging performance while reducing the size of the mounting substrate 120. In addition, the number of electronic components can be easily reduced. Further, it is easy to reduce the weight of the imaging unit. In addition, the degree of freedom in substrate design can be increased. Further, since electromagnetic waves radiated to the outside can be suppressed, it can be a measure against electromagnetic radiation (EMI) in electromagnetic compatibility (EMC). As described above, according to the imaging unit 40, the influence of the current flowing through the power supply pattern 300 and the ground pattern 400 on the imaging chip 100 and the outside of the imaging unit 40 can be suppressed.

  In addition, as shown in FIG. 6, the first terminal 281 connected to the power supply pattern 300 and the second terminal 282 connected to the ground pattern 400 are adjacent to each other. As described above, when the terminals near the connector 181 are assigned as the power supply side terminal and the ground side terminal, it is easy to realize a wiring pattern that cancels out electromagnetic waves and the like.

  It is more desirable that the current path from the output from the connector 181 to the return to the connector 181 be short. Therefore, for example, as a power supply side terminal for supplying current to the counter 552, it is desirable to use a terminal closest to the connector 181. In the imaging unit 40, since the conversion circuit 550 is provided on the y-axis minus side of the peripheral area 102, the (n−1) th terminal 283 is used as a power supply side terminal for supplying current to the counter 552, and the current to the counter 552 is used. The n-th terminal 284 may be used as a ground terminal for supply.

  Note that when a first conversion circuit similar to the conversion circuit 550 is provided on the y axis minus side of the peripheral region 102 and a second conversion circuit similar to the conversion circuit 550 is provided on the y axis plus side, the first conversion The first terminal 281 is used as a power supply side terminal for a circuit, the second terminal 282 is used as a ground side terminal for a first conversion circuit, and the (n-1) th terminal 283 is used as a power supply side terminal for a second conversion circuit. And it is desirable to use the n-th terminal 284 as the ground-side terminal for the second conversion circuit. In this manner, the same type of circuit is provided at different positions, a power supply current supplied to one circuit is supplied from the first terminal pair of the connector, and a power supply current supplied to the other circuit is supplied to the other circuit. In the case of supply from the second terminal pair, the first terminal pair is located closer to one circuit than the second terminal pair, and the second terminal pair is It is desirable to be located on the side closer to the other circuit.

  In the imaging unit 40 described above, the power supply pattern 300 may be provided on the wiring layer 214 and the ground pattern 400 may be provided on the wiring layer 216. Note that one of the power supply pattern 300 and the ground pattern 400 may be provided in the wiring layer 212, and the other of the power supply pattern 300 and the ground pattern 400 may be provided in the wiring layer 214. From the viewpoint of suppressing noise superimposed on the imaging chip 100, it is desirable that the power supply pattern 300 and the ground pattern 400 be located farther from the imaging chip 100. For example, it is desirable that the power supply pattern 300 and the ground pattern 400 are located on the z-axis minus side of the core layer 209. It is desirable that a solid ground pattern like a ground pattern 490 be provided between the power supply pattern 300 and the ground pattern 400 and the imaging chip 100. However, the wiring layer 204 may not have the solid ground pattern 490. Note that the ground pattern 490 is provided on the mounting substrate 120, and is located between the current flow part 301 and the current flow part 401 and the imaging chip 100, and the current flow part 301 and the current It is an example of a flat conductor at a ground potential, which covers the passage section 401.

  FIG. 8 is a cross-sectional view schematically illustrating an imaging unit 2040 according to the second embodiment. FIG. 8 is a cross-sectional view of the imaging unit 2040 corresponding to FIG.

  The imaging unit 2040 has a core layer 2209 made of metal instead of the core layer 209 of the imaging unit 40. The imaging unit 2040 further includes an insulating layer 2207 and an insulating layer 2217 in addition to the components included in the imaging unit 40. Note that among the components included in the imaging unit 2040, components denoted by the same reference numerals as the components described in relation to the imaging unit 40 have the same configuration. Therefore, description of the components may be omitted.

  As a material of the core layer 2209, for example, an alloy of nickel and iron (for example, 42 alloy, 56 alloy), copper, aluminum, or the like may be used. The core layer 2209 is sandwiched between the insulating layers 2207 and 2217 in the z-axis direction. An insulating layer 2207 in contact with the wiring layer 206 and the core layer 2209 is disposed between the wiring layer 206 and the core layer 2209, and an insulating layer 2217 in contact with the core layer 2209 between the core layer 2209 and the wiring layer 216. Is arranged. The insulating layer 2207 and the insulating layer 2217 are formed using the same material as the material for forming the insulating layer 203, the insulating layer 205, the insulating layer 215, and the insulating layer 213.

  The core layer 2209 is electrically connected to a ground pattern such as the ground pattern 480 via a via. According to the imaging unit 2040, the power supply pattern 300 and the ground pattern 400 are provided on the z-axis minus side of the core layer 2209. Therefore, it is possible to suppress the floating fringe electric field from reaching the imaging chip 100. As described above, according to the imaging unit 2040, the electromagnetic wave generated in the power supply pattern 300 and the ground pattern 400 can be shielded by the core layer 2209. Therefore, the influence of the current flowing through the power supply pattern 300 and the ground pattern 400 on the imaging chip 100 and the outside of the imaging unit 40 can be suppressed.

  The core layer 2209 is provided on the mounting substrate 120, and is located between the current flowing portion 301 and the current flowing portion 401 and the imaging chip 100, and is provided between the current flowing portion 301 and the current flowing portion with respect to the imaging chip 100. 5 is an example of a flat conductor at a ground potential and covering a portion 401. In the imaging unit 2040, the wiring layer 204 does not have to have the solid ground pattern 490. Since the core layer 2209 is formed of metal, even if the wiring layer 204 does not have the solid ground pattern 490, the current flowing through the power supply pattern 300 and the ground pattern 400 can be generated outside the imaging chip 100 and the imaging unit 40. Can be suppressed.

  FIG. 9 is a cross-sectional view schematically illustrating an imaging unit 3040 according to the third embodiment. FIG. 9 is a cross-sectional view of the imaging unit 3040 corresponding to FIG.

  The imaging unit 3040 has a power supply pattern 3300 and a ground pattern 3400 instead of the power supply pattern 300 and the ground pattern 400 included in the imaging unit 40. Note that among the components included in the imaging unit 3040, components denoted by the same reference numerals as the components described in relation to the imaging unit 40 have the same configuration. Therefore, description of the components may be omitted. Further, among the components included in the imaging unit 3040, the components corresponding to the components described in relation to the imaging unit 40 have the same configuration as the corresponding components included in the imaging unit 40, and thus description thereof will be omitted. May be.

  The imaging unit 3040 has a power supply pattern 3310, a power supply pattern 3320, a power supply pattern 3330, a power supply pattern 3340, and a power supply pattern 3350 as power supply patterns other than the power supply pattern 3300 in the wiring layer 216. These power supply patterns correspond to the power supply patterns 310, 320, 330, 340, 350, and 360 other than the power supply pattern 300 in the imaging unit 40. The imaging unit 3040 has a ground pattern 3480 in the wiring layer 214 as a ground pattern corresponding to the ground pattern 480.

  The power supply pattern 3300 and the ground pattern 3400 are provided on the wiring layer 212 of the mounting board 120. The ground pattern 3400 is provided substantially parallel to the power supply pattern 300. The ground pattern 3400 is provided along the power supply pattern 3300. Specifically, both the power supply pattern 3300 and the ground pattern 3400 extend in a direction parallel to the y-axis. The power supply pattern 3300 is an example of a wiring formed on one wiring layer of the mounting board 120. The ground pattern 3400 is an example of a wiring formed on the wiring layer on which the power supply pattern 3300 is formed and located near the power supply pattern 3300.

  The ground pattern 3480 is a solid ground pattern provided as the wiring layer 214. The power supply pattern 3300 and the ground pattern 3400 are provided on the surface layer on the second main surface 112 side of the mounting board 120. The power supply pattern 3300, the ground pattern 3400, and the ground pattern 3480 have a so-called microstrip line structure. According to this line structure, the ground pattern 3480 has a function of coupling the lines of electric force generated in the positive z-axis direction. Therefore, many lines of electric force generated from the power supply pattern 3300 and the ground pattern 3400 can be captured.

  Thus, the power pattern 3300 and the ground pattern 3400 provide a pair of balanced differential lines. Therefore, the influence of the current flowing through the power supply pattern 3300 and the ground pattern 3400 on the imaging chip 100 and the outside of the imaging unit 40 can be suppressed.

  From the viewpoint of suppressing noise superimposed on the imaging chip 100, it is desirable that the power supply pattern 3300 and the ground pattern 3400 be located farther from the imaging chip 100. However, the power supply pattern 3300 and the ground pattern 3400 may be provided in an inner layer of the mounting board 120. For example, the power supply pattern 3300 and the ground pattern 3400 may be provided in one of the wiring layers 214, 216, and 206. In this case, a solid ground pattern may be provided on a wiring layer on the z-axis plus side from the wiring layer on which the power supply pattern 3300 and the ground pattern 3400 are provided.

  Further, similarly to the imaging unit 2040, the core layer 209 may be formed of metal. In this case, the power supply pattern 3300 and the ground pattern 3400 are desirably provided on a wiring layer on the z-axis minus side from the core layer 209. Specifically, it is preferable that the power supply pattern 3300 and the ground pattern 3400 be provided in any one of the wiring layers 212, 214, and 216.

  FIG. 10 is a cross-sectional view schematically illustrating an imaging unit 4040 according to the fourth embodiment. FIG. 10 is a cross-sectional view of the imaging unit 4040 corresponding to FIG.

  The imaging unit 4040 further includes a guard pattern 4500a and a guard pattern 4500b in the wiring layer 212 in addition to the components included in the imaging unit 3040. Note that among components included in the imaging unit 4040, components denoted by the same reference numerals as the components described in relation to the imaging unit 3040 have the same configuration. Therefore, description of the components may be omitted. In addition, among components included in the imaging unit 4040, components corresponding to the components described in relation to the imaging unit 3040 have the same configurations as the corresponding components included in the imaging unit 3040, and thus description thereof will be omitted. May be.

  The guard pattern 4500a, the guard pattern 4500b, the power supply pattern 3300, and the ground pattern 3400 are provided on the same wiring layer. The guard pattern 4500a is electrically connected to the ground pattern 3480 via the via 4131a. The guard pattern 4500b is electrically connected to the ground pattern 3480 via the via 4131b.

  The guard pattern 4500a is an example of a ground potential wiring formed along the power supply pattern 3300 and the ground pattern 3400 on the wiring layer on which the power supply pattern 3300 and the ground pattern 3400 are formed. The guard pattern 4500b is an example of a ground potential wiring formed along the power supply pattern 3300 and the ground pattern 3400 on the wiring layer on which the power supply pattern 3300 and the ground pattern 3400 are formed. The power supply pattern 3300 is located between the guard pattern 4500a and the ground pattern 3400. The ground pattern 3400 is located between the guard pattern 4500b and the power supply pattern 3300.

  As described above, by providing the guard patterns 4500a and 4500b of the ground potential extending along the power supply pattern 3300 and the ground pattern 3400 on both sides of the power supply pattern 3300 and the ground pattern 3400, the shielding effect of the electromagnetic wave is further improved. be able to. In this configuration, since the power supply pattern 3300 and the ground pattern 3400 are not surrounded by the ground potential, deterioration of the frequency characteristics of the power supply system can be suppressed.

  Note that the guard pattern 4500a and the guard pattern 4500b are desirably provided with a plurality of vias at regular intervals and connected to the ground pattern 3480. It is desirable to provide more vias for connecting the guard patterns 4500a and 4500b and the ground pattern 3480. Further, it is desirable that the interval between vias connecting guard patterns 4500a and 4500b and ground pattern 3480 is less than １ ／ wavelength of the frequency of the current flowing through power supply pattern 3300 and ground pattern 3400.

  It is desirable that the power supply pattern 3300 and the ground pattern 3400a are more strongly coupled between the power supply pattern 3300 and the guard pattern 4500a. Further, it is desirable that the power supply pattern 3300 and the ground pattern 3400 are more strongly coupled between the ground pattern 3400 and the guard pattern 4500b. Specifically, when the interval between the power supply pattern 3300 and the ground pattern 3400 is S, the guard pattern 4500a is desirably provided at least 2S away from the power supply pattern 3300. Similarly, the guard pattern 4500b is desirably provided at least 2S away from the ground pattern 3400. Thus, it is desirable that the distance between the guard pattern 4500a and the power supply pattern 3300 is larger than twice the distance between the power supply pattern 3300 and the ground pattern 3400. Further, it is desirable that the distance between guard pattern 4500b and ground pattern 3400 is larger than twice the distance between power supply pattern 3300 and ground pattern 3400.

  When the width of the power supply pattern 3300 is W, it is preferable that the guard pattern 4500a is provided at a distance of 2 W or more from the power supply pattern 3300. Similarly, the guard pattern 4500b is desirably provided at a distance of 2 W or more from the ground pattern 3400. It is desirable that S <W. Note that the width of the power supply pattern 3300 is a length in a direction orthogonal to the direction in which the power supply pattern 3300 extends. That is, the width of the power supply pattern 3300 is the length in the x-axis direction. Similarly, the width of the ground pattern 3400 is the length of the ground pattern 3400 in the x-axis direction.

  FIG. 11 is a cross-sectional view schematically illustrating an imaging unit 5040 according to the fifth embodiment. FIG. 11 is a cross-sectional view of the imaging unit 5040 corresponding to FIG.

  The imaging unit 5040 has a power supply pattern 5300 instead of the power supply pattern 3300 included in the imaging unit 3040. The imaging unit 5040 has a ground pattern 5400 instead of the ground pattern 3400 included in the imaging unit 3040. The imaging unit 5040 has a core layer 5209 made of metal instead of the core layer 209 included in the imaging unit 3040. The imaging unit 5040 further includes an insulating layer 5207 and an insulating layer 5217 in addition to the components included in the imaging unit 3040. Note that among components included in the imaging unit 5040, components denoted by the same reference numerals as the components described in relation to the imaging unit 3040 have the same configuration. Therefore, description of the components may be omitted.

  The power supply pattern 5300 is a power supply pattern corresponding to the power supply pattern 3300. The ground pattern 5400 is a ground pattern corresponding to the ground pattern 3400. The imaging unit 5040 has a power supply pattern 5310, a power supply pattern 5320, a power supply pattern 5330, a power supply pattern 5340, and a power supply pattern 5350 as power supply patterns other than the power supply pattern 5300 in the wiring layer 216. These power patterns are power patterns corresponding to the power patterns 3310, 3320, 3330, 3340, and 3350 other than the power pattern 3300 in the imaging unit 3040. Note that the core layer 5209 corresponds to the core layer 2209 in the imaging unit 2040. The insulating layer 5207 corresponds to the insulating layer 2207 in the imaging unit 2040. The insulating layer 5217 corresponds to the insulating layer 2217 in the imaging unit 2040. Among components included in the imaging unit 5040, components corresponding to the components described in relation to the imaging unit 2040 or the imaging unit 3040 have the same configuration as the corresponding components included in the imaging unit 2040 or the imaging unit 3040. Therefore, the description may be omitted.

  The power supply pattern 5300 and the ground pattern 5400 are provided in an inner layer of the mounting board 120. Specifically, the power supply pattern 5300 and the ground pattern 5400 are provided on the wiring layer 216 of the mounting board 120. Thus, the power supply pattern 5300 and the ground pattern 5400 are sandwiched between the core layer 5209 and the ground pattern 3480. The power supply pattern 5300 and the ground pattern 5400 are located between the core layer 2209 and the ground pattern 3480. The ground pattern 3480 is an example of a flat conductor having a ground potential and provided on the mounting substrate 120 and covering the power supply pattern 5300 and the ground pattern 5400.

  The power supply pattern 5300, the ground pattern 5400, the ground pattern 3480, and the core layer 5209 have a so-called strip line structure. According to this structure, the power supply pattern 5300 and the ground pattern 5400 are substantially shielded by the core layer 5209 and the ground pattern 3480, so that the electromagnetic wave shielding effect can be further enhanced. As in the other embodiments, since the capacitor 182 is connected to the power supply pattern 5300 and the ground pattern 5400, a decrease in the frequency response caused by the power supply pattern 5300 and the ground pattern 5400 being substantially shielded by a conductor is prevented. Can be suppressed.

  Note that the power supply pattern 5300 and the ground pattern 5400 may be provided in a wiring layer other than the wiring layer 216. For example, the power supply pattern 5300 and the ground pattern 5400 may be provided on any layer as long as the wiring layer is on the z axis minus side from the core layer 5209. Further, a so-called strip line structure may be provided by providing a solid ground pattern in two wiring layers sandwiching the power supply pattern 5300 and the ground pattern 5400 without using the metal core layer 5209.

  In the imaging unit 3040, the imaging unit 4040, and the imaging unit 5040, the power supply pattern and the ground pattern are provided on the same wiring layer. However, the power supply pattern and the ground pattern may be provided on different wiring layers. For example, a power supply pattern may be provided on the wiring layer 216 and a ground pattern may be provided on the wiring layer 214. As described above, the ground pattern may be provided on the wiring layer adjacent to the wiring layer provided with the power supply pattern. If the wiring layer provided with the power supply pattern and the wiring layer provided with the ground pattern are close to each other, a corresponding effect can be expected. In order to shield electromagnetic waves and the like, it is desirable that each wiring layer has a large thickness.

  FIG. 12 is a bottom view schematically showing the mounting substrate 120 on which the flexible substrate 600 is mounted. In FIG. 12, as in FIG. 6, illustration of electronic components other than the connector 181 and the capacitor 182 and the wiring layer 212 among components included in the mounting board 120 is omitted. FIG. 13 is a cross-sectional view schematically illustrating the imaging unit 40 with the flexible substrate 600 mounted. FIG. 13 is a cross-sectional view of the imaging unit 40 and the flexible substrate 600 when cut along the line CC of FIG.

  The flexible board 600 is, for example, a flexible printed board. The flexible board 600 of the present embodiment is a single-sided flexible printed board. The flexible board 600 is mounted on the connector 181. The flexible substrate 600 supplies a current supplied to the imaging chip 100. The flexible substrate 600 has a power supply wiring 610, a ground wiring 620, and a signal line group 650 including a plurality of signal lines.

  The signal line group 650 may include a signal line for transmitting the pixel signal from the imaging chip 100 transmitted to the connector 181 to the ASIC 52. Further, the signal line group 650 may include a signal line for transmitting a control signal for controlling the imaging chip 100.

  The power supply wiring 610 allows a current supplied from an external power supply of the imaging unit 40 to the imaging chip 100 to flow. When the flexible board 600 is mounted on the connector 181, the power supply wiring 610 allows a current supplied from the power supply to the imaging chip 100 to flow in the negative x-axis direction. The power supply outside the imaging unit 40 is, for example, a power supply circuit included in the battery unit. The power supply wiring 610 is an example of a wiring that allows a current supplied from the power supply to the imaging chip 100 to flow in the third direction.

  The current flowing through the power supply wiring 610 is supplied to the mounting board 120 through the first terminal 281 of the connector 181. Specifically, as described above, the current flowing through the power supply wiring 610 flows into the power supply connection part 302 included in the power supply pattern 300 through the first terminal 281 and the via.

  The ground wiring 620 supplies a current that is supplied to the imaging chip 100 through the power supply wiring 610 and returns from the imaging chip 100 to the power supply. Specifically, a current returning from the imaging chip 100 to an external power supply is supplied to the ground wiring 620. Specifically, as described above, the current returning from the imaging chip 100 to the external power supply is supplied to the ground wiring 620 through the second terminal 282 of the connector 181, and flows through the ground wiring 620 to return to the external power supply.

  The ground wiring 620 is provided adjacent to and along the power supply wiring 610. Therefore, when the flexible substrate 600 is mounted on the connector 181, the ground wiring 620 allows the current supplied to the imaging chip 100 via the power supply wiring 610 and returned from the imaging chip 100 to the power supply to flow in the positive x-axis direction. The ground wiring 620 is an example of a wiring that flows a current supplied to the imaging chip 100 through the power supply wiring 610 and returned from the imaging chip 100 to a power supply in a fourth direction substantially opposite to the third direction.

  As shown in FIG. 13, the flexible substrate 600 has one wiring layer 670. In the wiring layer 670, a power supply wiring 610, a ground wiring 620, and a signal line group 650 are provided. As described above, the power supply wiring 610 and the ground wiring 620 are provided side by side on the same wiring layer 670 of the flexible substrate 600.

  The power supply wiring 610 and the ground wiring 620 extend side by side, the direction in which the current flows through the power supply wiring 610 is opposite to the direction in which the current flows through the ground wiring 620, and the magnitude of the current flowing through the power supply wiring 610 is the ground wiring. 620 is substantially equal to the magnitude of the current flowing through it. Therefore, the power supply wiring 610 and the ground wiring 620 have a pattern configuration that provides a pair of balanced differential lines. Since the power supply wiring 610 and the ground wiring 620 are adjacent to each other, the power supply wiring 610 and the ground wiring 620 provide a pair of balanced differential lines that are tightly coupled. Therefore, the electromagnetic field caused by the current flowing through the ground wiring 620 and returning to the power supply acts in a direction to cancel the electromagnetic field caused by the current flowing through the power supply wiring 610 and supplied to the imaging chip 100. That is, the electromagnetic field caused by the current flowing through the power supply wiring 610 and supplied to the imaging chip 100 and the electromagnetic field caused by the current flowing through the ground wiring 620 and returning to the power supply act in directions to cancel each other. Therefore, the influence on the imaging chip 100 of the electromagnetic field generated by the current flowing through the power supply wiring 610 and the current flowing through the ground wiring 620 can be suppressed.

  Accordingly, even when the flexible substrate 600 is provided at a position below the imaging chip 100, the influence of noise on the imaging chip 100 can be suppressed. Therefore, it is possible to suppress the deterioration of the imaging performance while reducing the size of the mounting substrate 120. Further, it is easy to reduce the weight of the imaging unit. In addition, the degree of freedom in substrate design can be increased. Further, since electromagnetic waves radiated to the outside can be suppressed, it can be a measure against electromagnetic radiation (EMI) in electromagnetic compatibility (EMC). As described above, according to the flexible substrate 600, at least the electromagnetic field caused by the current flowing through the ground wiring 620 and returning to the power supply is equal to or less than the electromagnetic field caused by the current flowing through the power supply wiring 610 and supplied to the imaging chip 100. It is provided along the power supply wiring 610 so that one side is canceled. Therefore, the influence of the current flowing through the power supply wiring 610 and the ground wiring 620 on the outside of the imaging chip 100 and the imaging unit 40 can be suppressed.

  Note that the direction of the current flowing through the power supply wiring 610 and the direction of the current flowing through the ground wiring 620 need not be completely opposite. The direction of the current flowing through the power supply wiring 610 and the direction of the current flowing through the ground wiring 620 may be substantially opposite to each other so as to substantially act in directions in which electromagnetic waves cancel each other. Thereby, the same effect as the effect obtained by forming the above-described current flow portion 301 and current flow portion 401 in a tightly coupled differential pattern can be obtained. Although the influence of the electromagnetic wave on the imaging chip 100 and the like is mainly described here, the same applies to at least one of the magnetic field and the electric field. That is, the ground wiring 620 has a direction in which at least one of a magnetic field and an electric field caused by a current flowing through the ground wiring 620 and returning to the power supply cancels out at least one of a magnetic field and an electric field caused by a current flowing through the power supply wiring 610 and supplied to the imaging chip 100. May be provided along the power supply wiring 610.

  In addition, as shown in FIG. 12, the width of the mounting substrate 120 in the x-axis direction is Ws. That is, the width of the mounting substrate 120 in the direction along the extending direction of the power supply wiring 610 is Ws. When the flexible board 600 is mounted on the connector 181, the flexible board 600 is provided at a position facing the mounting board 120. The width of the mounting substrate 120 in a direction along the extending direction of the power supply wiring 610 in a region where the mounting substrate 120 is provided to face the flexible substrate 600 is represented by a width Wl. Here, Wl is equal to or less than half of Ws. For example, the position of the connector 181 is provided on the mounting board 120 such that Wl is equal to or less than half of Ws. Thus, the length of the portion where the mounting substrate 120 and the flexible substrate 600 overlap when projected on the xy plane is equal to or less than half of Ws. Therefore, even if some electromagnetic waves leak from the flexible substrate 600, the influence of the electromagnetic waves on the imaging chip 100 can be suppressed.

  When the flexible board 600 is mounted on the connector 181, the power supply wiring 610 and the ground wiring 620 are substantially orthogonal to the vertical signal lines 530. Accordingly, even if some electromagnetic waves leak from the power supply wiring 610 and the ground wiring 620, it is possible to suppress the noise from being superimposed on the pixel signal through the vertical signal line 530.

  Note that as the angle between the extending direction of the power supply wiring 610 and the ground wiring 620 and the extending direction of the vertical signal line 530 is closer to 90 °, the superimposition of noise on the pixel signal through the vertical signal line 530 can be suppressed. Therefore, it is preferable that the angle between the extending direction of the power supply wiring 610 and the ground wiring 620 and the extending direction of the vertical signal line 530 is close to 90 °. However, even when the power supply wiring 610 and the ground wiring 620 form an angle of 45 ° with the vertical signal line 530, it is possible to suppress superimposition of large noise on the pixel signal through the vertical signal line 530. Therefore, the power supply wiring 610 and the ground wiring 620 are provided at least in a direction in which the angle between the vertical signal line 530 and the vertical signal line 530 is within a range of 45 ° or more and 90 ° or less in a portion where the flexible substrate 600 is provided to face the mounting substrate 120. May be.

  In a non-facing region other than the portion where the flexible substrate 600 is provided facing the mounting substrate 120, the power supply wiring 610 and the ground wiring 620 do not need to be orthogonal to the vertical signal lines 530. In the non-opposing region, the angle formed between the extending direction of the power supply wiring 610 and the ground wiring 620 and the extending direction of the vertical signal line 530 may be less than 45 °.

  FIG. 14 is a cross-sectional view schematically illustrating the flexible substrate 700 and the imaging unit 40. FIG. 14 is a sectional view corresponding to FIG. The flexible substrate 700 is a modified example of the flexible substrate 600. The flexible board 700 is an example of a double-sided flexible printed board.

  The flexible substrate 700 has a wiring layer 770 and a ground layer 780. The wiring layer 770 and the ground layer 780 are insulated by an insulating layer. In the wiring layer 770, a power supply wiring 710, a ground wiring 720, and a signal line group 750 including a plurality of signal lines are provided.

  The wiring layer 770 corresponds to the wiring layer 670. The power supply wiring 710 corresponds to the power supply wiring 610, and the ground wiring 720 corresponds to the ground wiring 620. Of the components included in the flexible substrate 700, components corresponding to the components described in relation to the flexible substrate 600 have the same configurations as the corresponding components included in the flexible substrate 600, and thus description thereof will be omitted. There are cases.

  The ground layer 780 is a substantially solid pattern that covers at least the power supply wiring 610 and the ground wiring 620. The ground layer 780 is an example of a flat conductor having a ground potential. The ground layer 780 covers the power supply wiring 710, the ground wiring 720, and the signal line group 750. When the flexible board 700 is mounted on the connector 181, the ground layer 780 is located between the wiring layer 770 and the mounting board 120.

  According to the flexible substrate 700, since the ground layer 780 is located between the wiring layer 770 and the mounting substrate 120, for example, a floating fringe electric field caused by a current flowing through the power supply wiring 710 and the ground wiring 720 reaches the imaging chip 100. It can be suppressed by the ground layer 780. As described above, according to the flexible substrate 700, the electromagnetic wave generated in the power supply wiring 710 and the ground wiring 720 can be shielded by the ground layer 780. Therefore, the influence of the current flowing through the power supply wiring 710 and the ground wiring 720 on the imaging chip 100 and the outside of the imaging unit 40 can be suppressed.

  FIG. 15 is a cross-sectional view schematically illustrating the flexible substrate 800 and the imaging unit 40. FIG. 15 is a sectional view corresponding to FIG. The flexible substrate 800 is a further modified example of the flexible substrate 600. The flexible board 800 is an example of a double-sided flexible printed board.

  The flexible substrate 800 has a wiring layer 870 and a wiring layer 880. The wiring layer 870 and the wiring layer 880 are insulated by an insulating layer. Wiring layer 870 includes power supply wiring 810. The wiring layer 880 includes a ground wiring 820. The wiring layers 870 and 880 further include a signal line group 850 including a plurality of signal lines.

  The wiring layer 870 corresponds to the wiring layer 770. The power supply wiring 810 corresponds to the power supply wiring 610, and the ground wiring 820 corresponds to the ground wiring 620. Of the components included in the flexible substrate 800, components corresponding to the components described in relation to the flexible substrate 600 have the same configuration as the corresponding components included in the flexible substrate 600. May be omitted.

  The wiring layer 880 is a wiring layer adjacent to the wiring layer 870. The power supply wiring 810 is provided so that at least a part of the surface of the power supply wiring 810 and at least a part of the surface of the ground wiring 820 face each other. Specifically, when the power supply wiring 810 and the ground wiring 820 are projected on the xy plane, at least a part of a region occupied by the power supply wiring 810 on the xy plane and a region occupied by the ground wiring 820 on the xy plane overlap. The area where the power supply wiring 810 and the ground wiring 820 overlap when projected on the xy plane extends along the x-axis. Thus, the power supply wiring 810 and the ground wiring 820 extend substantially in parallel with each other. Therefore, even with the flexible substrate 800, the influence of the current flowing through the power supply wiring 810 and the ground wiring 820 on the imaging chip 100 and the outside of the imaging unit 40 can be suppressed.

  FIG. 16 is a bottom view schematically showing the mounting board 6120 on which the flexible board 900 is mounted. FIG. 15 is a bottom view corresponding to FIG.

  The flexible substrate 900 is a further modified example of the flexible substrate 600. The flexible board 800 is an example of a single-sided flexible printed board. The imaging chip 6100 is mounted on the mounting substrate 6120. The imaging chip 6100 is a modified example of the imaging chip 100. The imaging chip 6100 includes an imaging region 6101 and conversion circuits 6550a and 6550b provided in a peripheral region. The imaging region 6101 corresponds to the imaging region 101. The conversion circuit 6550a is provided in a peripheral area on the y-axis minus side in the imaging chip 6100, like the conversion circuit 550. In the imaging chip 6100, a conversion circuit 6550b is provided in a peripheral region on the y-axis plus side.

  Of the components included in the flexible substrate 900, components corresponding to the components described in relation to the flexible substrate 600 have the same configuration as the corresponding components included in the flexible substrate 600, and therefore, except for differences. May be omitted. The mounting substrate 120 is a mounting substrate for the imaging chip 6100, and has the same configuration as the mounting substrate 120 except that the mounting substrate 120 has a configuration for driving the imaging chip 6100.

  The flexible substrate 900 supplies a current supplied to the imaging chip 6100. The flexible substrate 900 includes a power supply wiring 910, a ground wiring 920, a signal line group 950 including a plurality of signal lines, a power supply wiring 930, and a ground wiring 940.

  The wiring pair of the power wiring 910 and the ground wiring 920 is a wiring pair located on the most positive side in the y-axis direction among the wiring pairs of the flexible substrate 900. The wiring pair of the power wiring 930 and the ground wiring 940 is a wiring pair located on the most negative side in the y-axis direction among the wiring pairs of the flexible substrate 900.

  Power supply wiring 910 corresponds to power supply wiring 610. The ground wiring 920 corresponds to the ground wiring 620. The power supply wiring 910 allows a current supplied from an external power supply to the imaging chip 6100 to flow. The ground wiring 920 supplies a current that is supplied to the imaging chip 6100 through the power wiring 910 and returns from the imaging chip 6100 to the power supply.

  In particular, the power supply wiring 910 allows a current supplied from an external power supply to the conversion circuit 6550b of the imaging chip 6100 to flow. Specifically, a current flowing through the power supply wiring 910 is supplied to the mounting board 6120 through the first terminal 281 of the connector 181, and is supplied to the conversion circuit 6550b through the mounting board 6120. The current returning from the conversion circuit 6550b to the external power supply is supplied to the ground wiring 920 through the second terminal 282 of the connector 181, flows through the ground wiring 920, and returns to the external power supply.

  The power supply wiring 930 is provided on the negative side of the y-axis, and differs from the power supply wiring 910 in that a current supplied to the conversion circuit 6550a flows. The ground wiring 940 is provided on the negative side of the y-axis, and differs from the ground wiring 920 in that a current returning to the power supply from the conversion circuit 6550a flows. Specifically, power supply wiring 930 allows a current supplied from an external power supply to conversion circuit 6550a to flow. Specifically, the current flowing through the power supply wiring 930 is supplied to the mounting board 6120 through the (n-1) th terminal 283 of the connector 181, and is supplied to the conversion circuit 6550a through the mounting board 6120. The current returning from the conversion circuit 6550a to the external power supply is supplied to the ground wiring 940 through the n-th terminal 284 of the connector 181, flows through the ground wiring 940, and returns to the external power supply.

  Similarly to the power supply wiring 610 and the ground wiring 620, the current flowing through the power supply wiring 910 and the current flowing through the ground wiring 920 act in directions to cancel each other out. Further, the current flowing through the power supply wiring 930 and the current flowing through the ground wiring 940 also act in directions in which electromagnetic waves cancel each other. Therefore, similarly to the flexible substrate 600, the influence of the current flowing through the power wiring 910, the ground wiring 920, the power wiring 930, and the ground wiring 940 on the imaging chip 6100 and the outside can be suppressed.

  Further, according to the flexible board 900, the power supply wiring 910 and the ground wiring 920 are located closer to the conversion circuit 6550b than other wirings of the flexible board 900. Further, the power supply wiring 930 and the ground wiring 940 are located closer to the conversion circuit 6550a than other wirings included in the flexible substrate 900. Therefore, a path through which a large current flows in the mounting substrate 6120 can be shortened. Thus, the effect of the current flowing through the mounting substrate 6120 on the imaging chip 6100 and the outside can be further suppressed.

  Note that as a modification example of the flexible substrate 900, a configuration of a double-sided flexible printed board included in at least one of the flexible substrate 700 and the flexible substrate 800 can be applied. In addition, any one of the above-described flexible substrates 600, 700, 800, and 900 can be applied to any of the imaging unit 2040, the imaging unit 3040, the imaging unit 4040, and the imaging unit 5040.

  In the above description, the power supply pattern and the ground pattern for supplying the current to the counter 552 have been mainly described. However, the counter 552 is an example of an electronic component to which a power supply current is supplied. For example, when the imaging chip 100 includes an analog CDS circuit that performs a CDS process on an analog pixel signal, the configuration of the power supply pattern and the ground pattern described above may be applied to the analog CDS circuit. Further, it goes without saying that the configuration of the power supply pattern and the ground pattern described above can be applied not only to the counter 552 and the analog CDS circuit but also to other electronic components.

  As a method for mounting the imaging chip 100, flip-chip mounting may be applied. Further, the mounting substrate of the imaging chip 100 is not limited to the core substrate, and various substrates can be applied as the mounting substrate. The above-described configuration of the power supply pattern and the ground pattern can also be applied to an imaging unit in which the first substrate on which the imaging chip 100 is mounted is mounted on the second substrate on which electronic components such as connectors are mounted.

  In the above, the camera 10 including the lens unit 20 and the camera body 30 has been described as an example of the imaging device. However, the imaging device need not include the lens unit 20. For example, the camera body 30 is an example of an imaging device. Further, the image pickup device is a concept including an image pickup device of a non-interchangeable lens type in addition to an image pickup device of an interchangeable lens type such as a single lens reflex camera.

  The imaging unit is an example of an electronic unit. The configuration having the power supply pattern and the ground pattern described above can be applied to various electronic units other than the imaging unit. The imaging device is an example of an electronic device. The electronic device may include an electronic unit having the configuration of the power supply pattern and the ground pattern described above.

  As described above, the present invention has been described using the embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is apparent to those skilled in the art that various changes or improvements can be made to the above embodiment. It is apparent from the description of the appended claims that embodiments with such changes or improvements can be included in the technical scope of the present invention.

  The execution order of each processing such as operation, procedure, step, and step in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before”, “before”. It should be noted that they can be realized in any order as long as the output of the previous process is not used in the subsequent process. Even if the operation flow in the claims, the specification, and the drawings is described using "first," "second," or the like for convenience, it means that it is essential to perform the operation in this order. Not something.

10 camera, 20 lens unit, 22 optical axis, 24 lens side mount, 26 body side mount, 30 camera body, 31 mirror unit, 32 main mirror, 33 sub mirror, 38 shutter unit, 40 image pickup unit, 51 MPU, 52 ASIC, Reference Signs List 60 mirror box, 62 substrate, 70 imaging optical system, 72 focus detection sensor, 80 focus plate, 82 pentaprism, 84 finder optical system, 86 finder window, 88 display unit 100 imaging chip, 101 imaging area, 102 peripheral area, 110 wire 111 first main surface, 112 second main surface 120 mounting board 121 first layer, 122 second layer 131 via 138 opening 140 frame 141 first surface, 142 second surface, 143 third surface, 144 fourth Surface, 145 5th surface, 146 6th surface 147 Positioning 148 mounting hole, 150 bracket, 160 cover glass 201, 211 solder resist layer 202, 204, 206, 212, 214, 216 wiring layer 203, 205, 213, 215 insulating layer 209 core layer 240 bonding lead 181 connector, 182 capacitor 183 resistor, 184 transistor 281 first terminal, 282 second terminal, 283 n-1 terminal, 284 nth terminal 300, 310, 320, 330, 340, 350, 360 power supply pattern 301 current flow section, 302 power supply Connection section, 303 Chip connection section 400, 480, 490 Ground pattern 401 Current flow section, 402 Power supply connection section, 403 Chip connection section 500 Pixel section, 501 unit cell, 510 row reset line, 520 row selection line, 530 vertical signal Wire, 540 processing circuit 550 conversion circuit, 551 comparator, 552 counter, 560 drive signal generation unit, 570 peripheral circuit unit, 580 scanning circuit unit, 590 output circuit unit 2040, 3040, 4040, 5040 Imaging unit 2207, 2217 insulating layer, 2209 core layer 3300, 3310, 3320, 3330, 3340, 3350 Power supply pattern 3400, 3480 Ground pattern 4131 Via, 4500 Guard pattern 5300, 5310, 5320, 5330, 5340, 5350 Power supply pattern 5400 Ground pattern 5207, 5217 Insulating layer, 5209 Core layer Power supply pattern

Claims (36)

An imaging element having an imaging region for imaging a subject,
A substrate having a first surface on which the image sensor is arranged and a second surface opposite to the first surface ;
In the substrate, a current flows in a direction from a first power supply toward the image sensor between a region corresponding to the imaging region on the first surface and a region corresponding to the imaging region on the second surface. A first wiring, and a second wiring arranged along the first wiring, wherein the current flows in a direction from the imaging element toward the first power supply after being supplied to the imaging element by the first wiring. And an electronic unit having wiring . An imaging element having an imaging region for imaging a subject,
A substrate having a first surface on which the image sensor is arranged and a second surface opposite to the first surface ;
In the substrate, a current flows in a direction from a first power supply toward the image sensor between a region corresponding to the imaging region on the first surface and a region corresponding to the imaging region on the second surface. An electronic unit comprising: a first wiring; and a second wiring disposed along the first wiring and flowing a current in a direction from the image sensor to the first power supply .
[KT Toshi 1]   The electronic unit according to claim 1, wherein the substrate has a first wiring layer including the first wiring and a second wiring layer including the second wiring. The electronic unit according to claim 3, wherein the first wiring layer and the second wiring layer are arranged adjacent to each other on the substrate. The first wiring is formed as a power supply pattern,
The electronic unit according to claim 1, wherein the second wiring is formed as a ground pattern . At least a portion of the surface, the electronic unit according to claim 5 which is arranged to face the at least a portion of the surface of the power supply pattern of the ground pattern.   The electronic unit according to claim 1, wherein the substrate has a wiring layer including the first wiring and the second wiring. The first wiring is formed as a power supply pattern,
  The electronic unit according to claim 7, wherein the second wiring is formed as a ground pattern.   The substrate has a first conductor at a ground potential,
  9. The electronic unit according to claim 1, wherein the first conductor is disposed between the first surface and the first and second wires on the substrate. 10.   The electronic unit according to claim 9, wherein the first conductor is formed in a plate shape.   The substrate has a second conductor at a ground potential;
  The electronic unit according to claim 9, wherein the first wiring and the second wiring are arranged on the substrate between the first conductor and the second conductor.   The electronic unit according to claim 11, wherein the second conductor is formed in a plate shape. The substrate is a core substrate including a metal core layer,
Wherein the first conductor is, the electronic unit according to any one of claims 12 to claim 9 is the metal core layer. The image sensor has a first electronic circuit to which a current is supplied by the first wiring, and a second electronic circuit provided at a position different from the first electronic circuit,
The substrate includes a first terminal pair to flow a current supplied to the first electronic circuit, the connector having a second terminal pair to flow a current supplied to the second electronic circuits are arranged,
The first terminal pair is disposed closer to the first electronic circuit than the second terminal pair ,
14. The electronic unit according to claim 1, wherein the second terminal pair is disposed closer to the second electronic circuit than the first terminal pair. 15. Wherein the first electronic circuit, an electronic unit according to claim 14 having a processing circuit for processing the picture element signals. The image sensor has a pixel element that outputs a pixel signal and a vertical signal line that transmits the pixel signal,
The electronic unit includes:
A first connection wiring provided substantially parallel to the first surface on the substrate and connected to the first wiring;
A second connection wiring provided substantially parallel to the first surface on the substrate and connected to the second wiring;
And near the connecting portion between the first wiring and the first connection wiring, Bei give a, a capacitor connected between the vicinity of the second connecting line and the second wiring and the connecting portion,
The first connection wiring is located between the first wiring and the imaging element in a current path between the first wiring and the imaging element;
The second connection wiring is located between the second wiring and the imaging element in a current path between the second wiring and the imaging element,
The first connection wiring, the current supplied from the capacitor to the image sensor, the vertical signal line flows in a direction substantially orthogonal to the transmission direction of transmitting the pixel signal,
The electronic device according to claim 1, wherein the second connection wiring causes a current supplied from the capacitor to the image sensor and returned from the image sensor to flow in a direction substantially orthogonal to the transmission direction. unit. Further comprising a flexible substrate mounted on the substrate,
The flexible substrate includes a third wire current supplied to the imaging element from the first power source is the flow, are disposed along the front Symbol third wiring, a current flowing from the imaging element to said first power supply flows The electronic unit according to any one of claims 1 to 16 , further comprising: a fourth wiring . The electronic unit according to claim 17 , wherein the flexible substrate has a third wiring layer including the third wiring and the fourth wiring . The flexible substrate has a ground layer,
The electronic unit according to claim 18 , wherein the ground layer is disposed between the third wiring layer and the substrate. The flexible substrate includes a third wiring layer including the third wiring, and a fourth wiring layer including the fourth wiring,
Wherein at least a portion of the surface of the third wiring electronic unit according to claim 17 which is positioned to face the at least a portion of a surface of the fourth wire. The electronic unit according to any one of claims 17 to 20, wherein the flexible substrate is arranged to face the substrate . The imaging device, have a vertical signal line for transmitting a pixel element and the pixel signal and outputs the pixel signal,
The third wiring and the fourth wiring are arranged at least in a direction in which the flexible substrate is arranged to face the substrate at an angle within a range from 45 ° to 90 ° with the vertical signal line. An electronic unit according to any one of claims 17 to 21 . The imaging device includes a processing circuit for processing the picture element signals,
The electronic unit according to any one of claims 17 to 22, wherein the third wiring and the fourth wiring are arranged at a position closer to the processing circuit than other wirings of the flexible substrate.   An image sensor having a pixel portion in which a plurality of unit cells that output pixel signals are arranged;
  A substrate on which the image sensor is arranged,
  The substrate is disposed along the first wiring, in which a current flows in a direction from the first power supply to the image sensor, below the pixel unit, and the substrate is disposed along the first wiring and travels from the image sensor to the first power supply. And a second wiring through which a current flows in the direction.   The electronic unit according to claim 24, wherein the substrate has a first wiring layer including the first wiring and a second wiring layer including the second wiring. 26. The electronic unit according to claim 25, wherein the first wiring layer and the second wiring layer are arranged adjacent to each other on the substrate.   The first wiring is formed as a power supply pattern,
  The electronic unit according to any one of claims 24 to 26, wherein the second wiring is formed as a ground pattern.   The electronic unit according to claim 27, wherein at least a part of the ground pattern is arranged to face at least a part of the power supply pattern.   The electronic unit according to claim 24, wherein the substrate has a wiring layer including the first wiring and the second wiring. The first wiring is formed as a power supply pattern,
  30. The electronic unit according to claim 29, wherein the second wiring is formed as a ground pattern.   Further comprising a flexible substrate mounted on the substrate,
  The flexible substrate includes a third wiring through which a current supplied from the first power supply to the imaging device flows, and a fourth wiring arranged along the third wiring, wherein a current flowing from the imaging device to the first power supply flows. 31. The electronic unit according to claim 24, further comprising a wiring.   32. The electronic unit according to claim 31, wherein the flexible substrate has a third wiring layer including the third wiring and the fourth wiring.   The flexible substrate includes a third wiring layer including the third wiring, and a fourth wiring layer including the fourth wiring,
  32. The electronic unit according to claim 31, wherein at least a part of a surface of the third wiring is arranged so as to face at least a part of a surface of the fourth wiring.   The electronic unit according to any one of claims 31 to 33, wherein the flexible substrate is arranged to face the substrate.   The image sensor has a vertical signal line transmitting the pixel signal,
  The third wiring and the fourth wiring are arranged at least in a direction in which the flexible substrate is arranged to face the substrate at an angle within a range from 45 ° to 90 ° with the vertical signal line. An electronic unit according to any one of claims 31 to 34.   The image sensor has a processing circuit that processes the pixel signal,
  The electronic unit according to any one of claims 31 to 35, wherein the third wiring and the fourth wiring are arranged at a position closer to the processing circuit than other wirings of the flexible substrate.

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