JP2017103517A - Electronic unit, imaging apparatus and flexible substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce influences that are exerted upon an electronic unit or the outside of the electronic unit by at least one of a magnetic field and an electric field generated by a current supplied from a power source to an electronic component.SOLUTION: An electronic unit comprises: a substrate; an electronic component provided on the substrate; first wiring which is provided on the substrate and through which a current supplied from a first power source to the electronic component is made flow in a first direction; and second wiring which is provided on the substrate along the first wiring and through which a current supplied through the first wiring to the electronic component and returned from the electronic component to the first power source is made flow in a second direction substantially opposite to the first direction in the vicinity of the first wiring. The electronic unit comprises: a substrate; an imaging device provided on the substrate and including a pixel element for outputting a pixel signal and a vertical signal line for transmitting the pixel signal; and wiring provided substantially in parallel with a face of the substrate on which the imaging element is provided, for causing a current supplied from a capacitor to at least one of the imaging element and another electronic component provided on the substrate, to flow in a direction substantially orthogonal to a direction in which the vertical signal line transmits the pixel signal.SELECTED DRAWING: None

Description

  The present invention relates to an electronic unit, an imaging device, and a flexible substrate.

Conventionally, an electronic element module including an electronic element mounted on a substrate is known.
However, the conventional electronic element module has a problem that noise cannot be removed.
[Prior art documents]
[Patent Literature]
[Patent Document 1] JP 2010-45082 A

  In the first aspect, the electronic unit includes a substrate, an electronic component provided on the substrate, a first wiring provided on the substrate and configured to flow a current supplied from the first power source to the electronic component in a first direction. The second current that is provided on the substrate along the first wiring and is supplied to the electronic component through the first wiring and returns from the electronic component to the first power source is a second that is substantially opposite to the first direction in the vicinity of the first wiring. And a second wiring that flows in the direction.

  In the second aspect, the electronic unit is provided on the substrate, the electronic component provided on the substrate, the first wiring provided on the substrate and supplying a current supplied from the first power source to the electronic component, and the substrate. And a second wiring that supplies a current that is supplied to the electronic component through the first wiring and returns from the electronic component to the first power source, and the second wiring includes a magnetic field and an electric field generated by the current that flows through the second wiring and returns to the first power source. Is provided along the first wiring so that at least one of the magnetic field and the electric field due to the current supplied to the electronic component through the first wiring is canceled.

  In the third aspect, the electronic unit includes a substrate, an image sensor that is provided on the substrate and has a pixel element that outputs a pixel signal and a vertical signal line that transmits the pixel signal, and a surface on which the image sensor is provided on the substrate. And a wiring for flowing a current supplied from the capacitor to at least one of the image sensor and other electronic components provided on the substrate in a direction substantially perpendicular to the direction in which the vertical signal line transmits the pixel signal. Is provided.

  In a fourth aspect, an imaging device includes the electronic unit.

  In the fifth aspect, the flexible substrate is provided along the first wiring adjacent to the first wiring, the first wiring for flowing the current supplied from the first power source to the electronic component in the first direction, And a second wiring that supplies a current that is supplied to the electronic component through the first wiring and returns from the electronic component to the first power supply in a second direction substantially opposite to the first direction.

  In the sixth aspect, the flexible substrate flows a first wiring for supplying a current supplied from the first power source to the electronic component, and a current supplied to the electronic component through the first wiring and returning from the electronic component to the first power source. And the second wiring includes at least one of a magnetic field and an electric field generated by a current flowing through the second wiring and returning to the first power source, and a magnetic field and an electric field generated by a current supplied through the first wiring to the electronic component. Are provided along the first wiring so that at least one of them is canceled out.

  It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

1 is a cross-sectional view schematically showing a camera 10. FIG. It is a top view which shows typically the imaging unit 40 which concerns on 1st Embodiment. 4 is a cross-sectional view schematically showing a cross section AA of the imaging unit 40. FIG. 4 is a cross-sectional view schematically showing a BB cross section of the imaging unit 40. FIG. An example of a power supply pattern included in the wiring layer 214 and a ground pattern included in the wiring layer 216 are schematically shown. 2 is a bottom view schematically showing the imaging chip 100. FIG. 2 is a diagram schematically illustrating a configuration of a circuit block formed on the imaging chip 100. FIG. It is sectional drawing which represents typically the imaging unit 2040 which concerns on 2nd Embodiment. It is sectional drawing which represents typically the imaging unit 3040 which concerns on 3rd Embodiment. It is sectional drawing which represents typically the imaging unit 4040 which concerns on 4th Embodiment. It is sectional drawing which represents typically the imaging unit 5040 which concerns on 5th Embodiment. It is a bottom view which shows typically the mounting substrate 120 with which the flexible substrate 600 was mounted | worn. FIG. 6 is a cross-sectional view schematically showing the imaging unit 40 with the flexible substrate 600 attached. 4 is a cross-sectional view schematically showing a flexible substrate 700 and an imaging unit 40. FIG. 4 is a cross-sectional view schematically showing a flexible substrate 800 and an imaging unit 40. FIG. It is a bottom view which shows typically the mounting substrate 6120 with which the flexible substrate 900 was mounted | worn.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

  FIG. 1 is a cross-sectional view schematically showing a camera 10 according to the embodiment. The camera 10 is a single-lens reflex camera that is an example of an imaging apparatus. The camera 10 includes a lens unit 20 and a camera body 30. The lens unit 20 is attached to the camera body 30. The lens unit 20 includes an optical system arranged along the optical axis 22 in the lens barrel, and guides an incident subject light flux to the imaging unit 40 of the camera body 30.

  In the present embodiment, the direction along the optical axis 22 is defined as the z-axis direction. That is, the direction in which the subject light beam enters the imaging chip 100 included in the imaging unit 40 is defined as the z-axis direction. Specifically, the direction in which the subject luminous flux is incident is defined as the z-axis minus direction, and the opposite direction is defined as the z-axis plus direction. The longitudinal direction of the imaging chip 100 is defined as the x-axis direction. The short direction of the imaging chip 100 is defined as the y-axis direction. Specifically, the x-axis direction and the y-axis direction are determined in the directions illustrated in FIG. The x-axis, y-axis, and z-axis are right-handed orthogonal coordinate systems. For convenience of explanation, the z-axis plus direction may be referred to as the front side, the front side, the upper side, the upper surface side, or the like. Further, the negative z-axis direction may be referred to as the rear side, the rear side, the lower side, the back side, or the like. Further, a view when viewed in the z-axis minus direction from a position in the z-axis plus direction may be referred to as a top view or the like. Further, a view when viewed in the z-axis plus direction from a position in the z-axis minus direction may be referred to as a bottom view or the like.

  The camera body 30 has a mirror unit 31 at a position in the negative z-axis direction from the body side mount 26 coupled to the lens side mount 24. The mirror unit 31 includes a main mirror 32 and a sub mirror 33. The main mirror 32 is rotatably supported between an entry position where it enters the optical path of the subject light beam emitted from the lens unit 20 and a retreat position where it is retracted from the optical path of the subject light flux. The sub mirror 33 is rotatably supported with respect to the main mirror 32. The sub mirror 33 enters the entry position together with the main mirror 32 and retracts to the retract position together with the main mirror 32. As described above, the mirror unit 31 takes the approach state in which the subject light flux enters the optical path and the retreat state in which the subject light flux is retracted.

  When the mirror unit 31 is in the entering state, a part of the subject light beam incident on the main mirror 32 is reflected by the main mirror 32 and guided to the focus plate 80. The focus plate 80 is disposed at a position conjugate with the imaging surface of the imaging chip 100 included in the imaging unit 40, and visualizes the subject image formed by the optical system of the lens unit 20. The subject image formed on the focus plate 80 is observed from the finder window 86 through the pentaprism 82 and the finder optical system 84.

  When the mirror unit 31 is in the entering state, light beams other than the subject light beam reflected by the main mirror 32 out of the subject light beam incident on the main mirror 32 enter the sub mirror 33. Specifically, the main mirror 32 has a half mirror area, and the subject light flux that has passed through the half mirror area of the main mirror 32 enters the sub mirror 33. The sub mirror 33 reflects the light beam incident from the half mirror region toward the imaging optical system 70. The imaging optical system 70 guides the incident light beam to a focus detection sensor 72 for detecting the focus position. The focus detection sensor 72 outputs the focus position detection result to the MPU 51.

  The focus plate 80, the pentaprism 82, the main mirror 32, the sub mirror 33, and the finder optical system 84 are supported by a mirror box 60 as a support member. When the mirror unit 31 is in the retracted state and the front curtain and the rear curtain of the shutter unit 38 are in the open state, the subject luminous flux that passes through the lens unit 20 reaches the imaging surface of the imaging chip 100.

  A substrate 62 and a display unit 88 are sequentially arranged at a position in the negative z-axis direction of the imaging unit 40. As the display unit 88, for example, a liquid crystal panel or the like can be applied. The display surface of the display unit 88 appears on the back surface of the camera body 30. The display unit 88 displays an image generated from the output signal from the imaging chip 100.

  Electronic circuits such as MPU 51 and ASIC 52 are mounted on the substrate 62. The MPU 51 is responsible for overall control of the camera 10. An output signal from the imaging chip 100 is output to the ASIC 52 via a flexible board such as a flexible printed board. The ASIC 52 processes the output signal output from the imaging chip 100.

  The ASIC 52 generates image data for display based on the output signal from the imaging chip 100. The display unit 88 displays an image based on the display image data generated by the ASIC 52. The ASIC 52 generates image data for recording based on the output signal from the imaging chip 100. The ASIC 52 generates image data for recording by performing, for example, image processing or compression processing on the output signal of the imaging chip. The recording image data generated by the ASIC 52 is recorded on a recording medium attached to the camera body 30. The camera body 30 has a configuration in which a recording medium can be attached and detached.

  FIG. 2 is a top view schematically showing the imaging unit 40 according to the first embodiment. FIG. 3 is a cross-sectional view schematically showing an AA cross section of the imaging unit 40. FIG. 4 is a cross-sectional view schematically showing a BB cross section of the imaging unit 40. The imaging unit 40 includes an imaging chip 100, a mounting substrate 120, a frame 140, and a cover glass 160.

  The imaging chip 100 is a CMOS image sensor or a CCD image sensor. The imaging chip 100 includes an imaging area 101 and a peripheral area 102. The imaging region 101 is formed in the central portion of the imaging chip 100 in a plane parallel to xy. In the imaging region 101 of the imaging chip 100, an imaging surface is formed by a plurality of photoelectric conversion elements that photoelectrically convert subject light. The peripheral area 102 of the imaging chip 100 is located around the imaging area 101. The peripheral area 102 of the imaging chip 100 includes a processing circuit that reads out a pixel signal obtained by photoelectric conversion in the photoelectric conversion element and performs signal processing. The processing circuit includes a circuit that converts the output pixel signal into a digital signal. The imaging chip 100 has a rectangular shape on the xy plane. The imaging chip 100 has a first short side 105a and a second short side 105b, and a first long side 106a and a second long side 106b. The first short side 105a is located in the x-axis plus direction from the second short side 105b. The first long side 106a is positioned in the y-axis plus direction from the second long side 106b.

  The imaging chip 100 is provided on the mounting substrate 120. The imaging chip 100 is mounted on the mounting substrate 120. The imaging chip 100 is mounted on the mounting substrate 120 by COB (Chip On Board). The imaging chip 100 is mounted on the first main surface 111 of the mounting substrate 120. The imaging chip 100 is mounted by being bonded to the mounting substrate 120.

  Specifically, the imaging chip 100 is bonded to the solder resist layer 201 of the mounting substrate 120. The imaging chip 100 is bonded to the solder resist layer 201 with an adhesive. An adhesive that adheres the imaging chip 100 to the mounting substrate 120 is, for example, a thermosetting adhesive. The imaging chip 100 is bonded and fixed to the mounting substrate 120 by, for example, thermosetting a thermosetting adhesive.

  The imaging chip 100 is electrically connected to the mounting substrate 120 via bonding wires including a bonding wire 110a, a bonding wire 110b, a bonding wire 110c, and a bonding wire 110d. The plurality of bonding wires may be collectively referred to as bonding wires 110.

  The bonding wire 110 is mounted on the bonding lead 240 of the mounting substrate 120 and the imaging chip 100. The bonding wire 110 electrically connects the imaging chip 100 and the bonding lead 240 through a wire bonding process (bonding wire mounting process). The pixel signal converted into a digital signal by the processing circuit of the imaging chip 100 is output to the mounting substrate 120 via the bonding wire 110.

  The mounting substrate 120 mounts the imaging chip 100. The mounting substrate 120 includes a first layer 121, a core layer 209, and a second layer 122. The first layer 121 includes a solder resist layer 201, a wiring layer 202, an insulating layer 203, a wiring layer 204, an insulating layer 205, and a wiring layer 206. The second layer 122 includes a wiring layer 216, an insulating layer 215, a wiring layer 214, an insulating layer 213, a wiring layer 212, and a solder resist layer 211. The mounting substrate 120 is a multilayer core substrate having a core layer 209 as a core layer.

  In the mounting substrate 120, the imaging chip 100, the first layer 121, the core layer 209, and the second layer 122 are arranged in the order of the imaging chip 100, the first layer 121, the core layer 209, and the second layer 122 along the optical axis 22. Arranged at. Specifically, on the mounting substrate 120, along the optical axis 22, the imaging chip 100, the solder resist layer 201, the wiring layer 202, the insulating layer 203, the wiring layer 204, the insulating layer 205, the wiring layer 206, the core layer 209, The wiring layer 216, the insulating layer 215, the wiring layer 214, the insulating layer 213, the wiring layer 212, and the solder resist layer 211 are arranged in this order.

  The insulating layer 203, the insulating layer 205, the insulating layer 215, and the insulating layer 213 are, for example, resin layers. The thickness of each of the insulating layer 203, the insulating layer 205, the insulating layer 215, and the insulating layer 213 is 20 μm to 50 μm. The thickness is a length in the z-axis direction.

  The wiring layer 202, the wiring layer 204, the wiring layer 206, the wiring layer 216, the wiring layer 214, and the wiring layer 212 include a wiring pattern. As a material of the wiring layer 202, the wiring layer 204, the wiring layer 206, the wiring layer 216, the wiring layer 214, and the wiring layer 212, an alloy of nickel and iron (for example, 42 alloy, 56 alloy), copper, aluminum, or the like can be used. The thickness of each of the wiring patterns included in the wiring layer 202, the wiring layer 204, the wiring layer 206, the wiring layer 216, the wiring layer 214, and the wiring layer 212 is about 10 μm to 50 μm.

  The core layer 209 is made of resin. When the core layer 209 is formed of resin, the core layer 209 may be formed using, for example, a material having a higher elastic modulus than FR4 and FR4. The thickness of the core layer 209 is greater than the thickness of any of the wiring layers 202, 204, 204, 206, 216, 214, and 212. The thickness of the core layer 209 is larger than the thickness of any of the insulating layers 203, 205, 215, and 213. Specifically, the thickness of the core layer 209 is about 0.1 mm to 0.8 mm. The rigidity of the core layer 209 is higher than the rigidity of any of the wiring layers 202, 204, 204, 206, 216, 214, and 212. The rigidity of the core layer 209 may be higher than the rigidity of the first layer 121. The rigidity of the core layer 209 may be higher than the rigidity of the second layer 122.

  Thus, the mounting substrate 120 is a multilayer core substrate having a resin core. The thickness of the mounting substrate 120 may be about 0.3 mm to 1.0 mm as a whole.

  At least a part of the wiring layer 202 is used for a wiring pattern that receives a pixel signal output from the imaging chip 100 via the bonding wire 110. Further, at least a part of the wiring layer 202 is used for a wiring pattern that supplies a power supply current supplied to the imaging chip 100 to the bonding wires 110. Further, at least a part of the wiring layer 202 is supplied to the imaging chip 100 as a power supply current, and used for a wiring pattern that receives a return current output from the imaging chip 100 via the bonding wires 110.

  The wiring layer 202 includes bonding leads 240 to which the bonding wires 110 are connected. The wiring layer 202 receives the pixel signal output from the imaging chip 100 via the bonding wire 110 by the bonding lead 240. Further, the wiring layer 202 outputs a power supply current to the imaging chip 100 to the bonding wire 110 via the bonding lead 240. Further, the wiring layer 202 receives the return current output from the imaging chip 100 via the bonding wire 110 by the bonding lead 240.

  The wiring layer 202 is electrically connected to each of the wiring layer 204, the wiring layer 206, the wiring layer 216, the wiring layer 214, and the wiring layer 212, and vias including the via 131a, the via 131b, the via 131c, the via 131d, and the via 131e. Connected. For example, the bonding lead 240 is electrically connected to each of the wiring layer 204, the wiring layer 206, the wiring layer 216, the wiring layer 214, and the wiring layer 212 through vias.

  For example, the pixel signal output from the imaging chip 100 is transmitted to the bonding lead 240 of the wiring layer 202 via the bonding wire 110c and the bonding wire 110d, and a via that electrically connects the wiring layer 202 and the wiring layer 212. The data is transmitted to the wiring layer 212 via 131d and via 131e.

  The wiring pattern included in the wiring layer 204, the wiring pattern included in the wiring layer 206, the wiring pattern included in the wiring layer 216, and the wiring pattern included in the wiring layer 214 include, for example, a part of the ground line, the power line Can be used for some parts. That is, the wiring pattern included in the wiring layer 204, the wiring pattern included in the wiring layer 206, the wiring pattern included in the wiring layer 216, and the wiring pattern included in the wiring layer 214 are used as a ground wiring pattern and a power wiring pattern. Is done.

  An electronic component is mounted on the second main surface 112 opposite to the first main surface 111 of the mounting substrate 120. For example, the electronic component mounted on the second main surface 112 is provided on the solder resist layer 211. The electronic component mounted on the second main surface 112 and the wiring layer 212 are electrically connected by a lead member. The lead member is fixed to the wiring layer 212 with solder or the like. A part of the wiring layer 212 is exposed to the outside through an opening formed in the solder resist layer 211 to provide an electrode such as a land for connecting the lead member. The electronic components provided on the second main surface 112 include, for example, mechanical components such as a connector 181, passive components such as a capacitor 182 and a resistor 183, active components such as a transistor 184 and a regulator.

  The connector 181 is electrically connected to the wiring layer 212. For example, a pixel signal transmitted from the imaging chip 100 to the wiring layer 212 through the bonding wire 110, the wiring layer 202, and the via is transmitted to the connector 181 through the wiring layer 212. For example, a flexible substrate is attached to the connector 181. The flexible substrate attached to the connector 181 transmits the pixel signal transmitted to the connector 181 to the ASIC 52.

  Further, the flexible substrate attached to the connector 181 outputs the power supplied to the imaging chip 100 to the connector 181. The electric power supplied by the flexible substrate is supplied from a battery unit included in the camera body 30. The power output from the flexible substrate to the connector 181 is output to the power supply wiring pattern through the wiring layer 212, directly or through a power supply circuit such as a regulator, and supplied to the imaging chip 100. The flexible substrate will be described later with reference to FIGS.

  In the imaging unit 40, the wiring pattern included in the wiring layer 204 and the wiring pattern included in the wiring layer 216 are used as a ground wiring pattern. Further, the wiring pattern included in the wiring layer 214 is used as a power supply wiring pattern.

  The wiring layer 204 has a ground pattern 490. The ground pattern 490 is electrically connected to the bonding wire 110a through the via 131a. The ground pattern 490 is a solid pattern.

  The wiring layer 216 includes a ground pattern 400 and a ground pattern 480. The ground pattern 400 is electrically connected to the bonding wire 110b through the via 131b. The ground pattern 480 is a planar pattern. The ground pattern 480 is substantially a solid pattern. The ground pattern 480 may be electrically connected to the ground pattern 490 through a via.

  As shown in FIGS. 3 and 4, the wiring layer 214 includes a power supply pattern 300, a power supply pattern 310, a power supply pattern 320, a power supply pattern 330, a power supply pattern 340, a power supply pattern 350, and a power supply pattern 360. Have. The power supply pattern 300, the power supply pattern 310, the power supply pattern 320, the power supply pattern 330, the power supply pattern 340, the power supply pattern 350, and the power supply pattern 360 are power supply patterns for power supplies that are independent from each other. The power supply pattern 300 is electrically connected to the bonding wire 110 for power supply current through a via. The power supply pattern 310 is electrically connected to another power supply current bonding wire 110 through another via. Similarly, the power supply pattern 320, the power supply pattern 330, the power supply pattern 340, the power supply pattern 350, and the power supply pattern 360 are electrically connected to the corresponding bonding wires 110 for power supply current through vias.

  The power transmitted to the wiring layer 212 from the flexible board attached to the connector 181 is directly or via a power supply circuit via the via 131c that electrically connects the wiring layer 212 and the power supply pattern 300. 300. The power supplied to the power supply pattern 300 is supplied to the wiring layer 202 through a via that electrically connects the power supply pattern 300 and the wiring layer 202, and is supplied to the imaging chip 100 through the bonding wire 110. Therefore, the power supply current to the imaging chip 100 is supplied to the imaging chip 100 from the power supply pattern 300 via the vias that electrically connect the power supply pattern 300 and the wiring layer 202, the wiring layer 202, and the bonding wires 110. Supplied.

  A return current supplied from the power supply pattern 300 to the imaging chip 100 as a power supply current and output from the imaging chip 100 is output to the wiring layer 202 via the bonding wire 110b, and the wiring layer 202 and the ground pattern 400 are electrically connected. The signal is output to the ground pattern 400 via the connecting via 131b. The return current output to the ground pattern 400 is output to the wiring layer 212 through a via that electrically connects the ground pattern 400 and the wiring layer 212.

  The electric power supplied from the power supply pattern 310 is supplied to the wiring layer 202 through vias that electrically connect the power supply pattern 310 and the wiring layer 202, and is supplied to the imaging chip 100 through the bonding wires 110. A return current supplied from the power supply pattern 310 to the imaging chip 100 as a power supply current and output from the imaging chip 100 is output to the ground pattern 480 or the ground pattern 490 via the via. Similarly, for the power supplied to the imaging chip 100 from the power supply pattern 320, the power supply pattern 330, the power supply pattern 340, the power supply pattern 350, and the power supply pattern 360, the return current output from the imaging chip 100 is the ground pattern 480 or the ground pattern. 490 is output.

  The instantaneous value of the power supply current supplied from the power supply pattern 300 to the imaging chip 100 is relatively large. During the reading operation of the imaging chip 100, the power supply current from the power supply pattern 300 to the imaging chip 100 changes greatly with time. For example, a power supply current supplied from the power supply pattern 300 to the imaging chip 100 is supplied to a processing circuit for CDS that performs a CDS (correlated double sampling) process of the imaging chip 100. The processing circuit for CDS repeats operation and non-operation at high speed during the reading operation of the imaging chip 100. The currents flowing through the power supply pattern 300 and the ground pattern 400 change according to the operating state of the CDS processing circuit. When the CDS processing circuit switches from the non-operating state to the operating state, a rush current flows through the power supply pattern 300 and the ground pattern 400.

  Here, the ground pattern 400 is provided corresponding to the power supply pattern 300 so that the electromagnetic wave generated by the current flowing through the power supply pattern 300 is weakened by the electromagnetic wave generated by the current flowing through the ground pattern 400. An example of the ground pattern 400 and the power supply pattern 300 will be described later.

  The imaging chip 100 is accommodated in the opening 138 of the frame 140. The frame 140 is an example of a surrounding member that surrounds the imaging chip 100. The frame 140 is bonded to the mounting substrate 120. Specifically, the frame 140 is bonded to the solder resist layer 201 of the mounting substrate 120. The frame 140 is bonded with, for example, an adhesive. An adhesive that bonds the frame 140 to the mounting substrate 120 is, for example, a thermosetting adhesive. The frame 140 is mounted on the mounting substrate 120 in an adhesive manner by thermosetting a thermosetting adhesive. In the frame mounting process, when the frame 140 is mounted on the mounting substrate 120, the frame 140 is mounted on the heated mounting substrate 120 by thermocompression bonding.

  The frame 140 has a first surface 141, a second surface 142, a third surface 143, a fourth surface 144, a fifth surface 145, and a sixth surface 146. The sixth surface 146 forms an opening 138. The sixth surface 146 forms the inner wall surface of the frame 140. The opening 138 is formed at, for example, a central portion in the xy plane.

  The first surface 141 is a surface bonded to the cover glass 160. The first surface 141 is a surface in contact with the end of the sixth surface 146. The first surface 141 is formed along the outer edge of the sixth surface 146. The first surface 141 is a surface substantially parallel to the xy plane.

  The second surface 142 is a surface in contact with the end of the first surface 141. The second surface 142 is a surface formed along the outer edge of the first surface 141. The second surface 142 has a surface substantially parallel to the yz plane and a surface substantially parallel to the xz plane.

  The third surface 143 is a surface in contact with the end of the second surface 142. The third surface 143 is a surface substantially parallel to the xy plane and a surface substantially parallel to the first surface 141.

  The fourth surface 144 is a surface in contact with the end of the third surface 143. The fourth surface 144 is a surface formed along the outer edge of the third surface 143. The fourth surface 144 has a surface substantially parallel to the yz plane and a surface substantially parallel to the xz plane.

  The fifth surface 145 is a surface in contact with the end of the fourth surface 144. The fifth surface 145 is a surface formed along the outer edge of the fourth surface 144. The fifth surface 145 is a surface substantially parallel to the xy plane. The fifth surface 145 is a surface substantially parallel to the first surface 141 and the third surface 143. The fifth surface 145 is a surface that is bonded to the solder resist layer 201 of the mounting substrate 120. The fifth surface 145 is a surface in contact with the end of the sixth surface 146. The fifth surface 145 is formed along the outer edge of the sixth surface 146.

  The frame 140 has a step portion formed by the first surface 141, the second surface 142, and the third surface 143. The frame 140 has a mounting hole 148 as a mounting portion. The frame 140 has, for example, three attachment holes 148. All of the three attachment holes 148 pass through the third surface 143 to the fifth surface 145. All of the three attachment holes 148 are used for attaching the imaging unit 40 to another structure such as the mirror box 60.

  The frame 140 is fixed to the bracket 150 by, for example, being screwed with three screws through the three mounting holes 148. The bracket 150 is fixed to the mirror box 60 by, for example, screwing. Therefore, the imaging unit 40 is fixed to the mirror box 60.

  When the frame 140 and the bracket 150 are screwed with, for example, metal screws using the mounting holes 148, heat generated when the imaging chip 100 is operating is heated toward the mirror box 60 via the screws. It is possible to form a heat transfer path for releasing the heat.

  The frame 140 has a positioning hole 147. The frame 140 has two positioning holes 147, for example. Each of the two positioning holes 147 is a hole penetrating from the third surface 143 to the fifth surface 145. Any of the positioning holes 147 is used to position the imaging unit 40 with respect to the imaging unit 40. Of the two positioning holes 147, one positioning hole is a fitting hole, and the other positioning hole 147 is a long hole.

  The frame 140 is positioned with respect to the bracket 150 using the two positioning holes 147. For example, the frame 140 and the bracket 150 are positioned by inserting two positioning pins provided on the bracket 150 into the two positioning holes 147. The frame 140 is fixed while being positioned with respect to the bracket 150. Therefore, the imaging unit 40 is fixed while being positioned on the mirror box 60. The frame 140 and the bracket 150 may be fixed to a structure other than the mirror box 60.

  The imaging unit 40 may be fixed to the mirror box 60 without using the bracket 150. The imaging unit 40 may be fixed to the mirror box 60 by, for example, screwing through the three mounting holes 148.

  The cover glass 160 is used for sealing the imaging chip 100. Cover glass 160 is fixed to frame 140 so as to cover opening 138 of frame 140. The cover glass 160 uses the opening 138 as a sealed space together with the frame 140 and the mounting substrate 120.

  Cover glass 160 is bonded to frame 140. The cover glass 160 is bonded to the frame 140 with an adhesive. The adhesive that bonds the cover glass 160 to the frame 140 is, for example, a photo-curing adhesive. The photocurable adhesive that bonds the cover glass 160 to the frame 140 is, for example, an ultraviolet curable adhesive. The cover glass 160 is bonded and fixed to the frame 140 by curing an ultraviolet curable adhesive with ultraviolet rays. As a material for the cover glass 160, borosilicate glass, quartz glass, non-alkali glass, heat-resistant glass, or the like can be used. The cover glass 160 has translucency. The thickness of the cover glass 160 is 0.5 mm to 0.8 mm.

  The cover glass 160 is fixed to the frame 140 after the imaging chip 100, the bonding wire 110 and the frame 140 are mounted on the mounting substrate 120. Since the cover glass 160 has a light-transmitting property, the cover glass 160 and the frame 140 can be bonded using a photo-curing adhesive. The cover glass 160 is an example of a translucent member. As the translucent member, quartz or the like can be applied in addition to glass.

  Thus, the mounting space is formed by the mounting substrate 120, the frame 140, and the cover glass 160. The imaging chip 100 is disposed in a sealed space formed by the mounting substrate 120, the frame 140, and the cover glass 160. As a result, the imaging chip 100 is less affected by the external environment. For example, the imaging chip 100 is not easily affected by moisture existing outside the sealed space. Therefore, deterioration of the imaging chip 100 can be prevented.

  FIG. 5 schematically shows an example of the power supply pattern included in the wiring layer 214 and the ground pattern included in the wiring layer 216. FIG. 5A schematically shows a power supply pattern included in the wiring layer 214. FIG. 5A is a top view when the insulating layer 213 and the wiring layer 214 are taken out from the imaging unit 40. FIG. 5B schematically shows a ground pattern included in the wiring layer 216. FIG. 5B is a top view when the insulating layer 215 and the wiring layer 216 are taken out from the imaging unit 40.

  FIG. 6 is a bottom view schematically showing the mounting substrate 120. 6 is intended to schematically show the positional relationship between the connector 181 and the capacitor 182, and in FIG. 6, the electronic components other than the connector 181 and the capacitor 182, the wiring layer 212, and the like are not shown. The connector 181 includes n terminals as lead members. Specifically, the connector 181 includes a first terminal 281, a second terminal 282, an n−1 terminal 283, and an nth terminal 284. The first terminal 281 and the second terminal 282 are a pair of terminals located on the most positive side in the y-axis direction among the terminals included in the connector 181. The (n−1) th terminal 283 and the nth terminal 284 are terminal pairs that are located on the most minus side in the y-axis direction among the terminals of the connector 181.

  The ground pattern 400 functions as a ground for the power supply pattern 300. The ground pattern 480 functions as a ground for the power supply pattern 310, the power supply pattern 320, the power supply pattern 330, the power supply pattern 340, the power supply pattern 350, and the power supply pattern 360.

  As shown in FIG. 5A, the power supply pattern 300 includes a power supply connection portion 302, a current flow portion 301, and a chip connection portion 303. The power connection unit 302 is electrically connected to the first terminal 281 of the connector 181 through a via. The chip connection unit 303 is connected to the wiring layer 202 through a via.

  The current flow part 301 is a part between the power supply connection part 302 and the chip connection part 303. The current flow part 301 extends along the y-axis direction. Specifically, the current flow part 301 is a rectangular pattern portion having a long side along the y axis and a short side along the x axis. The current flow unit 301 is connected to the power supply connection unit 302 on the y-axis plus side, and is connected to the chip connection unit 303 on the y-axis minus side. That is, the y-axis plus side of the current flow part 301 is connected to the y-axis minus side of the power supply connection part 302, and the y-axis minus side of the current flow part 301 is connected to the y-axis plus side of the chip connection part 303. To do.

  At least a part of the power supply pattern 300 is located below the imaging region 101. Specifically, at least a part of the current flow unit 301 is located below the imaging region 101. More specifically, when the current flow unit 301 and the imaging region 101 are projected on the xy plane, at least a part of the current flow unit 301 overlaps a part of the imaging region 101.

  The ground pattern 400 includes a power supply connection unit 402, a current flow unit 401, and a chip connection unit 403. The power supply connection unit 402 is electrically connected to the second terminal 282 of the connector 181 through a via. The chip connection unit 403 is connected to the wiring layer 202 through a via.

  The power connection unit 402 is a pattern portion corresponding to the power connection unit 302. The chip connection unit 403 is a pattern portion corresponding to the chip connection unit 303. The current flow portion 401 is a pattern portion corresponding to the current flow portion 301.

  The current flow part 401 is a part between the power supply connection part 402 and the chip connection part 403. The current flow part 401 extends in a direction substantially parallel to the direction in which the current flow part 301 extends. Specifically, the current flow part 401 extends along the y-axis direction. The current conducting portion 401 is a rectangular pattern portion having a long side along the y axis and a short side along the x axis. The current flow unit 401 is connected to the power supply connection unit 402 on the y-axis plus side, and is connected to the chip connection unit 403 on the y-axis minus side. That is, the y-axis plus side of the current flow unit 401 is connected to the y-axis minus side of the power supply connection unit 402, and the y-axis minus side of the current flow unit 401 is connected to the y-axis plus side of the chip connection unit 403. To do.

  At least a part of the ground pattern 400 is located below the imaging region 101. Specifically, at least a part of the current flow unit 401 is located below the imaging region 101. More specifically, when the current flow unit 401 and the imaging region 101 are projected on the xy plane, at least a part of the current flow unit 401 overlaps a part of the imaging region 101.

  In the power supply pattern 300, the current supplied from the first terminal 281 of the connector 181 is transmitted via the first terminal 281 of the connector 181 and vias that electrically connect the first terminal 281 and the power supply connection portion 302. It flows into the power supply connection unit 302. The current that has flowed into the power supply connection portion 302 flows out from the y-axis minus side of the power supply connection portion 302 and flows into the y-axis plus side of the current flow portion 301. The current flowing into the current flow part 301 flows through the current flow part 301 in the negative y-axis direction, flows out of the current flow part 301 from the negative y-axis side, and flows into the chip connection part 303. The current that has flowed into the chip connection unit 303 is supplied to the peripheral region 102 of the imaging chip 100 via the vias that connect the chip connection unit 303 and the wiring layer 202, the wiring layer 202, and the bonding wires 110. Specifically, the current that flows into the chip connection unit 303 is supplied to a processing circuit provided in the peripheral region 102, and the processing circuit is driven by the current supplied through the chip connection unit 303. The processing circuit will be described later. A return current supplied to the peripheral region 102 and returning from the peripheral region 102 flows into the chip connection unit 403 through a via connecting the wiring layer 202 and the chip connection unit 303.

  The current that flows into the chip connection unit 403 flows out from the y-axis plus side of the chip connection unit 403 and flows into the y-axis minus side of the current flow unit 401. The current that has flowed into the current flow portion 401 flows through the current flow portion 401 in the y-axis plus direction, flows out from the y-axis plus side of the current flow portion 401, and flows into the power supply connection portion 402. The current that has flowed into the power supply connection portion 402 flows into the second terminal 282 through a via that connects the power supply connection portion 402 and the second terminal 282.

  As shown in FIGS. 3, 4 and 5, the current flow portion 401 is provided along the current flow portion 301, and the current flow portion 301 and the current flow portion 401 are provided substantially in parallel. Yes. The current conducting part 401 is provided so that at least a part of the surface of the current conducting part 401 faces at least a part of the power supply pattern. Specifically, when the current flow unit 401 and the current flow unit 301 are projected on the xy plane, the region occupied by the current flow unit 401 in the xy plane and the region occupied by the current flow unit 301 in the xy plane are: At least partly overlaps. The region where the current conduction part 401 and the current conduction part 301 overlap when projected onto the xy plane is the y-axis plus side of at least one of the current conduction part 301 and the current conduction part 401, the current conduction part 301 and A region extending between at least one y-axis minus side of the current flow part 401 is formed. In addition, when the current flow unit 401, the current flow unit 301, and the imaging region 101 are projected on the xy plane, a part of the region occupied by the current flow unit 401 and a part of the region occupied by the current flow unit 301 And a part of the area occupied by the imaging area 101 overlap each other.

  Thus, the current flow part 301 and the current flow part 401 are in a positional relationship that overlaps when at least a part is projected onto the xy plane. And the current flow part 301 and the current flow part 401 are extended in parallel. The direction in which the current flows through the current flow unit 401 is opposite to the direction in which the current flows through the current flow unit 301. The magnitude of the current flowing through the current flow unit 301 is the current flowing through the current flow unit 401. Substantially equal to size. Therefore, the current flow unit 301 and the power supply connection unit 302 have a pattern configuration that provides a pair of balanced differential lines. Further, the current conducting part 301 and the current conducting part 401 are provided in the adjacent wiring layers. Therefore, the current flow unit 301 and the current flow unit 401 provide a pair of balanced differential lines that are tightly coupled. Therefore, it is possible to suppress the influence of the electromagnetic field generated by the current flowing through the current flow portion 301 and the current flowing through the current flow portion 401 on the imaging chip 100.

  Specifically, concentric lines of magnetic force are generated from each of the current flow part 301 and the current flow part 401 in a plane parallel to the xz plane. However, as described above, a pair of balanced differential lines is provided by the current flow unit 301 and the current flow unit 401, and therefore, concentric magnetic fields generated by the current flow unit 301 and the current flow unit 401, respectively. Works in the direction to counteract. That is, the magnetic field generated by the current flowing through the current flow unit 301 is strongly canceled by the magnetic field generated by the current flowing through the current flow unit 401.

  Further, as described above, the current supplied by the power supply pattern 300 varies greatly with time. Here, in general, a fringe electric field in which electric lines of force freely dissipate is formed from a line provided independently. However, since the current conducting part 301 and the current conducting part 401 provide a pair of balanced differential lines in which the current conducting part 301 and the current conducting part 401 are tightly coupled, the electric field lines dissipated from each of the current conducting parts 301 and 401 act as coupled. It does not propagate beyond the vicinity of the flow part 301 and the current flow part 401. Although the stray fringe field can reach relatively far, its electromagnetic field energy is very small. Further, since the wiring layer 204 has a solid ground pattern, it is possible to suppress the floating fringe electric field from reaching the imaging chip 100. Therefore, for example, the electromagnetic field energy transmitted to the imaging chip 100 can be remarkably reduced as compared with the case where the current conducting portion 301 and the current conducting portion 401 are each provided as a single line or a single solid pattern. Therefore, for example, noise superimposed on the pixel signal of the imaging chip 100 can be reduced.

  The current flow unit 301 is an example of a wiring that is provided on the mounting substrate 120 and flows a current supplied from the power source to the imaging chip 100 in the first direction. In addition, the current flow unit 401 is provided on the mounting substrate 120 along the current flow unit 301, and the current supplied to the imaging chip 100 through the current flow unit 301 and returning from the imaging chip 100 to the power source is the first current flow. It is an example of wiring that flows in a second direction substantially opposite to the direction.

  Note that the current supplied from the power supply pattern 310 to the wiring layer 202 via the via is supplied to the imaging chip 100 via the bonding wire 110, and the return current from the imaging chip 100 is grounded via the bonding wire 110. The data is output to the wiring layer 202 to which the pattern 480 is connected. The return current output to the wiring layer 202 is returned to the ground pattern 480 through the via. Similarly, currents supplied to the imaging chip 100 from the power supply pattern 320, the power supply pattern 330, the power supply pattern 340, the power supply pattern 350, and the power supply pattern 360 are also returned to the ground pattern 480.

  The ground pattern 480 is a pattern formed in a planar shape, and does not have a pattern configuration that provides a specific line. Further, the power supply pattern 320 and the power supply pattern 350 are also formed in a planar shape and do not substantially provide a unidirectional current path. The power supply pattern 310, the power supply pattern 330, and the power supply pattern 340 are not formed in a planar shape, but do not substantially provide a one-way current path.

  However, the magnitude of the instantaneous value of the current supplied to the imaging chip 100 from the power supply pattern 310, the power supply pattern 320, the power supply pattern 330, the power supply pattern 340, the power supply pattern 350, and the power supply pattern 360 is from the power supply pattern 300 to the imaging chip 100. Compared to the magnitude of the instantaneous value of the supplied current, the temporal change rate is also small. Accordingly, the energy of the electromagnetic field generated by the current flowing through the power supply pattern 310, the power supply pattern 320, the power supply pattern 330, the power supply pattern 340, the power supply pattern 350 and the power supply pattern 360 and the current flowing through the ground pattern 480 and transmitted to the imaging chip 100 is Relatively small. Therefore, the noise superimposed on the pixel signal and the like of the imaging chip 100 by the power supply current from these power supply patterns is relatively small.

  A capacitor 182 is electrically connected between the current flow unit 301 and the current flow unit 401. Specifically, the capacitor 182 electrically connects between the current flow unit 301 and the current flow unit 401 in the vicinity of the y-axis negative side end portions of the current flow unit 301 and the current flow unit 401. To do. More specifically, one terminal of the capacitor 182 is electrically connected to the current flow portion 301 via a via in the vicinity of the boundary between the current flow portion 301 and the chip connection portion 303. The other terminal of the capacitor 182 is electrically connected to the current flow portion 401 via a via in the vicinity of the boundary between the current flow portion 401 and the chip connection portion 403.

  The capacitor 182 accumulates electric charges supplied from the power supply via the connector 181. When the processing circuit unit 540 in the peripheral region 102 starts to operate, charge can be quickly supplied from the capacitor 182 to the processing circuit unit 540. Immediately after the processing circuit unit 540 in the peripheral region 102 starts its operation, most of the current supplied to the processing circuit unit 540 is supplied by discharging the capacitor 182. The electric charge corresponding to the discharge of the capacitor 182 is gradually replenished to the capacitor 182 by the current supplied from the connector 181.

  Thus, according to the imaging unit 40, since the capacitor 182 is provided in the vicinity of the chip connection unit 303 and the chip connection unit 403, a path through which a large current flows can be shortened. Therefore, noise superimposed on the pixel signal or the like of the imaging chip 100 can be suppressed.

  FIG. 7 is a diagram schematically illustrating a configuration of a circuit block formed in the imaging chip 100. As illustrated in FIG. A pixel unit 500 is formed in the imaging region 101 of the imaging chip 100. A peripheral circuit portion 570 is formed in the peripheral region 102. The peripheral circuit unit 570 includes a processing circuit unit 540, a drive signal generation unit 560, a scanning circuit unit 580a, a scanning circuit unit 580b, and an output circuit unit 590.

  The pixel unit 500 includes N × M unit cells 501. The unit cells 501 are two-dimensionally arranged in the xy plane. For example, the unit cells 501 are arranged in a matrix in the xy plane. Each of the unit cells 501 is provided at a position corresponding to one corresponding column from one column to M columns in one corresponding row from one row to N rows. Each of the unit cells 501 includes a photoelectric conversion element and a circuit such as a transistor that performs a reset operation or a read operation of accumulated charge accumulated in the photoelectric conversion element. An imaging unit is formed by a photoelectric conversion region formed by N × M unit cells 501.

  The scanning circuit portion 580a and the scanning circuit portion 580b perform readout scanning of the pixel portion 500. The scanning circuit unit 580b drives the unit cell 501 and the processing circuit unit 540, and outputs a signal obtained by photoelectric conversion of the photoelectric conversion element included in the unit cell 501. The unit cell 501 outputs an analog pixel signal indicating the amount of light received by the unit cell 501.

  The processing circuit unit 540 performs signal processing on the signal output from the unit cell 501 in accordance with the control of the scanning circuit unit 580a. The processing circuit unit 540 includes a conversion circuit 550 including a comparator 551 and a counter 552. The conversion circuit 550 is responsible for CDS and AD conversion processing. The processing circuit unit 540 performs so-called digital CDS. The output circuit unit 590 outputs the pixel signal of the digital signal obtained by the processing circuit unit 540 to the mounting substrate 120.

  Specifically, the scanning circuit portion 580b is electrically connected to the plurality of unit cells 501 via the row reset line 510-1 to the row reset line 510-N. The scanning circuit unit 580b is electrically connected to the plurality of unit cells 501 through the row selection line 520-1 to the row selection line 520-N. The scanning circuit unit 580b includes a shift register and the like.

  Processing circuit unit 540 includes comparators 551-1 to 551 -M and counters 552-1 to 552 -M. The analog signals output from the unit cells 501 are input to the comparators 551-1 to 551 -M through the vertical signal lines 530-1 to 530 -M. In addition, a ramp voltage as a reference voltage is input to the comparators 551-1 to 551 -M.

  Each of the unit cells 501 is connected to the row reset line 510 of the row corresponding to each unit cell 501 among the row reset lines 510-1 to 510-N. Each of the unit cells 501 is connected to the row selection line 520 of the row corresponding to each unit cell 501 among the row selection lines 520-1 to 520-N. Each of the unit cells 501 is connected to the vertical signal line 530 of the column corresponding to each unit cell 501 among the vertical signal lines 530-1 to 530-M.

  The row reset line 510-1 to the row reset line 510-N and the row selection line 520-1 to the row selection line 520-N send a signal for controlling reading of the unit cell 501 to the unit cell 501 provided in the corresponding row. Transmit to. The row reset line 510-1 to the row reset line 510-N transmit a reset signal generated by the shift register included in the scanning circuit unit 580b to the unit cells 501 provided in the corresponding row. The unit cell 501 resets the accumulated charge of the photoelectric conversion element included in the unit cell 501 in response to the reset signal. The unit cell 501 outputs the output signal of the photoelectric conversion element in a state where the accumulated charge is reset to the row selection line 520. This output signal is an analog signal indicating a reset level.

  The row selection lines 520-1 to 520 -N transmit row selection signals generated by the shift register included in the scanning circuit unit 580 to the unit cells 501 provided in the corresponding rows. The unit cell 501 outputs the output signal of the photoelectric conversion element included in the unit cell 501 to the vertical signal line 530 in accordance with the row selection signal. This output signal is an analog signal indicating the signal level of the pixel signal. The vertical signal line 530 transmits the output signal to the processing circuit unit 540 along the y-axis direction.

  The drive signal generation unit 560 is a timing generation circuit that controls the operation timing of each circuit such as the scanning circuit unit 580a, the scanning circuit unit 580b, the processing circuit unit 540, and the output circuit unit 590, and a reference voltage output to the conversion circuit 550. Including a reference signal generation circuit for generating the ramp voltage of the reference.

  The comparator 551 compares the voltage level of the ramp voltage input from the drive signal generator 560 to the comparator 551 with the voltage level of the output signal from the unit cell 501 in the corresponding column, and compares the comparison result with the corresponding counter. It outputs to 552. While the comparator 551 compares the voltage level of the lamp voltage with the reset level, the counter 552 is decreased until a comparison result indicating that the voltage level of the lamp voltage of the unit cell 501 matches the reset level is input. Count. Further, the counter 552 compares the voltage level of the ramp voltage with the signal level of the unit cell 501 while the comparator 551 is comparing the voltage level of the ramp voltage until a comparison result indicating that the voltage level of the ramp voltage matches the signal level is input. , Do an up-count. The count value obtained by the counter 552 corresponds to the digital value of the pixel signal.

  Thereby, the conversion circuit 550 generates a digital pixel signal obtained by removing the influence of the reset level from the input signal level. In this way, the conversion circuit 550 can generate a digital pixel signal with reduced noise such as fixed pattern noise. The digital pixel signal generated by the conversion circuit 550 is input to the output circuit unit 590 and output to the mounting substrate 120 via the bonding wire 110.

  Here, the current flow unit 301 and the current flow unit 401 are located below the pixel unit 500 included in the imaging chip 100. Specifically, when the current flow unit 301 and the pixel unit 500 are projected on the xy plane, at least a part of the current flow unit 301 overlaps a part of the pixel unit 500. Further, when the current conducting part 401 is projected on the xy plane, at least a part of the current conducting part 401 overlaps with a part of the pixel part 500. The current supplied via the power supply pattern 300 is supplied to the counter 552 of the conversion circuit 550. On the other hand, the current supplied through the power supply pattern 310, the power supply pattern 320, the power supply pattern 330, the power supply pattern 340, the power supply pattern 350, and the power supply pattern 360 is a circuit other than the counter 552 among the circuits formed in the peripheral region 102. It is supplied to the circuit and the pixel portion 500.

  The counter 552 instantaneously requires a relatively large current during the counting operation. The counter 552 repeatedly performs a counting operation and a non-operation. A relatively large current is intermittently and periodically supplied to the counter 552. Therefore, a large electromagnetic field may be generated due to the current supplied to the counter 552. In particular, in order to increase the number of pixels in the imaging chip or to enable high-speed reading in moving image shooting, it is necessary to increase the pixel signal reading speed. In order to increase the reading speed, for example, the driving cycle of the counter 552 is shortened. As a result, the supply cycle of the power supply current supplied to the counter 552 is shortened, and a large electromagnetic field may be generated.

  Generally, when the current supply cycle is shortened, electromagnetic radiation generated by the current increases. When electromagnetic field radiation increases, the operation of electronic components such as an imaging chip may be affected. For example, in an imaging unit, large noise may be mixed into a pixel signal generated by an imaging chip. For example, when a power supply pattern that crosses the substrate along the y-axis is formed below the imaging chip, noise is superimposed on the pixel signal due to an electromagnetic field generated from the power supply pattern at the time of reading, and an image including a fixed pattern of vertical stripes May be generated.

  On the other hand, according to the imaging unit 40, as described above, since the power supply pattern 300 and the ground pattern 400 provide a pair of balanced differential lines, the electromagnetic field radiation caused by the current supplied to the counter 552 is suppressed. it can. Therefore, the influence on the operation of the imaging chip 100 can be suppressed. For example, noise superimposed on the pixel signal generated by the imaging chip 100 can be suppressed by electromagnetic field radiation generated by the current supplied to the counter 552.

  Further, as described above, the capacitor 182 is electrically connected in the vicinity of the chip connection portion 303 and the chip connection portion 403. The change in current when the counter 552 switches between the operating state and the non-operating state is absorbed by the capacitor 182. Therefore, in the power supply pattern 300 and the ground pattern 400, the current path through which a large current flows to the counter 552 that is driven at high speed is substantially limited to the chip connection unit 303 and the chip connection unit 403. In particular, an abrupt current change when the operation state of the counter 552 is switched mainly appears in the chip connection unit 303 and the chip connection unit 403.

  Here, the influence of the current flowing along the y-axis is likely to appear in the pixel signal via the vertical signal line 530 arranged along the y-axis. In the imaging unit 40, as shown in FIG. 5, since the chip connection portion 303 and the chip connection portion 403 as a whole extend in the x-axis direction, the y-axis is between the capacitor 182 and the wiring layer 202. There is substantially no current path along. Therefore, according to the imaging unit 40, it is possible to suppress noise from being superimposed on the pixel signal via the vertical signal line 530 due to the influence of the current supplied to the counter 552. The chip connection unit 303 and the chip connection unit 403 are provided substantially in parallel with the surface on which the imaging chip 100 is provided on the mounting substrate 120, and the current supplied from the capacitor 182 to the imaging chip 100 is supplied to the vertical signal line 530 as a pixel signal. It is an example of the wiring which flows in the direction substantially orthogonal to the direction which transmits. Specifically, the chip connection unit 303 is located between the current flow unit 301 and the imaging chip 100 in the current path between the current flow unit 301 and the imaging chip 100, and from the capacitor 182 to the imaging chip 100. Is supplied in a direction substantially perpendicular to the transmission direction in which the vertical signal line 530 transmits the pixel signal. Further, the chip connection unit 403 is located between the chip connection unit 403 and the imaging chip 100 in the current path between the chip connection unit 403 and the imaging chip 100, and is supplied from the capacitor 182 to the imaging chip 100 and is captured by the imaging chip. The current returning from 100 is passed in a direction substantially perpendicular to the transmission direction in which the vertical signal line 530 transmits the pixel signal.

  In addition, if a board sufficiently wider than the imaging chip is used as a mounting board for the imaging chip or a board for mounting the imaging chip itself, a board in which a connector is arranged outside the imaging chip or a power supply pattern is constructed outside the imaging chip. Design becomes possible. And especially about the power supply pattern through which a large power supply flows, if the shape is a solid pattern, there is a possibility that the influence of electromagnetic radiation from the power supply pattern can be made relatively small. However, in order to apply this substrate design, a large-area substrate is required. Therefore, when this board design is applied, it is difficult to miniaturize the camera. Further, since electronic components such as connectors cannot be arranged in the vicinity of the imaging chip 100, it is not easy to reduce the number of electronic components. Moreover, it is not easy to reduce the weight of the imaging unit. In addition, the degree of freedom in board design is reduced.

  On the other hand, according to the imaging unit 40, even if the connector 181 and the power supply pattern 300 are provided at a position below the imaging chip 100, the influence of noise on the imaging chip 100 can be suppressed. Therefore, it is possible to suppress the deterioration of the imaging performance while downsizing the mounting board 120. Moreover, it becomes easy to reduce the number of electronic components. Moreover, it becomes easy to reduce the weight of the imaging unit. Moreover, the freedom degree of a board | substrate design can be raised. Moreover, since the electromagnetic wave radiated | emitted outside can be suppressed, it can become a countermeasure to the electromagnetic radiation (EMI) in electromagnetic compatibility (EMC). As described above, according to the imaging unit 40, the influence of the current flowing through the power supply pattern 300 and the ground pattern 400 on the imaging chip 100 and the outside of the imaging unit 40 can be suppressed.

  As shown in FIG. 6, the first terminal 281 connected to the power supply pattern 300 and the second terminal 282 connected to the ground pattern 400 are adjacent to each other. As described above, when the terminals in the vicinity of the connector 181 are assigned as the power supply side terminals and the ground side terminals, it is easy to realize a wiring pattern that cancels electromagnetic waves and the like.

  It is more desirable that the current path from the output from the connector 181 to the return to the connector 181 is short. Therefore, for example, it is desirable to use the nearest terminal among the terminals included in the connector 181 as a power supply side terminal for supplying current to the counter 552. In the imaging unit 40, since the conversion circuit 550 is provided on the negative side of the y-axis of the peripheral region 102, the n−1 terminal 283 is used as a power supply side terminal for supplying current to the counter 552, and the current to the counter 552 is The nth terminal 284 may be used as a ground side terminal for supply.

  Note that when the first conversion circuit similar to the conversion circuit 550 is provided on the y axis minus side of the peripheral region 102 and the second conversion circuit similar to the conversion circuit 550 is provided on the y axis plus side, the first conversion circuit The first terminal 281 is used as the power supply side terminal for the circuit, the second terminal 282 is used as the ground side terminal for the first conversion circuit, and the n−1th terminal 283 is used as the power supply side terminal for the second conversion circuit. It is desirable to use the nth terminal 284 as the ground side terminal for the second conversion circuit. In this way, the same kind of circuits are provided at different positions, the power supply current supplied to one circuit is supplied from the first terminal pair of the connector, and the power supply current supplied to the other circuit is supplied to the connector. When supplying from the second terminal pair, the first terminal pair is positioned closer to one circuit than the second terminal pair, and the second terminal pair is from the first terminal pair, It is desirable to be located on the side close to the other circuit.

  In the imaging unit 40 described above, the power supply pattern 300 may be provided in the wiring layer 214 and the ground pattern 400 may be provided in the wiring layer 216. Note that one of the power supply pattern 300 and the ground pattern 400 may be provided in the wiring layer 212, and the other of the power supply pattern 300 and the ground pattern 400 may be provided in the wiring layer 214. From the viewpoint of suppressing noise superimposed on the imaging chip 100, it is desirable that the power supply pattern 300 and the ground pattern 400 are located farther from the imaging chip 100. For example, the power supply pattern 300 and the ground pattern 400 are desirably located on the negative side of the z axis from the core layer 209. Note that it is desirable to have a solid ground pattern like the ground pattern 490 between the power supply pattern 300 and the ground pattern 400 and the imaging chip 100. However, the wiring layer 204 may not have the solid ground pattern 490. The ground pattern 490 is provided on the mounting substrate 120 and is located between the current flow unit 301 and the current flow unit 401 and the imaging chip 100, and the current flow unit 301 and the current with respect to the imaging chip 100. It is an example of a flat conductor having a ground potential that covers a flow passage portion 401.

  FIG. 8 is a cross-sectional view schematically showing the imaging unit 2040 according to the second embodiment. FIG. 8 is a cross-sectional view of the imaging unit 2040 corresponding to FIG.

  The imaging unit 2040 includes a core layer 2209 made of metal instead of the core layer 209 included in the imaging unit 40. The imaging unit 2040 further includes an insulating layer 2207 and an insulating layer 2217 in addition to the components included in the imaging unit 40. Note that among the constituent elements of the imaging unit 2040, constituent elements having the same reference numerals as those described in relation to the imaging unit 40 have the same configuration. Therefore, description of the components may be omitted.

  As a material of the core layer 2209, for example, an alloy of nickel and iron (for example, 42 alloy, 56 alloy), copper, aluminum, or the like may be used. The core layer 2209 is sandwiched between the insulating layer 2207 and the insulating layer 2217 in the z-axis direction. An insulating layer 2207 that contacts the wiring layer 206 and the core layer 2209 is disposed between the wiring layer 206 and the core layer 2209, and an insulating layer 2217 that contacts the core layer 2209 between the core layer 2209 and the wiring layer 216. Is arranged. The insulating layer 2207 and the insulating layer 2217 are formed using the same material as the material for forming the insulating layer 203, the insulating layer 205, the insulating layer 215, and the insulating layer 213.

  The core layer 2209 is electrically connected to a ground pattern such as the ground pattern 480 through a via. According to the imaging unit 2040, the power supply pattern 300 and the ground pattern 400 are provided on the negative side of the z-axis from the core layer 2209. Therefore, it is possible to suppress the floating fringe electric field from reaching the imaging chip 100. Thus, according to the imaging unit 2040, the electromagnetic wave generated in the power supply pattern 300 and the ground pattern 400 can be shielded by the core layer 2209. Therefore, the influence of the current flowing through the power supply pattern 300 and the ground pattern 400 on the outside of the imaging chip 100 and the imaging unit 40 can be suppressed.

  The core layer 2209 is provided on the mounting substrate 120, and is positioned between the current flow unit 301 and the current flow unit 401 and the imaging chip 100, and the current flow unit 301 and the current flow with respect to the imaging chip 100. 4 is an example of a flat conductor having a ground potential that covers the portion 401. Note that in the imaging unit 2040, the wiring layer 204 may not have the solid ground pattern 490. Since the core layer 2209 is formed of metal, even if the wiring layer 204 does not have the solid ground pattern 490, the current flowing through the power supply pattern 300 and the ground pattern 400 is external to the imaging chip 100 and the imaging unit 40. The influence which it has on can be suppressed.

  FIG. 9 is a cross-sectional view schematically showing an imaging unit 3040 according to the third embodiment. FIG. 9 is a cross-sectional view of the imaging unit 3040 corresponding to FIG.

  The imaging unit 3040 includes a power pattern 3300 and a ground pattern 3400 instead of the power pattern 300 and the ground pattern 400 included in the imaging unit 40. Note that, among the components included in the imaging unit 3040, components having the same reference numerals as those described in relation to the imaging unit 40 have the same configuration. Therefore, description of the components may be omitted. In addition, among the components included in the imaging unit 3040, the components corresponding to the components described in relation to the imaging unit 40 have the same configuration as the corresponding components included in the imaging unit 40, and thus description thereof is omitted. There is a case.

  The imaging unit 3040 includes a power pattern 3310, a power pattern 3320, a power pattern 3330, a power pattern 3340, and a power pattern 3350 in the wiring layer 216 as power patterns other than the power pattern 3300. These power supply patterns correspond to the power supply pattern 310, the power supply pattern 320, the power supply pattern 330, the power supply pattern 340, the power supply pattern 350, and the power supply pattern 360, which are power supply patterns other than the power supply pattern 300 in the imaging unit 40. Further, the imaging unit 3040 has a ground pattern 3480 in the wiring layer 214 as a ground pattern corresponding to the ground pattern 480.

  The power supply pattern 3300 and the ground pattern 3400 are provided on the wiring layer 212 of the mounting substrate 120. The ground pattern 3400 is provided substantially parallel to the power supply pattern 300. The ground pattern 3400 is provided along the power supply pattern 3300. Specifically, both the power supply pattern 3300 and the ground pattern 3400 extend in a direction parallel to the y-axis. The power supply pattern 3300 is an example of wiring formed in one wiring layer of the mounting substrate 120. The ground pattern 3400 is an example of a wiring that is formed in a wiring layer in which the power supply pattern 3300 is formed and is located in the vicinity of the power supply pattern 3300.

  The ground pattern 3480 is a solid ground pattern provided as the wiring layer 214. The power supply pattern 3300 and the ground pattern 3400 are provided on the surface layer of the mounting substrate 120 on the second main surface 112 side. The power supply pattern 3300, the ground pattern 3400, and the ground pattern 3480 have a so-called microstrip line structure. According to this line structure, the ground pattern 3480 has a function of coupling electric lines of force generated in the z-axis plus direction. Therefore, many lines of electric force generated from the power supply pattern 3300 and the ground pattern 3400 can be captured.

  Thus, the power supply pattern 3300 and the ground pattern 3400 provide a pair of balanced differential lines. Therefore, the influence of the current flowing through the power supply pattern 3300 and the ground pattern 3400 on the outside of the imaging chip 100 and the imaging unit 40 can be suppressed.

  From the viewpoint of suppressing noise superimposed on the imaging chip 100, it is desirable that the power supply pattern 3300 and the ground pattern 3400 are located farther from the imaging chip 100. However, the power supply pattern 3300 and the ground pattern 3400 may be provided in the inner layer of the mounting substrate 120. For example, the power supply pattern 3300 and the ground pattern 3400 may be provided in any one of the wiring layer 214, the wiring layer 216, and the wiring layer 206. In this case, a solid ground pattern may be provided in the wiring layer on the z-axis plus side from the wiring layer provided with the power supply pattern 3300 and the ground pattern 3400.

  Further, similarly to the imaging unit 2040, the core layer 209 may be formed of metal. In this case, it is desirable to provide the power supply pattern 3300 and the ground pattern 3400 in the wiring layer on the negative side of the z axis from the core layer 209. Specifically, the power supply pattern 3300 and the ground pattern 3400 are preferably provided in any one of the wiring layer 212, the wiring layer 214, and the wiring layer 216.

  FIG. 10 is a cross-sectional view schematically showing an imaging unit 4040 according to the fourth embodiment. FIG. 10 is a cross-sectional view of the imaging unit 4040 corresponding to FIG.

  The imaging unit 4040 further includes a guard pattern 4500a and a guard pattern 4500b in the wiring layer 212 in addition to the components included in the imaging unit 3040. Note that among the constituent elements of the imaging unit 4040, constituent elements having the same reference numerals as those described in relation to the imaging unit 3040 have the same configuration. Therefore, description of the components may be omitted. In addition, among the components included in the imaging unit 4040, the components corresponding to the components described in relation to the imaging unit 3040 have the same configuration as the corresponding components included in the imaging unit 3040, and thus description thereof is omitted. There is a case.

  The guard pattern 4500a, the guard pattern 4500b, the power supply pattern 3300, and the ground pattern 3400 are provided in the same wiring layer. Guard pattern 4500a is electrically connected to ground pattern 3480 through via 4131a. Guard pattern 4500b is electrically connected to ground pattern 3480 through via 4131b.

  The guard pattern 4500a is an example of a ground potential wiring formed along the power supply pattern 3300 and the ground pattern 3400 in the wiring layer in which the power supply pattern 3300 and the ground pattern 3400 are formed. The guard pattern 4500b is an example of a ground potential wiring formed along the power supply pattern 3300 and the ground pattern 3400 in the wiring layer in which the power supply pattern 3300 and the ground pattern 3400 are formed. The power supply pattern 3300 is located between the guard pattern 4500a and the ground pattern 3400. The ground pattern 3400 is located between the guard pattern 4500b and the power supply pattern 3300.

  In this way, by providing the ground potential guard pattern 4500a and the guard pattern 4500b extending along the power supply pattern 3300 and the ground pattern 3400 on both sides of the power supply pattern 3300 and the ground pattern 3400, the shielding effect of electromagnetic waves is further enhanced. be able to. In this configuration, since the power supply pattern 3300 and the ground pattern 3400 are not surrounded by the ground potential, it is possible to suppress the deterioration of the frequency characteristics of the power supply system.

  Note that the guard pattern 4500a and the guard pattern 4500b are preferably connected to the ground pattern 3480 by providing a plurality of vias at regular intervals. It is desirable to provide more vias that connect the guard pattern 4500a and the guard pattern 4500b to the ground pattern 3480. In addition, the interval between vias connecting the guard pattern 4500a and the guard pattern 4500b and the ground pattern 3480 is preferably less than a quarter wavelength of the frequency of the current flowing through the power supply pattern 3300 and the ground pattern 3400.

  It is desirable that power supply pattern 3300 and ground pattern 3400a be more strongly coupled between power supply pattern 3300 and guard pattern 4500a. Further, it is desirable that the power supply pattern 3300 and the ground pattern 3400 are more strongly coupled between the ground pattern 3400 and the guard pattern 4500b. Specifically, when the interval between the power supply pattern 3300 and the ground pattern 3400 is S, it is desirable that the guard pattern 4500a be provided 2S or more away from the power supply pattern 3300. Similarly, it is desirable that the guard pattern 4500b be provided 2S or more away from the ground pattern 3400. As described above, the distance between the guard pattern 4500a and the power supply pattern 3300 is preferably larger than twice the distance between the power supply pattern 3300 and the ground pattern 3400. The distance between the guard pattern 4500b and the ground pattern 3400 is preferably greater than twice the distance between the power supply pattern 3300 and the ground pattern 3400.

  In addition, when the width of the power supply pattern 3300 is W, the guard pattern 4500a is desirably provided 2 W or more away from the power supply pattern 3300. Similarly, the guard pattern 4500b is desirably provided at a distance of 2 W or more from the ground pattern 3400. Further, it is desirable that S <W. The width of the power supply pattern 3300 is a length in a direction orthogonal to the direction in which the power supply pattern 3300 extends. That is, the width of the power supply pattern 3300 is the length in the x-axis direction. Similarly, the width of the ground pattern 3400 is the length of the ground pattern 3400 in the x-axis direction.

  FIG. 11 is a cross-sectional view schematically showing an imaging unit 5040 according to the fifth embodiment. FIG. 11 is a cross-sectional view of the imaging unit 5040 corresponding to FIG.

  The imaging unit 5040 includes a power supply pattern 5300 instead of the power supply pattern 3300 included in the imaging unit 3040. The imaging unit 5040 includes a ground pattern 5400 instead of the ground pattern 3400 included in the imaging unit 3040. Further, the imaging unit 5040 includes a core layer 5209 formed of metal instead of the core layer 209 included in the imaging unit 3040. The imaging unit 5040 further includes an insulating layer 5207 and an insulating layer 5217 in addition to the components included in the imaging unit 3040. Note that among the constituent elements of the imaging unit 5040, constituent elements having the same reference numerals as those described in relation to the imaging unit 3040 have the same configuration. Therefore, description of the components may be omitted.

  The power supply pattern 5300 is a power supply pattern corresponding to the power supply pattern 3300. The ground pattern 5400 is a ground pattern corresponding to the ground pattern 3400. The imaging unit 5040 includes a power pattern 5310, a power pattern 5320, a power pattern 5330, a power pattern 5340, and a power pattern 5350 in the wiring layer 216 as power patterns other than the power pattern 5300. These power supply patterns are power supply patterns corresponding to the power supply pattern 3310, the power supply pattern 3320, the power supply pattern 3330, the power supply pattern 3340, and the power supply pattern 3350 which are power supply patterns other than the power supply pattern 3300 in the imaging unit 3040. The core layer 5209 corresponds to the core layer 2209 in the imaging unit 2040. The insulating layer 5207 corresponds to the insulating layer 2207 in the imaging unit 2040. The insulating layer 5217 corresponds to the insulating layer 2217 in the imaging unit 2040. Among the components included in the imaging unit 5040, the components corresponding to the components described in relation to the imaging unit 2040 or the imaging unit 3040 have the same configuration as the corresponding components included in the imaging unit 2040 or the imaging unit 3040. In some cases, the description is omitted.

  The power supply pattern 5300 and the ground pattern 5400 are provided in the inner layer of the mounting substrate 120. Specifically, the power supply pattern 5300 and the ground pattern 5400 are provided on the wiring layer 216 of the mounting substrate 120. As described above, the power supply pattern 5300 and the ground pattern 5400 are sandwiched between the core layer 5209 and the ground pattern 3480. The power supply pattern 5300 and the ground pattern 5400 are located between the core layer 2209 and the ground pattern 3480. The ground pattern 3480 is an example of a flat conductor with a ground potential that is provided on the mounting substrate 120 and covers the power supply pattern 5300 and the ground pattern 5400.

  The power supply pattern 5300, the ground pattern 5400, the ground pattern 3480, and the core layer 5209 have a so-called stripline structure. According to this structure, since the power supply pattern 5300 and the ground pattern 5400 are substantially shielded by the core layer 5209 and the ground pattern 3480, the electromagnetic wave shielding effect can be further enhanced. Since the capacitor 182 is connected to the power supply pattern 5300 and the ground pattern 5400 as in the other embodiments, the frequency response is reduced when the power supply pattern 5300 and the ground pattern 5400 are substantially shielded by the conductor. Can be suppressed.

  Note that the power supply pattern 5300 and the ground pattern 5400 may be provided in a wiring layer other than the wiring layer 216. For example, as long as the wiring layer is on the z-axis minus side from the core layer 5209, the power supply pattern 5300 and the ground pattern 5400 may be provided in any layer. Alternatively, a solid ground pattern may be provided in two wiring layers sandwiching the power supply pattern 5300 and the ground pattern 5400 without using the metal core layer 5209 so as to have a so-called stripline structure.

  In the imaging unit 3040, the imaging unit 4040, and the imaging unit 5040, the power supply pattern and the ground pattern are provided in the same wiring layer. However, the power supply pattern and the ground pattern may be provided in different wiring layers. For example, the power supply pattern may be provided on the wiring layer 216 and the ground pattern may be provided on the wiring layer 214. Thus, the ground pattern may be provided in the wiring layer adjacent to the wiring layer provided with the power supply pattern. If the wiring layer provided with the power supply pattern is close to the wiring layer provided with the ground pattern, a corresponding effect can be expected. Further, in order to shield electromagnetic waves and the like, it is desirable that each wiring layer is thicker.

  FIG. 12 is a bottom view schematically showing the mounting board 120 on which the flexible board 600 is mounted. In FIG. 12, as in FIG. 6, among the components included in the mounting substrate 120, illustration of electronic components other than the connector 181 and the capacitor 182, the wiring layer 212, and the like is omitted. FIG. 13 is a cross-sectional view schematically showing the imaging unit 40 with the flexible substrate 600 attached. 13 is a cross-sectional view of the imaging unit 40 and the flexible substrate 600 when cut along the CC cross section of FIG.

  The flexible substrate 600 is a flexible printed substrate, for example. The flexible board 600 of this embodiment is a single-sided flexible printed board. The flexible substrate 600 is attached to the connector 181. The flexible substrate 600 supplies a current supplied to the imaging chip 100. The flexible substrate 600 includes a power supply wiring 610, a ground wiring 620, and a signal line group 650 including a plurality of signal lines.

  The signal line group 650 may include a signal line that transmits the pixel signal from the imaging chip 100 transmitted to the connector 181 to the ASIC 52. Further, the signal line group 650 may include a signal line that transmits a control signal for controlling the imaging chip 100.

  The power supply wiring 610 flows a current supplied to the imaging chip 100 from a power supply external to the imaging unit 40. When the flexible substrate 600 is attached to the connector 181, the power supply wiring 610 causes a current supplied from the power supply to the imaging chip 100 to flow in the negative direction of the x axis. The power supply outside the imaging unit 40 is, for example, a power supply circuit included in the battery unit. The power supply wiring 610 is an example of a wiring that allows a current supplied from the power supply to the imaging chip 100 to flow in the third direction.

  A current flowing through the power supply wiring 610 is supplied to the mounting substrate 120 through the first terminal 281 of the connector 181. Specifically, as described above, the current flowing through the power supply wiring 610 flows into the power supply connection portion 302 included in the power supply pattern 300 through the first terminal 281 and vias.

  The ground wiring 620 flows a current that is supplied to the imaging chip 100 through the power wiring 610 and returns from the imaging chip 100 to the power source. Specifically, the current returning from the imaging chip 100 to the external power supply is supplied to the ground wiring 620. Specifically, as described above, the current returning from the imaging chip 100 to the external power supply is supplied to the ground wiring 620 through the second terminal 282 of the connector 181, flows through the ground wiring 620, and returns to the external power supply.

  The ground wiring 620 is provided along the power supply wiring 610 adjacent to the power supply wiring 610. Therefore, when the flexible substrate 600 is attached to the connector 181, the ground wiring 620 causes a current that is supplied to the imaging chip 100 through the power supply wiring 610 and returns from the imaging chip 100 to the power source to flow in the x-axis plus direction. The ground wiring 620 is an example of a wiring that supplies a current that is supplied to the imaging chip 100 through the power supply wiring 610 and returns from the imaging chip 100 to the power source in a fourth direction that is substantially opposite to the third direction.

  As shown in FIG. 13, the flexible substrate 600 has one wiring layer 670. In the wiring layer 670, a power supply wiring 610, a ground wiring 620, and a signal line group 650 are provided. As described above, the power supply wiring 610 and the ground wiring 620 are provided side by side in the same wiring layer 670 included in the flexible substrate 600.

  The power supply wiring 610 and the ground wiring 620 are extended side by side, and the direction in which the current flows through the power supply wiring 610 is opposite to the direction in which the current flows through the ground wiring 620. Substantially equal to the magnitude of the current flowing through 620. Therefore, the power supply wiring 610 and the ground wiring 620 have a pattern configuration that provides a pair of balanced differential lines. Further, since the power supply wiring 610 and the ground wiring 620 are adjacent to each other, the power supply wiring 610 and the ground wiring 620 provide a pair of balanced differential lines that are tightly coupled. Therefore, the electromagnetic field due to the current flowing through the ground wiring 620 and returning to the power supply acts in a direction to cancel the electromagnetic field due to the current flowing through the power wiring 610 and supplied to the imaging chip 100. That is, the electromagnetic field due to the current flowing through the power supply wiring 610 and supplied to the imaging chip 100 and the electromagnetic field due to the current flowing through the ground wiring 620 and returning to the power supply act in a mutually canceling direction. Therefore, it is possible to suppress the influence of the electromagnetic field generated by the current flowing through the power supply wiring 610 and the current flowing through the ground wiring 620 on the imaging chip 100.

  Thereby, even if the flexible substrate 600 is provided at a position below the imaging chip 100, the influence of noise on the imaging chip 100 can be suppressed. Therefore, it is possible to suppress the deterioration of the imaging performance while downsizing the mounting board 120. Moreover, it becomes easy to reduce the weight of the imaging unit. Moreover, the freedom degree of a board | substrate design can be raised. Moreover, since the electromagnetic wave radiated | emitted outside can be suppressed, it can become a countermeasure to the electromagnetic radiation (EMI) in electromagnetic compatibility (EMC). As described above, according to the flexible substrate 600, the electromagnetic field caused by the current flowing through the ground wiring 620 through the ground wiring 620 and returning to the power supply is at least the electromagnetic field caused by the current flowing through the power supply wiring 610 and supplied to the imaging chip 100. It is provided along the power supply wiring 610 so that one of the directions is canceled out. Therefore, the influence of the current flowing through the power supply wiring 610 and the ground wiring 620 on the outside of the imaging chip 100 and the imaging unit 40 can be suppressed.

  The direction of the current flowing through the power supply wiring 610 and the direction of the current flowing through the ground wiring 620 need not be completely opposite. The direction of the current flowing through the power supply wiring 610 and the direction of the current flowing through the ground wiring 620 may be approximately opposite to the extent that they substantially act in the direction of canceling out electromagnetic waves. Thereby, the effect similar to the effect acquired by comprising the current carrying part 301 mentioned above and the current carrying part 401 by comprising a closely-coupled differential pattern is acquired. Here, the influence of electromagnetic waves on the imaging chip 100 and the like has been mainly described, but the same applies to at least one of a magnetic field and an electric field. That is, the ground wiring 620 has a direction in which at least one of a magnetic field and an electric field due to a current flowing through the ground wiring 620 and returning to the power supply cancels at least one of a magnetic field and an electric field due to the current flowing through the power wiring 610 and supplied to the imaging chip 100. May be provided along the power supply wiring 610.

  As shown in FIG. 12, the width of the mounting substrate 120 in the x-axis direction is Ws. That is, the width of the mounting substrate 120 in the direction along the extending direction of the power supply wiring 610 is Ws. When the flexible substrate 600 is attached to the connector 181, the flexible substrate 600 is provided at a position facing the mounting substrate 120. The width of the mounting substrate 120 in the direction along the extending direction of the power supply wiring 610 in the region where the mounting substrate 120 is provided facing the flexible substrate 600 is represented by a width Wl. Here, Wl is less than half of Ws. For example, the position of the connector 181 is provided on the mounting substrate 120 such that Wl is equal to or less than half of Ws. Thus, the length of the portion where the mounting substrate 120 and the flexible substrate 600 overlap when projected onto the xy plane is less than or equal to half of Ws. Therefore, even if some electromagnetic waves leak from the flexible substrate 600, the influence of the electromagnetic waves on the imaging chip 100 can be suppressed.

  When the flexible substrate 600 is attached to the connector 181, the power supply wiring 610 and the ground wiring 620 are substantially orthogonal to the vertical signal line 530. Accordingly, even if some electromagnetic waves leak from the power supply wiring 610 and the ground wiring 620, it is possible to suppress noise from being superimposed on the pixel signal through the vertical signal line 530.

  Note that as the angle formed between the extending direction of the power supply wiring 610 and the ground wiring 620 and the extending direction of the vertical signal line 530 is closer to 90 °, noise can be suppressed from being superimposed on the pixel signal through the vertical signal line 530. Therefore, the angle formed by the extending direction of the power supply wiring 610 and the ground wiring 620 and the extending direction of the vertical signal line 530 is preferably close to 90 °. However, even when the power supply wiring 610 and the ground wiring 620 form a 45 ° angle with the vertical signal line 530, it is possible to suppress large noise from being superimposed on the pixel signal through the vertical signal line 530. Therefore, the power supply wiring 610 and the ground wiring 620 are provided in an orientation that forms an angle with the vertical signal line 530 in the range of 45 ° to 90 ° at least in a portion where the flexible substrate 600 is provided facing the mounting substrate 120. It's okay.

  Further, the power supply wiring 610 and the ground wiring 620 do not need to be orthogonal to the vertical signal line 530 in the non-facing region that is a portion other than the portion where the flexible substrate 600 is provided facing the mounting substrate 120. In the non-facing region, the angle formed between the extending direction of the power supply wiring 610 and the ground wiring 620 and the extending direction of the vertical signal line 530 may be less than 45 °.

  FIG. 14 is a cross-sectional view schematically showing the flexible substrate 700 and the imaging unit 40. FIG. 14 is a cross-sectional view corresponding to FIG. The flexible substrate 700 is a modification of the flexible substrate 600. The flexible board 700 is an example of a double-sided flexible printed board.

  The flexible substrate 700 has a wiring layer 770 and a ground layer 780. The wiring layer 770 and the ground layer 780 are insulated by an insulating layer. In the wiring layer 770, a power supply wiring 710, a ground wiring 720, and a signal line group 750 including a plurality of signal lines are provided.

  The wiring layer 770 corresponds to the wiring layer 670. The power supply wiring 710 corresponds to the power supply wiring 610, and the ground wiring 720 corresponds to the ground wiring 620. Among the components included in the flexible substrate 700, the components corresponding to the components described in relation to the flexible substrate 600 have the same configuration as the corresponding components included in the flexible substrate 600, and thus description thereof is omitted. There is a case.

  The ground layer 780 is a substantially solid pattern that covers at least the power supply wiring 610 and the ground wiring 620. The ground layer 780 is an example of a flat conductor having a ground potential. The ground layer 780 covers the power supply wiring 710, the ground wiring 720, and the signal line group 750. When the flexible substrate 700 is attached to the connector 181, the ground layer 780 is located between the wiring layer 770 and the mounting substrate 120.

  According to the flexible substrate 700, since the ground layer 780 is located between the wiring layer 770 and the mounting substrate 120, for example, a floating fringe electric field caused by a current flowing through the power supply wiring 710 and the ground wiring 720 reaches the imaging chip 100. It can be suppressed by the ground layer 780. As described above, according to the flexible substrate 700, the electromagnetic wave generated in the power supply wiring 710 and the ground wiring 720 can be shielded by the ground layer 780. Therefore, the influence of the current flowing through the power supply wiring 710 and the ground wiring 720 on the outside of the imaging chip 100 and the imaging unit 40 can be suppressed.

  FIG. 15 is a cross-sectional view schematically showing the flexible substrate 800 and the imaging unit 40. FIG. 15 is a cross-sectional view corresponding to FIG. The flexible substrate 800 is a further modification of the flexible substrate 600. The flexible substrate 800 is an example of a double-sided flexible printed substrate.

  The flexible substrate 800 includes a wiring layer 870 and a wiring layer 880. The wiring layer 870 and the wiring layer 880 are insulated by an insulating layer. The wiring layer 870 includes power supply wiring 810. The wiring layer 880 includes a ground wiring 820. The wiring layer 870 and the wiring layer 880 further include a signal line group 850 including a plurality of signal lines.

  The wiring layer 870 corresponds to the wiring layer 770. The power supply wiring 810 corresponds to the power supply wiring 610, and the ground wiring 820 corresponds to the ground wiring 620. Among the constituent elements of the flexible substrate 800, the constituent elements corresponding to the constituent elements described in relation to the flexible substrate 600 have the same configuration as the corresponding constituent elements of the flexible substrate 600. Explanation may be omitted.

  The wiring layer 880 is a wiring layer adjacent to the wiring layer 870. The power supply wiring 810 is provided so that at least a part of the surface of the power supply wiring 810 faces at least a part of the surface of the ground wiring 820. Specifically, when the power supply wiring 810 and the ground wiring 820 are projected onto the xy plane, at least a part of the region occupied by the power supply wiring 810 in the xy plane and the region occupied by the ground wiring 820 in the xy plane overlap. A region where the power supply wiring 810 and the ground wiring 820 overlap when projected onto the xy plane extends along the x-axis. Thus, the power supply wiring 810 and the ground wiring 820 extend substantially parallel to each other. Therefore, the flexible substrate 800 can also suppress the influence of the current flowing through the power supply wiring 810 and the ground wiring 820 on the imaging chip 100 and the outside of the imaging unit 40.

  FIG. 16 is a bottom view schematically showing the mounting substrate 6120 on which the flexible substrate 900 is mounted. FIG. 15 is a bottom view corresponding to FIG.

  The flexible substrate 900 is a further modification of the flexible substrate 600. The flexible substrate 800 is an example of a single-sided flexible printed substrate. An imaging chip 6100 is mounted on the mounting substrate 6120. The imaging chip 6100 is a modification of the imaging chip 100. The imaging chip 6100 includes an imaging region 6101 and a conversion circuit 6550a and a conversion circuit 6550b provided in the peripheral region. The imaging area 6101 corresponds to the imaging area 101. Similarly to the conversion circuit 550, the conversion circuit 6550a is provided in the peripheral region on the negative side of the y-axis in the imaging chip 6100. In the imaging chip 6100, a conversion circuit 6550b is provided in the peripheral region on the y-axis plus side.

  Among the components of the flexible substrate 900, the components corresponding to the components described in relation to the flexible substrate 600 have the same configuration as the corresponding components of the flexible substrate 600. Explanation may be omitted. The mounting substrate 120 is a mounting substrate for the imaging chip 6100 and has the same configuration as the mounting substrate 120 except that the mounting substrate 120 has a configuration for driving the imaging chip 6100.

  The flexible substrate 900 supplies a current supplied to the imaging chip 6100. The flexible substrate 900 includes a power supply wiring 910, a ground wiring 920, a signal line group 950 including a plurality of signal lines, a power supply wiring 930, and a ground wiring 940.

  The wiring pair of the power supply wiring 910 and the ground wiring 920 is a wiring pair located on the most positive side in the y-axis direction among the wiring pairs of the flexible substrate 900. The wiring pair of the power supply wiring 930 and the ground wiring 940 is a wiring pair located on the most negative side in the y-axis direction among the wiring pairs of the flexible substrate 900.

  The power supply wiring 910 corresponds to the power supply wiring 610. The ground wiring 920 corresponds to the ground wiring 620. The power supply wiring 910 flows current supplied to the imaging chip 6100 from an external power supply. The ground wiring 920 supplies a current that is supplied to the imaging chip 6100 through the power supply wiring 910 and returns from the imaging chip 6100 to the power source.

  In particular, the power supply wiring 910 flows a current supplied from an external power supply to the conversion circuit 6550b of the imaging chip 6100. Specifically, the current flowing through the power supply wiring 910 is supplied to the mounting board 6120 through the first terminal 281 of the connector 181 and is supplied to the conversion circuit 6550b through the mounting board 6120. The current returning from the conversion circuit 6550b to the external power supply is supplied to the ground wiring 920 through the second terminal 282 of the connector 181 and flows through the ground wiring 920 to return to the external power supply.

  The power supply wiring 930 is provided on the negative side of the y-axis and is different from the power supply wiring 910 in that a current supplied to the conversion circuit 6550a flows. The ground wiring 940 is provided on the negative side of the y-axis and is different from the ground wiring 920 in that a current returning from the conversion circuit 6550a to the power supply is passed. Specifically, the power supply wiring 930 flows current supplied from the external power supply to the conversion circuit 6550a. Specifically, the current flowing through the power supply wiring 930 is supplied to the mounting board 6120 through the (n-1) th terminal 283 of the connector 181 and is supplied to the conversion circuit 6550a through the mounting board 6120. The current returning from the conversion circuit 6550a to the external power supply is supplied to the ground wiring 940 through the n-th terminal 284 of the connector 181 and flows through the ground wiring 940 to return to the external power supply.

  Similar to the power supply wiring 610 and the ground wiring 620, the current flowing through the power supply wiring 910 and the current flowing through the ground wiring 920 act in a direction in which electromagnetic waves cancel each other. Further, the current flowing through the power supply wiring 930 and the current flowing through the ground wiring 940 also act in a direction in which electromagnetic waves cancel each other. Therefore, similarly to the flexible substrate 600, the influence of the current flowing through the power supply wiring 910, the ground wiring 920, the power supply wiring 930, and the ground wiring 940 on the imaging chip 6100 and the outside can be suppressed.

  Furthermore, according to the flexible substrate 900, the power supply wiring 910 and the ground wiring 920 are located closer to the conversion circuit 6550b than the other wirings included in the flexible substrate 900. The power supply wiring 930 and the ground wiring 940 are located closer to the conversion circuit 6550a than the other wirings included in the flexible substrate 900. Therefore, a path through which a large current flows in the mounting substrate 6120 can be shortened. Thereby, the influence which the electric current which flows through the mounting substrate 6120 exerts on the imaging chip 6100 and the outside can be further suppressed.

  Note that, as a modification of the flexible substrate 900, a double-sided flexible printed circuit board which at least one of the flexible circuit board 700 and the flexible circuit board 800 has can be applied. Further, any one of the flexible substrate 600, the flexible substrate 700, the flexible substrate 800, and the flexible substrate 900 described above can be applied to any of the imaging unit 2040, the imaging unit 3040, the imaging unit 4040, and the imaging unit 5040.

  In the above description, the power supply pattern and ground pattern for supplying current to the counter 552 have been mainly described. However, the counter 552 is an example of an electronic component to which a power supply current is supplied. For example, when the imaging chip 100 includes an analog CDS circuit that performs CDS processing on an analog pixel signal, the configuration of the power supply pattern and the ground pattern described above may be applied to the analog CDS circuit. Needless to say, the configurations of the power supply pattern and the ground pattern described above can be applied not only to the counter 552 and the analog CDS circuit but also to other electronic components.

  Note that flip-chip mounting may be applied as a method of mounting the imaging chip 100. Further, the mounting substrate of the imaging chip 100 is not limited to the core substrate, and various substrates can be applied as the mounting substrate. Further, the configuration of the power supply pattern and the ground pattern described above can also be applied to an imaging unit having a configuration in which the first substrate on which the imaging chip 100 is mounted is mounted on the second substrate on which an electronic component such as a connector is mounted.

  In the above, the camera 10 including the lens unit 20 and the camera body 30 has been described as an example of an imaging apparatus. However, the imaging device may not include the lens unit 20. For example, the camera body 30 is an example of an imaging device. The imaging device is a concept that includes a lens non-exchangeable imaging device in addition to a lens-exchangeable imaging device such as a single-lens reflex camera.

  The imaging unit is an example of an electronic unit. The configuration having the power supply pattern and the ground pattern described above can be applied to various electronic units other than the imaging unit. The imaging device is an example of an electronic device. The electronic device may include an electronic unit having the configuration of the power supply pattern and the ground pattern described above.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above embodiment. It is apparent from the description of the scope of claims that embodiments with such changes or improvements can be included in the technical scope of the present invention.

  The execution order of each process such as operation, procedure, step, and stage in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior to”. It should be noted that the output can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the specification, and the drawings, even if it is described using “first”, “next”, etc. for the sake of convenience, it means that it is essential to carry out in this order. It is not a thing.

10 Camera, 20 Lens unit, 22 Optical axis, 24 Lens side mount, 26 Body side mount, 30 Camera body, 31 Mirror unit, 32 Main mirror, 33 Sub mirror, 38 Shutter unit, 40 Imaging unit, 51 MPU, 52 ASIC, 60 mirror box, 62 substrate, 70 imaging optical system, 72 focus detection sensor, 80 focus plate, 82 penta prism, 84 finder optical system, 86 finder window, 88 display unit 100 imaging chip, 101 imaging area, 102 peripheral area, 110 Wire 111 First main surface, 112 Second main surface 120 Mounting substrate 121 First layer, 122 Second layer 131 Via 138 Opening 140 Frame 141 First surface, 142 Second surface, 143 Third surface, 144 Fourth Surface, 145 5th surface, 146 6th surface 147 Positioning 148 Mounting hole, 150 Bracket, 160 Cover glass 201, 211 Solder resist layer 202, 204, 206, 212, 214, 216 Wiring layer 203, 205, 213, 215 Insulating layer 209 Core layer 240 Bonding lead 181 Connector, 182 Capacitor , 183 Resistor, 184 Transistor 281 1st terminal, 282 2nd terminal, 283 n-1 terminal, 284 nth terminal 300, 310, 320, 330, 340, 350, 360 Power supply pattern 301 Current carrying part, 302 Power supply Connection part, 303 Chip connection part 400, 480, 490 Ground pattern 401 Current conduction part, 402 Power supply connection part, 403 Chip connection part 500 Pixel part, 501 Unit cell, 510 row reset line, 520 row selection line, 530 Vertical signal Line, 540 Processing circuit section 550 conversion circuit, 551 comparator, 552 counter, 560 drive signal generation unit, 570 peripheral circuit unit, 580 scanning circuit unit, 590 output circuit unit 2040, 3040, 4040, 5040 imaging unit 2207, 2217 insulating layer, 2209 core layer 3300, 3310, 3320, 3330, 3340, 3350 Power supply pattern 3400, 3480 Ground pattern 4131 Via, 4500 Guard pattern 5300, 5310, 5320, 5330, 5340, 5350 Power supply pattern 5400 Ground pattern 5207, 5217 Insulating layer, 5209 Core layer Power supply pattern

Claims (30)

A substrate,
Electronic components provided on the substrate;
A first wiring provided on the substrate and configured to flow a current supplied from a first power source to the electronic component in a first direction;
A current that is provided on the substrate along the first wiring, is supplied to the electronic component through the first wiring, and returns from the electronic component to the first power source in the first direction in the vicinity of the first wiring. And a second wiring that flows in a second direction substantially opposite to the electronic unit. A substrate,
Electronic components provided on the substrate;
A first wiring that is provided on the substrate and allows a current supplied from a first power source to the electronic component;
A second wiring that is provided on the substrate and is supplied to the electronic component through the first wiring and flows a current returning from the electronic component to the first power source;
In the second wiring, at least one of a magnetic field and an electric field due to a current flowing through the second wiring and returning to the first power source is a magnetic field and an electric field due to a current flowing through the first wiring and supplied to the electronic component. An electronic unit provided along the first wiring so as to be in a direction to cancel at least one. The first wiring is a power supply pattern formed in a first wiring layer of the substrate,
The electronic unit according to claim 1, wherein the second wiring is a ground pattern formed in a second wiring layer adjacent to the first wiring layer. The electronic unit according to claim 3, wherein the ground pattern is provided such that at least a part of the ground pattern faces at least a part of the power pattern. The first wiring is a power supply pattern formed in one wiring layer of the substrate,
3. The electronic unit according to claim 1, wherein the second wiring is a ground pattern formed in the one wiring layer and positioned in the vicinity of the power supply pattern. The electronic unit according to any one of claims 3 to 5, wherein the ground pattern extends in a direction substantially parallel to a direction in which the power supply pattern extends. A third wiring from which a current supplied from the second power source to the electronic component returns from the electronic component;
The instantaneous value of the current supplied from the first wiring to the electronic component is larger than the instantaneous value of the current supplied from the second power source to the electronic component,
The electronic unit according to claim 3, wherein the third wiring is formed with a solid ground pattern. A third wiring having a ground potential formed along the power supply pattern and the ground pattern on the one wiring layer;
The one wiring layer further includes a fourth wiring having a ground potential formed along the power supply pattern and the ground pattern,
The power supply pattern is located between the third wiring and the ground pattern,
The electronic unit according to claim 5, wherein the ground pattern is located between the fourth wiring and the power supply pattern. The distance between the third wiring and the power supply pattern is greater than twice the distance between the power supply pattern and the ground pattern,
The electronic unit according to claim 8, wherein a distance between the fourth wiring and the ground pattern is greater than twice a distance between the power supply pattern and the ground pattern. A first flat conductor having a ground potential, which is provided on the substrate and is located between the first wiring and the second wiring and the electronic component and covers the first wiring and the second wiring; The electronic unit according to claim 1, further comprising an electronic unit. A second plate-like conductor having a ground potential provided on the substrate and covering the first wiring and the second wiring;
The electronic unit according to claim 10, wherein the first wiring and the second wiring are located between the first flat conductor and the second flat conductor. The electronic unit according to claim 11, wherein the second flat conductor is a solid wiring layer included in the substrate. The substrate is a core substrate including a metal core layer;
The electronic unit according to claim 10, wherein the first flat conductor is the metal core layer. The electronic component is
A first electronic circuit;
A second electronic circuit provided at a position different from the first electronic circuit,
The first wiring supplies current to the first electronic circuit;
The electronic unit is
The connector further includes a first terminal pair that is provided on the substrate and flows a current supplied to the first electronic circuit, and a second terminal pair that flows a current supplied to the second electronic circuit. ,
The first terminal pair is located closer to the first electronic circuit than the second terminal pair,
The electronic unit according to any one of claims 1 to 13, wherein the second terminal pair is located closer to the second electronic circuit than the first terminal pair. The electronic unit according to claim 1, wherein the electronic component is an image sensor. The electronic unit according to claim 15, wherein the first wiring and the second wiring are located below a pixel portion included in the imaging element. The image sensor has a processing circuit for processing the generated pixel signal,
The electronic unit according to claim 15, wherein the first wiring passes a current supplied from the first power supply to the processing circuit. The imaging element has a pixel element that outputs a pixel signal and a vertical signal line that transmits the pixel signal,
The electronic unit is
A first connection wiring provided substantially parallel to a surface of the substrate on which the imaging element is provided and connected to the first wiring;
A second connection wiring provided substantially parallel to a surface of the substrate on which the imaging element is provided and connected to the second wiring;
A capacitor connected between the vicinity of the connection portion between the first connection wiring and the first wiring; and the capacitor connected between the second connection wiring and the second wiring and the vicinity of the connection portion;
The first connection wiring is located between the first wiring and the image sensor in a current path between the first wiring and the image sensor,
The second connection wiring is located between the second wiring and the image sensor in a current path between the second wiring and the image sensor,
The first connection wiring flows a current supplied from the capacitor to the imaging element in a direction substantially orthogonal to a transmission direction in which the vertical signal line transmits the pixel signal,
The electronic unit according to any one of claims 15 to 17, wherein the second connection wiring causes a current supplied from the capacitor to the imaging device and returning from the imaging device to flow in a direction substantially orthogonal to the transmission direction. A flexible substrate that is mounted on the substrate and supplies a current supplied to the electronic component;
The flexible substrate is
A third wiring for flowing a current supplied from the first power source to the electronic component in a third direction;
The third direction is a current provided along the third wiring adjacent to the third wiring and supplied to the electronic component through the third wiring and returning from the electronic component to the first power source. The electronic unit according to any one of claims 1 to 18, further comprising a fourth wiring that flows in a substantially opposite fourth direction. A flexible board that is mounted on the board and supplies a current supplied to the electronic component through the board;
The flexible substrate is
A third wiring for flowing a current supplied from the first power source to the electronic component;
A fourth wiring for supplying a current that is supplied to the electronic component through the third wiring and returns from the electronic component to the first power source;
The fourth wiring is configured such that at least one of a magnetic field and an electric field caused by a current flowing through the fourth wiring and returning to the first power source has a magnetic field and an electric field caused by a current flowing through the third wiring and supplied to the electronic component. 19. The electronic unit according to claim 1, wherein the electronic unit is provided along the third wiring so that at least one of the directions is canceled. The electronic unit according to claim 19 or 20, wherein the third wiring and the fourth wiring are provided side by side in the same wiring layer of the flexible substrate. The flexible substrate has a ground layer,
The electronic unit according to claim 21, wherein the ground layer is located between the wiring layer and the substrate. The flexible substrate is
A first wiring layer provided with the third wiring;
A second wiring layer adjacent to the first wiring layer and provided with the fourth wiring;
21. The electronic unit according to claim 19, wherein the third wiring is provided so that at least a part of the third wiring faces at least a part of the fourth wiring. The flexible substrate is provided facing the substrate,
The width of the substrate in the direction along the extending direction of the third wiring in a region where the substrate faces the flexible substrate is less than or equal to half of the width in the direction along the extending direction of the third wiring. 24. The electronic unit according to any one of 23. The electronic component is an image sensor having a pixel element that outputs a pixel signal and a vertical signal line that transmits the pixel signal,
The third wiring and the fourth wiring are provided in a direction at least at an angle within a range of 45 ° to 90 ° with the vertical signal line in a portion where the flexible substrate is provided to face the substrate. Item 25. The electronic unit according to any one of Items 19 to 24. The electronic component is an image sensor having a processing circuit that processes the generated pixel signal,
The electronic unit according to any one of claims 19 to 25, wherein the third wiring and the fourth wiring are located closer to the processing circuit than other wirings of the flexible substrate. A substrate,
An image sensor provided on the substrate and having a pixel element for outputting a pixel signal and a vertical signal line for transmitting the pixel signal;
A current supplied from at least a capacitor to at least one of the imaging device and another electronic component provided on the substrate is provided substantially parallel to a surface of the substrate on which the imaging device is provided. An electronic unit comprising a wiring that flows in a direction substantially orthogonal to a direction in which the pixel signal is transmitted.   An imaging device comprising the electronic unit according to any one of claims 15 to 18 and 25 to 27. A first wiring for flowing a current supplied from the first power source to the electronic component in a first direction;
The first direction is a current provided along the first wiring adjacent to the first wiring and supplied to the electronic component through the first wiring and returning from the electronic component to the first power source. A flexible substrate having a second wiring that flows in a substantially opposite second direction. A first wiring for flowing a current supplied from the first power source to the electronic component;
A second wiring for supplying a current that is supplied to the electronic component through the first wiring and returns from the electronic component to the first power source;
In the second wiring, at least one of a magnetic field and an electric field due to a current flowing through the second wiring and returning to the first power source is a magnetic field and an electric field due to a current flowing through the first wiring and supplied to the electronic component. A flexible substrate provided along the first wiring so as to be in a direction to cancel at least one.

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