JP6613899B2 - Semiconductor device driving apparatus - Google Patents

Description

  The present invention relates to a driving device for a semiconductor element applied to a power conversion device or the like.

Conventionally, a power converter using an IGBT (Insulated Gate Bipolar Transistor) which is a voltage-driven semiconductor element is known (for example, Patent Document 1). In such a power conversion device, normally, two IGBTs are connected in series to form a switching arm.
In order to suppress an increase in current flowing through the IGBT when the two IGBTs constituting the switching arm are simultaneously turned on, a diode is provided between the gate which is the control electrode of the IGBT and the emitter which is the low potential side electrode. A clamp circuit composed of a series circuit of a capacitor and a capacitor is connected.

  This clamp circuit suppresses the rise in the gate voltage Vge by charging the capacitor with a part of the current flowing into the gate via the feedback capacitance between the collector which becomes the high potential side electrode of the IGBT and the gate. Yes. The diode is inserted to prevent the charge of the capacitor from flowing back to the gate. This diode prevents the gate voltage from fluctuating when a PWM signal is applied to the gate of the IGBT.

International Publication No. 2013/157086

  However, in the conventional example described in Patent Document 1, the clamp circuit is constituted by a series circuit of a diode and a capacitor, and the anode of the diode is connected to the gate of the IGBT. For this reason, the charging voltage to the capacitor can only be charged to a voltage that is lower than the drop voltage at the diode, the storage voltage range becomes narrow, and this reduces the effect of suppressing the reverse recovery surge voltage, which will be described later. Since the capacitor is charged through a diode at the time of turn-on, the rise of the gate voltage is delayed and the turn-on loss increases.

  Therefore, the present invention has been made paying attention to the problem of the conventional example described in Patent Document 1 described above, and can reduce the turn-on loss while suppressing the reverse recovery surge voltage of the voltage controlled semiconductor element. It is an object of the present invention to provide a semiconductor device driving device.

  To achieve the above object, a semiconductor device driving apparatus according to an aspect of the present invention includes a driving circuit for driving a control electrode of a voltage-controlled semiconductor element in which freewheeling diodes are connected in antiparallel. A resistor connected between the control electrode and the drive circuit, a capacitor having one end connected between the resistor and the control electrode, the other end of the capacitor and the low potential side of the voltage-controlled semiconductor element And a switch element connected between the electrodes, and a control electrode of the switch element is connected to a connection point of the resistor and the capacitor.

  According to one aspect of the present invention, it is possible to reduce the turn-on loss while suppressing the reverse recovery surge voltage of the voltage controlled semiconductor element in which the freewheeling diodes are connected in antiparallel.

1 is a circuit diagram showing a schematic configuration of an inverter provided with a gate drive device for a semiconductor device according to a first embodiment of the present invention. It is a circuit diagram which shows an example of the gate drive device of FIG. FIG. 3 is a waveform diagram showing a gate voltage waveform when the gate driving device of FIG. 2 is turned on. FIG. 3 is a waveform diagram showing a turn-on characteristic of the gate driving device of FIG. 2. FIG. 3 is a waveform diagram showing reverse recovery operation characteristics of the gate drive circuit of FIG. 2. It is a circuit which shows the modification of a gate drive circuit.

Next, an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals.
Further, the embodiment described below exemplifies an apparatus and a method for embodying the technical idea of the present invention, and the technical idea of the present invention is the material, shape, structure, The layout is not specified as follows. The technical idea of the present invention can be variously modified within the technical scope defined by the claims described in the claims.
Hereinafter, a semiconductor device driving apparatus according to an embodiment of the present invention will be described with reference to the drawings. In the present embodiment, a voltage-driven semiconductor element is taken as an example of a semiconductor element, and a semiconductor element gate drive apparatus is taken as an example of a semiconductor element drive apparatus.

First, a power conversion device 10 including a semiconductor element gate driving device according to the present invention will be described with reference to FIG.
As shown in FIG. 1, the power conversion device 10 is connected to a three-phase AC power source 11. The power converter 10 includes a rectifier circuit 12 that full-wave rectifies three-phase AC power input from a three-phase AC power supply 11 and a smoothing capacitor 13 that smoothes the power rectified by the rectifier circuit 12. Yes. Although not shown, the rectifier circuit 12 is configured by connecting six diodes in a full bridge, or connecting six switching elements in a full bridge.

A positive electrode side line Lp is connected to the positive electrode output terminal of the rectifier circuit 12, and a negative electrode side line Ln is connected to the negative electrode output terminal. A smoothing capacitor 13 is connected between the positive electrode side line Lp and the negative electrode side line Ln.
Further, the power conversion device 10 includes an inverter circuit 21 that converts a DC voltage applied between the positive electrode side line Lp and the negative electrode side line Ln into a three-phase AC voltage. The inverter circuit 21 includes, for example, insulated gate bipolar transistors (hereinafter referred to as IGBTs) 22a, 22c, and 22e as voltage control type semiconductor elements that constitute the upper arm portion connected to the positive line Lp, and the negative line Ln. IGBT22b, 22d, 22f which comprises the lower arm part connected to this.

IGBT22a and IGBT22b are connected in series between the positive electrode side line Lp and the negative electrode side line Ln, and comprise the U-phase output arm 23U. The IGBT 22c and the IGBT 22d are connected in series between the positive electrode side line Lp and the negative electrode side line Ln to constitute a V-phase output arm 23V. The IGBT 22e and the IGBT 22f are connected in series between the positive electrode side line Lp and the negative electrode side line Ln to constitute a W-phase output arm 23W.
Refrigeration diodes 24a to 24f are connected in reverse parallel to the IGBTs 22a to 22f, respectively. That is, the cathodes of the reflux diodes 24a to 24f are respectively connected to the collectors that are the high potential side electrodes of the IGBTs 22a to 22f, and the anodes of the reflux diodes 24a to 24f are respectively connected to the emitters that are the low potential side electrodes of the IGBTs 22a to 22f. ing.

And the connection part of IGBT22a and IGBT22b, the connection part of IGBT22c and IGBT22d, and the connection part of IGBT22e and IGBT22f are each connected to the three-phase alternating current motor 15 used as an inductive load.
Moreover, the power converter device 10 has gate drive units (GDU) 25a to 25f that individually control the switching operations of the IGBTs 22a to 22f, respectively.
The output terminals of the gate driving devices 25a to 25f are connected to gate terminals that are control terminals of the IGBTs 22a to 22f, respectively.

Therefore, the inverter circuit 21 includes a three-phase full bridge circuit in which the U-phase output arm 23U, the V-phase output arm 23V, and the W-phase output arm 23W are connected in parallel, and a gate driving device that controls the switching operation of the U-phase output arm 23U. 25a and 25b, gate drive devices 25c and 25d for controlling the switching operation of the V-phase output arm 23V, and gate drive devices 25e and 25f for controlling the switching operation of the W-phase output arm 23W.
Next, the drive device according to the present embodiment will be described using the gate drive device 25b as an example with reference to FIG. 1 and FIG. The gate driving devices 25a, 25c, 25d, 25e, and 25f have the same configuration as the gate driving device 25b.

As shown in FIG. 2, the gate driving device 25b includes an interface circuit 26 to which a control signal CS (b) composed of, for example, a pulse width modulation (PWM) signal for controlling on / off of the IGBT 22b from the outside is input, and the interface circuit 26 is provided with a gate drive circuit 27 for controlling on / off of the IGBT 22b by an internal control signal output from the internal control signal 26.
The gate drive circuit 27 is connected between the positive electrode line P1 and the negative electrode line N1, and an npn-type bipolar transistor 28 and a pnp-type bipolar transistor 29 are connected in series. The npn bipolar transistor 28 has a collector connected to the positive line P 1, an emitter connected to the emitter of the pnp bipolar transistor 29, and a base connected to the interface circuit 26.

The pnp bipolar transistor 29 has an emitter connected to the emitter of the npn bipolar transistor 28, a collector connected to the negative electrode line N 1, and a base connected to the interface circuit 26.
Therefore, the npn bipolar transistor 28 is turned on when the internal control signal output from the interface circuit 26 is at a high level, and is turned off when it is at a low level. Conversely, the pnp bipolar transistor 29 is turned off when the internal control signal output from the interface circuit 26 is at a high level, and turned on when it is at a low level.

A connection point between the npn-type bipolar transistor 28 and the pnp-type bipolar transistor 29 is connected to the gate of the IGBT 22b through the gate resistor 30.
In the gate driving device 25b, as shown in FIG. 2, one end of a capacitor 31 is connected between the gate electrode serving as the control electrode of the gate resistor 30 and the IGBT 22b. The other end of the capacitor 31 is connected to an emitter serving as a low potential electrode of the IGBT 22b via a switch element 32 formed of, for example, an npn bipolar transistor.
A control terminal (base terminal) of the switch element 32 is connected to a connection point between the gate resistor 30 and the capacitor 31.

Further, a discharging resistor 33 having a resistance value larger than that of the gate resistor 30 is connected in parallel with the capacitor 31. The resistance value Rdc of the discharging resistor 33 is set to a value that allows the charged charge of the capacitor 31 to be discharged during the pulse off time when the control signal CS (b), which is a PWM signal input from the outside, has the maximum frequency. Has been.
Here, in the inverter circuit 21 of the power conversion device 10 to which the present invention is applied, the frequency of the PWM signal serving as the gate drive signal is normally set to 20 kHz or less.
Therefore, assuming that the frequency of the PWM signal is 20 kHz at the maximum, one cycle is 1/20 k = 50 μs, and if the duty ratio is 50%, the on time and the off time of the PWM signal are each 25 μs.

The relationship between the discharge time t, the time constant τ, and the discharge rate is
63.2% when t = τ
86.5% when t = 2τ
95.0% when t = 3τ
98.2% at t = 4τ
99.3% when t = 5τ
It becomes.

Here, in order to discharge the capacitor 31, it is sufficient that the discharge time is t = 3τ and the discharge rate is 95.0%, and the obtained discharge time t is an on / off time of 25 μs or less (t <25 μs).
The capacitance Cc of the capacitor 31 is expressed as the sum of the gate-collector parasitic capacitance Cgc parasitic between the gates and collectors of the IGBTs 22a to 22f and the gate-emitter parasitic capacitance Cge parasitic between the gate and emitter. The input capacitance Cies may be 1 to half, and as described above, the resistance value Rdc of the discharging resistor 33 is set to about 10 times the resistance value Rg of the gate resistor 30.

Now, assuming that the capacitance of the capacitor 31 is Cc = 20 nF, the resistance value Rg of the gate resistor 30 is 1Ω, the resistance value Rdc of the discharging resistor 33 is 10Ω, and the time constant is τ, the discharge time t of the capacitor 31 is
t = 3τ = 3 × Rdc × Cc = 3 × 10Ω × 20 nF = 600 ns
It becomes.
As a result, since the discharge time t is 600 ns, the PWM signal is sufficiently shorter than the on / off time of 25 μs, and the discharge can be sufficiently performed within the PWM signal off time.

Further, when the discharging resistor 33 is provided to discharge the capacitor 31, if the charging of the capacitor 31 is completed when the switch element 32 is in the ON state, the gate voltage Vge is changed to the gate resistor 30 and the discharging resistor 33. Will be divided. For this reason, when the gate voltage Vge of the IGBTs 22a to 22f input from the gate drive circuit 27 is + Vp = 15V which is the positive potential of the positive line P1, the voltage Vdc applied to the discharging resistor 33 is the gate of the IGBTs 22a to 22f. -It will hang between the emitters.
Since Rg = 1Ω and Rdc = 10Ω, the voltage Vdc, that is, the gate voltage Vge is
Vge = Vdc = 15V × {10 / (1 + 10)} = 13.63V
It becomes.
Therefore, when 15V is required as the gate voltage Vge, by setting + Vp, which is the positive potential of the positive line P1 of the gate drive circuit 27, to 16.5V, the gate voltage Vge = 15V.
Vge = Vdc = 16.5 × {10 / (1 + 10)} = 15V

Next, the operation of this embodiment will be described.
In the power converter 10, the three-phase AC voltage input from the three-phase AC power supply 11 is converted into a DC voltage by the rectifier circuit 12, smoothed by the smoothing capacitor 13, and then input to the inverter circuit 21. The voltage is converted and supplied to the three-phase AC motor 15.
If the electric motor is, for example, a three-phase induction motor, the upper arm of the U-phase output arm 23U, V-phase output arm 23V and W-phase output arm 23W of the inverter circuit 21 is driven at an electrical angle of 180 ° or 120 °. The signals are supplied while being shifted by 120 °, and a drive signal with an electrical angle of 180 ° or 120 ° is further advanced by 60 ° and supplied to the lower arm.

  In each phase output arm 23U to 23W, when the upper arm IGBTs 22a, 22c, and 22e are in the on state, the lower arm IGBTs 22b, 22d, and 22f are in the off state. In order to prevent the upper arm IGBT and the lower arm IGBT from being turned on at the same time, the upper arm IGBTs 22a, 22c, and 22e are turned off at the same time when the upper arm IGBTs 22a, 22c, and 22e are turned off. Dead time is provided. Conversely, there is a dead time during which the lower arm IGBTs 22b, 22d, and 22f are turned off at the same time when the lower arm IGBTs 22b, 22d, and 22f are turned off.

Then, for example, the turn-on operation will be described using the IGBT 22b constituting the lower arm of the U-phase output arm 23U as an example. First, assuming that the control signal CS (b), which is a PWM signal supplied to the gate driving device 25b, is at a low level, the internal control signal output from the interface circuit 26 is also at a low level. Therefore, the npn type bipolar transistor 28 is turned off, and the pnp type bipolar transistor 29 is turned on.
Therefore, the gate electrode of the IGBT 22b is connected to the negative potential −Vn (for example, −15V) of the negative electrode line N1 via the gate resistor 30 and the pnp bipolar transistor 29. Therefore, the gate voltage Vge of the IGBT 22b is a negative potential −Vn as shown in FIG.

At this time, the collector-emitter voltage Vce of the IGBT 22b is a high voltage that is a voltage obtained by smoothing the output of the rectifier circuit 12 with the smoothing capacitor 13, as shown on the left side of the solid line in FIG. Further, the collector current Ic is zero as shown in the left part of the solid line in FIG.
When the control signal CS (b) input to the gate driving device 25b is switched from the low level to the high level at the time point t1 in FIG. 3 from this off state, the pnp bipolar transistor 29 is turned off. Thus, the npn bipolar transistor 28 is turned on. For this reason, the positive potential + Vp of the positive electrode line P1 is applied to the gate electrode of the IGBT 22b via the npn-type bipolar transistor 28 and the gate resistor 30.

At this time, in the initial state, the gate voltage Vge increases while charging the gate capacitance of the IGBT 22b. Therefore, the gate voltage Vge rises from the negative potential −Vn of the negative electrode line N1, as shown in FIG. The gate voltage Vge at this time increases at a relatively large increase rate (dV / dt) because the gate capacitance is charged through the gate resistor 30 having a relatively small resistance value.
Thereafter, when the gate voltage Vge reaches the threshold voltage Von of the switch element 32 at time t2, the switch element 32 is turned on. For this reason, a part of the gate current is shunted and accumulated in the capacitor 31. Accordingly, as indicated by a characteristic line L11 shown by a solid line in FIG. 3, the increase rate (dV / dt) of the gate voltage Vge decreases, and the arrival time of the gate voltage Vge to the mirror voltage Vgm is delayed. For this reason, the rise of the IGBT 22b is delayed, and the turn-on loss can be reduced as compared with the characteristic line L13 shown by the chain line when the switch element 32 is omitted and only the capacitor 31 is provided.

  Here, the mirror voltage Vgm will be described. When the IGBT gate voltage Vge is close to the IGBT threshold voltage when the IGBT is turned on or turned off, the IGBT gate-collector parasitic capacitance Cgc (has an effect larger than the actual capacitance value due to the mirror effect). There is a period called a mirror period in which the gate voltage Vge is flat for charging and discharging, and the mirror voltage Vgm is the gate voltage Vge during this mirror period. The mirror period is a period in which the collector-emitter voltage Vce changes and ends when the collector-emitter voltage Vce reaches the final value.

  That is, when only the capacitor 31 is provided, when the IGBT 22b is turned on, the gate voltage Vge starts to increase from the negative potential -Vn as shown by the one-dot chain characteristic line L13 in FIG. Accumulation starts. For this reason, dV / dt gradually decreases from the start of rising of the gate voltage Vge from the negative potential −Vn. Therefore, the time until the gate voltage Vge reaches the mirror voltage Vgm of the IGBT 22b becomes long, and the turn-on loss due to the switching loss becomes large.

  However, in the present embodiment, by connecting the switch element 32 between the capacitor 31 and the emitter of the IGBT 22b, the gate voltage Vge is solid as long as the switch element 32 is maintained in the OFF state as described above. As indicated by the characteristic line L11 shown in the figure, the increase rate (dV / dt) of the gate voltage Vge indicated by the characteristic line L12 shown by the dotted line in the case where the capacitor 31 itself is not provided. For this reason, the rising edge becomes steep, and then the switching element 32 is turned on, whereby the increase rate (dV / dt) of the gate voltage Vge is reduced. Therefore, in the present embodiment, it is possible to reduce the switching loss and the turn-on loss by shortening the time until the gate voltage Vge reaches the mirror voltage Vgm of the IGBT 22b as compared with the case where only the capacitor 31 is provided.

  Further, when the gate voltage Vge reaches the mirror voltage Vgm, the collector current Ic of the IGBT 22b starts increasing from zero as shown by the characteristic line L21 shown by the solid line in FIG. 4, and the collector-emitter voltage Vce is The decrease starts as illustrated by the solid line in FIG. The increase rate (dI / dt) of the collector current Ic at this time is smaller than the increase rate (dI / dt) compared to the characteristic line L22 shown by the dotted line when the capacitor 31 is not provided. For this reason, the maximum current at the time of overshoot of the collector current Ic can be suppressed to a value smaller than the maximum current at the time of overshoot of the collector current Ic when the capacitor 31 is not provided. When only the capacitor 31 is connected, the increase rate (dI / dt) when the collector current Ic is increased can be reduced as shown by the characteristic line L23 shown in FIG. Although the maximum current at the time of shooting can be further suppressed, the turn-on loss increases as described above.

Thus, in this embodiment, at the time of turn-on, the energy accumulated in the inductance component including the wiring inductance can be suppressed by suppressing the maximum current at the time of overshoot when the collector current Ic is increased.
Next, the IGBT 22a that constitutes the upper arm and the IGBT 22b that constitutes the lower arm are both in the off state, and the energy is stored in the coil of the three-phase AC motor 15 through the freewheeling diode 24b of the IGBT 22b that constitutes the lower arm. A case in which the return current If shown in FIG.

In this return state, the anode-cathode voltage Vr of the return diode 24b is zero as shown in the left part of FIG. 5 (strictly speaking, it is dropped only by the forward voltage of the diode, but a small value). Therefore, it is ignored in FIG. In FIG. 5, the return current If is positive when the current flows in the direction opposite to the arrow Ic (b) shown in FIG.
When the IGBT 22a constituting the upper arm is controlled to be in the ON state from the return state, the return diode 24b changes from the forward bias state to the state in which the reverse bias voltage is applied. At this time, when the capacitor 31 is not provided in both of the IGBTs 22a and 22b, the return current If flowing in the return diode 24b is reduced by a relatively large reduction rate (−dI / dt as shown by the dotted line in FIG. ). Thereafter, a reverse recovery operation state is achieved in which the return current If exceeds zero and becomes a reverse recovery current flowing in the reverse direction.

That is, when the PN junction of the free-wheeling diode 24b is forward-biased, the N ⁻ layer is saturated by carrier injection, but when a reverse bias voltage is applied to the diode electrode, the PN junction is caused by reverse voltage recovery. Start the shut-off operation. However, the PN junction cannot immediately shift from the saturation state of the carriers accumulated by the forward bias to the state in which the reverse voltage is recovered, and the excess carriers accumulated in the N ⁻ layer are recovered first in the depletion layer. Starting from the PN junction portion, electrons are discharged from the N ⁻ layer side, holes are discharged from the P layer side, and current flows until excess carriers accumulated in the N ⁻ layer disappear due to recombination. This current is observed as a reverse recovery current.

In this reverse recovery operation state, as the excess carriers decrease and the reverse breakdown voltage of the PN junction recovers, the reverse recovery current decreases and does not flow. Due to the reduction rate of the reverse recovery current (-dIf / dt), a reverse recovery surge voltage (= L '× dIf / dt) is generated by the parasitic inductance L' in the circuit. The reverse recovery surge voltage has a relatively large peak value Vrp in the return voltage Vr, as indicated by a characteristic line L32 shown by a dotted line in FIG.
On the other hand, the increase rate (dI / dt) of the collector current Ic of the IGBT 22a which becomes the upper arm at the time of turn-on by providing a series circuit of the capacitor 31 and the switch element 32 in the gate driving devices 25a and 25b of the IGBTs 22a and 22b. Decreases as shown in FIG. For this reason, in the IGBT 22b serving as the lower arm, the reduction rate (−dIf / dt) of the return current If is changed from the return state to the reverse recovery operation state as compared with the case where the capacitor 31 is not provided as shown by the solid line in FIG. Become smaller. Further, the peak value of the reverse recovery current in the reverse recovery operation state is also smaller than when the capacitor 31 is not provided.

For this reason, as described above, the reverse recovery surge voltage is determined by the parasitic inductance L ′ in the circuit and the reduction rate (−dIf / dt) of the return current If. Therefore, the peak value Vrp of the reverse recovery surge voltage is shown in FIG. As shown by the characteristic line L31 shown by a solid line in FIG. 5, it can be reduced as compared with the case where the capacitor 31 is not provided.
Although the amount of reduction of the reverse recovery surge voltage according to this embodiment is small compared with the amount of reduction when only the capacitor 31 is provided (characteristic line L33 shown by a one-dot chain line in FIG. 5), a sufficient surge voltage suppression effect is obtained. be able to.

When only the capacitor 31 is provided, as described above, the capacitance of the capacitor 31 is added to the gate capacitance of the IGBT 22b, so that the gate voltage characteristic at the time of turn-on is as shown by the characteristic line L13 shown in FIG. The rise of the gate voltage Vge is delayed, the switching loss at the turn-on time is increased, the gate capacitance discharge time at the turn-off time is lengthened, and the switching loss at the turn-off time is also increased.
However, according to the present embodiment, the capacitor 31 is connected between the gate and the emitter of the IGBT 22b only during the ON period of the switch element 32, and the switching loss at turn-on is suppressed compared to the case where only the capacitor 31 is provided. can do.

  Moreover, the switching loss at turn-off can be suppressed to the same level as when the capacitor 31 is not provided. That is, in the present embodiment, at the time of turn-off, the pnp bipolar transistor 29 is turned on, and the charge accumulated in the gate capacitance of the IGBT 22b is discharged through the gate resistor 30. At this time, the electric charge accumulated in the capacitor 31 does not flow from the emitter to the collector of the npn-type bipolar transistor constituting the switch element 32 even when the switch element 32 is in an on state. The road is not formed. For this reason, at the time of turn-off, it becomes the same as the case where the capacitor 31 is not provided, and the switching loss does not increase.

The electric charge accumulated in the capacitor 31 is discharged within the off time of one pulse of the PWM signal by the discharging resistor 33 having a resistance value larger than that of the gate resistor 30.
In the conventional example described above, a capacitor is connected between the gate resistor and the gate electrode of the IGBT via a diode. For this reason, the charging voltage of the capacitor is lower than the gate voltage Vge by the drop voltage of the diode, and the effect of suppressing the reverse recovery surge voltage is limited by this amount. In contrast, in this embodiment, the base current is not limited, and the on-voltage of the bipolar transistor (the emitter-collector voltage when it is on) is sufficiently small. For this reason, since it becomes substantially equal to the capacitor 31 being directly connected between the gate resistor 30 and the gate electrode of the IGBT 22b, the charging voltage of the capacitor 31 can be fully charged up to the gate voltage Vge. Therefore, a greater reduction effect can be exhibited with respect to the reverse recovery surge voltage.

In the above embodiment, the case where an npn bipolar transistor is applied as the switch element 32 connected to the capacitor 31 is described. However, the present invention is not limited to this, and instead of the npn bipolar transistor, as shown in FIG. A series circuit of a diode 34 and an n-channel MOSFET 35 may be applied.
Here, the diode 34 may be provided between the capacitor 31 and the n-channel MOSFET 35, or may be provided between the n-channel MOSFET 35 and the emitter of the IGBT 22b, and blocks current flowing from the emitter side of the IGBT 22b toward the capacitor 31. I can do it.

As described above, by configuring the switch element 32 with the diode 34 and the n-channel MOSFET 35, it is possible to obtain the same operational effect as in the case of applying the npn-type bipolar transistor described above. Further, if the threshold voltage of the n-channel MOSFET 35 is set higher than the forward voltage of the diode, turn-on loss can be suppressed as compared with the conventional example described above.
Moreover, although the said embodiment demonstrated the case where the power converter device 10 was provided with the rectifier circuit which converts the three-phase alternating current power from the three-phase alternating current power supply 11 into direct current | flow, it is not limited to this. That is, a single-phase AC power source can be applied instead of the three-phase AC power source 11, and a DC power source such as a battery can also be used.

  The technical scope of the present invention is not limited to the illustrated and described exemplary embodiments, and includes all embodiments that provide an effect equivalent to the intended purpose of the present invention. Further, the technical scope of the present invention is not limited to the combinations of features of the invention defined by the claims, but is defined by any desired combination of specific features among all the disclosed features. obtain.

  DESCRIPTION OF SYMBOLS 10 ... Power converter, 11 ... Three-phase alternating current power supply, 12 ... Rectifier circuit, 13 ... Smoothing capacitor, 15 ... Three-phase alternating current motor, 21 ... Inverter circuit, 22a-22f ... IGBT, 23U ... U-phase output arm, 23V ... V-phase output arm, 23W ... W-phase output arm, 24a-24f ... freewheeling diode, 25a-25f ... gate drive, 26 ... interface circuit, 27 ... gate drive circuit, 30 ... gate resistor, 31 ... capacitor, 32 ... Switch element, 33 ... discharge resistor, 34 ... diode, 35 ... n-channel MOSFET

Claims (4)

A drive device for a semiconductor device comprising a drive circuit for driving a control electrode of a voltage controlled semiconductor device in which freewheeling diodes are connected in antiparallel,
A resistor connected between the control electrode and the drive circuit;
A capacitor having one end connected between the resistor and the control electrode;
A switching element connected between the other end of the capacitor and the low potential side electrode of the voltage controlled semiconductor element;
A drive device for a semiconductor element, wherein a control electrode of the switch element is connected to a connection point of the resistor and the capacitor.   2. The semiconductor element driving device according to claim 1, further comprising a discharging resistor having a resistance value larger than that of the resistor connected in parallel with the capacitor.   2. The semiconductor element driving apparatus according to claim 1, wherein the switch element is formed of an npn bipolar transistor.   2. The semiconductor element driving device according to claim 1, wherein the switch element is configured by a series circuit of a diode and an n-channel MOSFET.

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