JP6531255B2 - 光検出素子及び固体撮像装置 - Google Patents
光検出素子及び固体撮像装置 Download PDFInfo
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Description
−−第1の実施形態に係る光検出素子−−
図1及び図2に示すように、本発明の第1の実施形態に係る光検出素子は、第1導電型(p型)の半導体からなる基体領域11と、基体領域11の上面に接して設けられたゲート絶縁膜23と、ゲート絶縁膜23に接して基体領域11の上部に環状(図1の平面図においてリング状)に埋め込まれた第2導電型(n型)の電荷生成埋込領域13と、電荷生成埋込領域13の内径側の位置の基体領域11の上部に環状に埋め込まれた、電荷生成埋込領域13よりも高不純物密度の第2導電型の電荷読出領域15i,jと、電荷読出領域15i,jから離間し、電荷読出領域15i,jの内径側に埋め込まれた、電荷生成埋込領域13よりも高不純物密度の第2導電型のリセットドレイン領域16i,jと、電荷生成埋込領域13の上方となるゲート絶縁膜23上に環状に設けられた透明電極21i,jと、電荷読出領域15i,jとリセットドレイン領域16i,jとの間の基体領域11の上方となるゲート絶縁膜23上に設けられたリセットゲート電極22i,jとを備える。図2に示すように、電荷生成埋込領域13に電荷読出領域15i,jが接している。
図1及び図2に示した構造の光検出素子を単位画素とし、多数の単位画素をマトリクス状に2次元配列すれば、本発明の第1の実施形態に係る固体撮像装置(2次元イメージセンサ)のピクセルアレイ領域を実現できる。説明の便宜上、ピクセルアレイ領域を構成する多数の単位画素のうち、図7では、4つの単位画素を2×2のマトリクス状に2次元配列した平面構造によって、第1の実施形態に係る固体撮像装置を模式的に説明する。即ち、図7に示す第1の実施形態に係る固体撮像装置は、左上の(i,j)番目の画素、右上の(i,j+1)番目の画素、左下の(i−1,j)番目の画素及び右下の(i−1,j+1)番目の画素によって、2×2のマトリクス構造を構成しているピクセルアレイ領域の一部の領域における平面パターンの一例を示したものである。
−−第2の実施形態に係る光検出素子−−
図9及び図10に示すように、本発明の第2の実施形態に係る光検出素子は、第1導電型(p型)の半導体からなる基体領域11と、基体領域11の上面に接して設けられたゲート絶縁膜23と、ゲート絶縁膜23に接して基体領域11の上部に環状(図9の平面図においてリング状)に埋め込まれた第2導電型(n型)の電荷生成埋込領域13と、電荷生成埋込領域13の内径側の位置の基体領域11の上部に環状に埋め込まれた、電荷生成埋込領域13よりも高不純物密度の第2導電型の電荷読出領域15i,jと、電荷読出領域15i,jから離間し、電荷読出領域15i,jの内径側に埋め込まれた、電荷生成埋込領域13よりも高不純物密度の第2導電型のリセットドレイン領域16i,jと、電荷生成埋込領域13の上方となるゲート絶縁膜23上に環状に設けられた透明電極21i,jと、電荷読出領域15i,jとリセットドレイン領域16i,jとの間の基体領域11の上方となるゲート絶縁膜23上に設けられたリセットゲート電極22i,jとを備える点では、第1の実施形態に係る光検出素子と同様である。
図9及び図10に示した構造の光検出素子を単位画素とし、多数の単位画素をマトリクス状に2次元配列すれば、本発明の第2の実施形態に係る固体撮像装置(2次元イメージセンサ)のピクセルアレイ領域を実現できる。説明の便宜上、ピクセルアレイ領域を構成している多数の単位画素のマトリクス状配列のうち、図12では、第1の実施形態に係る固体撮像装置と同様に、4つの単位画素を2×2のマトリクス状に2次元配列した平面構造によって、第2の実施形態に係る固体撮像装置のピクセルアレイ領域を模式的に説明する。即ち、図12に示す第2の実施形態に係る固体撮像装置は、左上の(i,j)番目の画素、右上の(i,j+1)番目の画素、左下の(i−1,j)番目の画素及び右下の(i−1,j+1)番目の画素によって、ピクセルアレイ領域のうちの2×2のマトリクス構造を構成している場合の平面パターンの一例を示したものである。
上記のように、本発明は第1及び第2の実施の形態によって記載したが、この開示の一部をなす論述及び図面は本発明を限定するものであると理解すべきではない。この開示から当業者には様々な代替実施の形態、実施例及び運用技術が明らかとなろう。
12i…ウェル領域
12o…素子分離領域
13…電荷生成埋込領域
14…反転層
15i,j,15i,j+1,15i-1,j,15i-1,j+1…電荷読出領域
16i,j,16i,j+1,16i-1,j,16i-1,j+1…リセットドレイン領域
17…チャネルストップ領域
21i,j,21i,j+1,21i-1,j,21i-1,j+1…透明電極
22i,j,22i,j+1,22i-1,j,22i-1,j+1…リセットゲート電極
23…ゲート絶縁膜
25i,j,25i,j+1,25i-1,j,25i-1,j+1…転送ゲート電極
29i,j,29i,j+1,29i-1,j,29i-1,j+1…読出回路部
31i,j,31i,j+1,31i-1,j,31i-1,j+1…コンタクトホール
32i,j,32i,j+1,32i-1,j,32i-1,j+1…表面配線
33i,j,33i,j+1,33i-1,j,33i-1,j+1…コンタクトホール
51…ドレイン領域
52…ソース/ドレイン共通領域
53b,53d…リーク阻止領域
54…ソース領域
61,64…表面配線
62,63…ゲート電極
Bj,Bj+1…垂直信号線
QAi,j,QAi,j+1,QAi-1,j,QAi-1,j+1…増幅トランジスタ
TRi,j,TRi,j+1,TRi-1,j,TRi-1,j+1…リセットトランジスタ
TSi,j,TSi,j+1,TSi-1,j,TSi-1,j+…画素選択トランンジスタ
Claims (8)
- 第1導電型の半導体からなる基体領域と、
前記基体領域の上面に接して設けられたゲート絶縁膜と、
前記ゲート絶縁膜に接して前記基体領域の上部に環状に連続して埋め込まれ、全領域を受光領域として光電変換で信号電荷を生成する、第2導電型の電荷生成埋込領域と、
前記基体領域の上部において、前記電荷生成埋込領域の外形に接して前記電荷生成埋込領域を環状に囲む第1導電型で前記基体領域より高不純物密度の素子分離領域と、
前記電荷生成埋込領域の内径側の位置の前記基体領域の上部に環状に連続して埋め込まれ前記信号電荷を蓄積する、前記電荷生成埋込領域よりも高不純物密度の第2導電型の電荷読出領域と、
前記電荷読出領域から離間し、前記電荷読出領域の内径側に埋め込まれた、前記電荷生成埋込領域よりも高不純物密度の第2導電型のリセットドレイン領域と、
前記電荷生成埋込領域の上方となる前記ゲート絶縁膜上に環状に連続して設けられ、該環状の外周が前記素子分離領域の内周の外側の位置となる形状で、前記電荷生成埋込領域の外形に沿って配置された透明電極と、
前記電荷読出領域と前記リセットドレイン領域との間の前記基体領域の上方となる前記ゲート絶縁膜上に設けられたリセットゲート電極
とを備え、前記電荷生成埋込領域の表面の表面ポテンシャルを、前記電荷生成埋込領域の少数キャリアとなる電荷でピニングし、前記電荷生成埋込領域で生成された前記信号電荷が前記電荷読出領域に向かって輸送されることを特徴とする光検出素子。 - 前記リセットゲート電極に印加する電圧により、前記電荷読出領域に蓄積された電荷の内、前記信号電荷に寄与しない電荷を前記リセットドレイン領域へ排出し、前記電荷読出領域をリセットすることを特徴とする請求項1に記載の光検出素子。
- 前記電荷生成埋込領域に前記電荷読出領域が接していることを特徴とする請求項1又は2に記載の光検出素子。
- 前記電荷生成埋込領域から前記電荷読出領域が離間しており、
前記電荷生成埋込領域と前記電荷読出領域との間の前記基体領域の上方となる前記ゲート絶縁膜上に転送ゲート電極が更に配置され、
前記転送ゲート電極に印加する電圧により、前記電荷生成埋込領域から前記電荷読出領域へ前記信号電荷を転送することを特徴とする請求項1又は2に記載の光検出素子。 - 第1導電型の半導体からなる基体領域と、
前記基体領域の上面に接して設けられたゲート絶縁膜と、
前記ゲート絶縁膜に接して前記基体領域の上部に環状に連続して埋め込まれ、全領域を受光領域として光電変換で信号電荷を生成する、第2導電型の電荷生成埋込領域と、
前記基体領域の上部において、前記電荷生成埋込領域の外形に接して前記電荷生成埋込領域を環状に囲む第1導電型で前記基体領域より高不純物密度の素子分離領域と、
前記電荷生成埋込領域の内径側の位置の前記基体領域の上部に環状に連続して埋め込まれ前記信号電荷を蓄積する、前記電荷生成埋込領域よりも高不純物密度の第2導電型の電荷読出領域と、
前記電荷読出領域から離間し、前記電荷読出領域の内径側に埋め込まれた、前記電荷生成埋込領域よりも高不純物密度の第2導電型のリセットドレイン領域と、
前記電荷生成埋込領域の上方となる前記ゲート絶縁膜上に環状に連続して設けられ、該環状の外周が前記素子分離領域の内周の外側の位置となる形状で、前記電荷生成埋込領域の外形に沿って配置された透明電極と、
前記電荷読出領域と前記リセットドレイン領域との間の前記基体領域の上方となる前記ゲート絶縁膜上に設けられたリセットゲート電極
とを備える画素を複数配列し、該複数配列されたそれぞれの前記画素において、前記電荷生成埋込領域の表面の表面ポテンシャルを、前記電荷生成埋込領域の少数キャリアとなる電荷でピニングし、前記電荷生成埋込領域で生成された前記信号電荷が前記電荷読出領域に向かって輸送されることを特徴とする固体撮像装置。 - それぞれの画素において、それぞれの前記リセットゲート電極に印加する電圧により、それぞれの前記電荷読出領域に蓄積された電荷の内、前記信号電荷に寄与しない電荷を、対応する前記リセットドレイン領域へ排出し、前記電荷読出領域をリセットすることを特徴とする請求項5に記載の固体撮像装置。
- それぞれの前記画素の前記電荷生成埋込領域に前記電荷読出領域が接していることを特徴とする請求項5又は6に記載の固体撮像装置。
- それぞれの前記画素において、前記電荷生成埋込領域から前記電荷読出領域が離間しており、
それぞれの前記画素の前記電荷生成埋込領域と前記電荷読出領域との間の前記基体領域の上方となる前記ゲート絶縁膜上に、転送ゲート電極がそれぞれ更に配置され、
それぞれの前記画素において、前記転送ゲート電極に印加する電圧により、前記電荷生成埋込領域から前記電荷読出領域へ前記信号電荷が転送されることを特徴とする請求項5又は6に記載の固体撮像装置。
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