JP6507308B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims description 62
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- 229910010271 silicon carbide Inorganic materials 0.000 description 37
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 35
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 8
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
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- 229910002601 GaN Inorganic materials 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
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- ATUOYWHBWRKTHZ-UHFFFAOYSA-N Propane Chemical compound CCC ATUOYWHBWRKTHZ-UHFFFAOYSA-N 0.000 description 2
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
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Description
2 n+型エピタキシャル層 (ドレイン領域)
4 n-型エピタキシャル層 (ドリフト領域)
5 p型ウェル領域
6 n+型ソース領域
7 p+型ソース領域
8 ゲート絶縁膜
9 ゲート電極
10 ソース電極
11 層間絶縁膜
12 バルク基板
31 コレクタ電極
32 p+型エピタキシャル層 (コレクタ領域)
33 n型エピタキシャル層 (バッファ領域)
34 n+型エミッタ領域
35 p+型エミッタ領域
36 エミッタ電極
200 従来の一般的な製造プロセスにより作製されたエピタキシャル基板
201 面取り面に沿って屈曲若しくは湾曲したバルク基板/エピタキシャル層界面
202 バルク基板とエピタキシャル層が同時に存在する研削面
203 基板外周端部で本来の裏面構造とは異なる層が露出する研削面
210 第1の実施形態に係る製造プロセスにより作製されたエピタキシャル基板
211 全面において本来の裏面構造と同じ面が形成された研削面
220 第2の実施形態に係る製造プロセスにより作製されたエピタキシャル基板
221 テーパーラウンド形状に面取りした基板外周端部
301 U字型状の研削断面を有する砥石
S101 スライシング (インゴットの輪切り) 工程
S102 半導体基板の基板外周端部の面取り工程
S103 半導体基板の研削工程
S104 半導体基板の研磨工程
S105 半導体基板を用いたエピタキシャル成長工程
S201 本発明に係るエピタキシャル基板製造工程
S202 パワー半導体素子製造工程
S203 電気特性のプローブ検査および良品選別工程
S204 基板からチップをダイシングする工程
Claims (6)
- バルク基板とエピタキシャル層の界面が基板外周端部まで平坦に形成され、および基板外周端部のエッジが基板側面に対して傾斜面となっているエピタキシャル基板を準備する工程と、
前記エピタキシャル基板のエピタキシャル層のドリフト層中、およびドリフト層上に半導体素子構造を形成する工程と、
前記エピタキシャル基板を反転して、裏面のバルク基板を研削により除去する工程と、
前記バルク基板の除去により現れた前記エピタキシャル基板のエピタキシャル層に電極を形成する工程とを有することを特徴とする半導体装置の製造方法。 - 前記エピタキシャル基板を準備する工程に続けて、裏面のバルク基板を研削により除去する工程を先に実行し、
前記エピタキシャル基板のエピタキシャル層のドリフト層中、およびドリフト層上に半導体素子構造を形成する工程をその後に実行することを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記エピタキシャル基板のエピタキシャル層のドリフト層中、およびドリフト層上に半導体素子構造を形成する工程が、
前記エピタキシャル層の第1導電型を有するドリフト層中に、第2導電型を有するウェル領域を形成する工程と、
前記ウェル領域内部に第1導電型を有するソース領域、および第2導電型を有するソース領域を形成する工程と、
前記第1導電型を有するソース領域、前記ウェル領域、および前記ドリフト層を被覆してゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜の真上を被覆してゲート電極を形成する工程と、
前記ゲート電極を覆って層間絶縁膜を形成した後、前記ソース領域、および前記ウェル領域を被覆してソース電極を形成する工程と、
を含むことを特徴とする請求項1、または請求項2に記載の半導体装置の製造方法。 - バルク基板とエピタキシャル層の界面が基板外周端部まで平坦に形成され、および基板外周端部のエッジが基板側面に対して傾斜面となっているエピタキシャル基板を準備する工程と、
前記エピタキシャル基板のエピタキシャル層のドリフト層中、およびドリフト層上に半導体素子構造を形成する工程と、
前記エピタキシャル基板を反転して、裏面のバルク基板を研削により除去する工程と、
前記バルク基板の除去により現れた前記エピタキシャル基板のエピタキシャル層に電極を形成する工程と
前記エピタキシャル基板の裏面の前記電極を全面導通させて、前記エピタキシャル基板の表面の各半導体素子の電極にプローブを当てて電気的特性検査を行う工程と、
前記エピタキシャル基板のチップダイシングを行う工程とを有することを特徴とする半導体装置の製造方法。 - 前記エピタキシャル基板を準備する工程に続けて、裏面のバルク基板を研削により除去する工程を先に実行し、
前記エピタキシャル基板のエピタキシャル層のドリフト層中、およびドリフト層上に半導体素子構造を形成する工程をその後に実行することを特徴とする請求項4に記載の半導体装置の製造方法。 - 前記エピタキシャル基板のエピタキシャル層のドリフト層中、およびドリフト層上に半導体素子構造を形成する工程が、
前記エピタキシャル層の第1導電型を有するドリフト層中に、第2導電型を有するウェル領域を形成する工程と、
前記ウェル領域内部に第1導電型を有するエミッタ領域、および第2導電型を有するエミッタ領域を形成する工程と、
前記第1導電型を有するエミッタ領域、前記ウェル領域、および前記ドリフト層を被覆してゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜の真上を被覆してゲート電極を形成する工程と、
前記ゲート電極を覆って層間絶縁膜を形成した後、前記エミッタ領域、および前記ウェル領域を被覆してエミッタ電極を形成する工程と、
を含むことを特徴とする請求項1、2、4、または請求項5のいずれか1項に記載の半導体装置の製造方法。
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