JP6492068B2 - インテグレートされたパワー技術における垂直トレンチmosfetデバイス - Google Patents

インテグレートされたパワー技術における垂直トレンチmosfetデバイス Download PDF

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JP6492068B2
JP6492068B2 JP2016520001A JP2016520001A JP6492068B2 JP 6492068 B2 JP6492068 B2 JP 6492068B2 JP 2016520001 A JP2016520001 A JP 2016520001A JP 2016520001 A JP2016520001 A JP 2016520001A JP 6492068 B2 JP6492068 B2 JP 6492068B2
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deep trench
semiconductor device
gate
vertical
substrate
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JP2016536781A (ja
JP2016536781A5 (enExample
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マートゥル グル
マートゥル グル
デニソン マリー
デニソン マリー
ペンハルカル サミール
ペンハルカル サミール
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日本テキサス・インスツルメンツ合同会社
テキサス インスツルメンツ インコーポレイテッド
テキサス インスツルメンツ インコーポレイテッド
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    • HELECTRICITY
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    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109Reduced surface field [RESURF] PN junction structures
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266Bombardment with radiation with high-energy radiation producing ion implantation using masks
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    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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    • H10D30/028Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
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    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/64Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66Vertical DMOS [VDMOS] FETs
    • H10D30/663Vertical DMOS [VDMOS] FETs having both source contacts and drain contacts on the same surface, i.e. up-drain VDMOS
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    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/64Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66Vertical DMOS [VDMOS] FETs
    • H10D30/668Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
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    • H10D62/13Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149Source or drain regions of field-effect devices
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    • H10D62/156Drain regions of DMOS transistors
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    • H10D62/13Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149Source or drain regions of field-effect devices
    • H10D62/151Source or drain regions of field-effect devices of IGFETs 
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    • H10D62/17Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
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    • H10D64/111Field plates
    • H10D64/117Recessed field plates, e.g. trench field plates or buried field plates
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    • H10D64/20Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311Gate electrodes for field-effect devices
    • H10D64/411Gate electrodes for field-effect devices for FETs
    • H10D64/511Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
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    • H10D64/27Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311Gate electrodes for field-effect devices
    • H10D64/411Gate electrodes for field-effect devices for FETs
    • H10D64/511Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/519Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts
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    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/64Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66Vertical DMOS [VDMOS] FETs
    • H10D30/665Vertical DMOS [VDMOS] FETs having edge termination structures
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    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113Isolations within a component, i.e. internal isolations
    • H10D62/115Dielectric isolations, e.g. air gaps
    • H10D62/116Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
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    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
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    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
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    • H10D84/02Manufacture or treatment characterised by using material-based technologies
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    • H10D84/83Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]

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  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2016520001A 2013-10-03 2014-09-26 インテグレートされたパワー技術における垂直トレンチmosfetデバイス Active JP6492068B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/044,926 2013-10-03
US14/044,926 US9123802B2 (en) 2013-10-03 2013-10-03 Vertical trench MOSFET device in integrated power technologies
PCT/US2014/057804 WO2015050792A1 (en) 2013-10-03 2014-09-26 Vertical trench mosfet device in integrated power technologies

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JP2016536781A JP2016536781A (ja) 2016-11-24
JP2016536781A5 JP2016536781A5 (enExample) 2017-10-19
JP6492068B2 true JP6492068B2 (ja) 2019-03-27

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US (2) US9123802B2 (enExample)
EP (1) EP3053193A4 (enExample)
JP (1) JP6492068B2 (enExample)
CN (1) CN105765718B (enExample)
WO (1) WO2015050792A1 (enExample)

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US9627328B2 (en) * 2014-10-09 2017-04-18 Infineon Technologies Americas Corp. Semiconductor structure having integrated snubber resistance
WO2016204794A1 (en) * 2015-06-19 2016-12-22 Intel Corporation Vertical transistor using a through silicon via gate
DE102016112020B4 (de) * 2016-06-30 2021-04-22 Infineon Technologies Ag Leistungshalbleitervorrichtung mit vollständig verarmten Kanalregionen
DE102016112017B4 (de) 2016-06-30 2020-03-12 Infineon Technologies Ag Leistungshalbleitervorrichtung mit vollständig verarmten Kanalregionen und Verfahren zum Betreiben einer Leistungshalbleitervorrichtung
DE102016112016A1 (de) 2016-06-30 2018-01-04 Infineon Technologies Ag Leistungshalbleiter mit vollständig verarmten Kanalregionen
DE102017130092B4 (de) 2017-12-15 2025-08-14 Infineon Technologies Dresden GmbH & Co. KG IGBT mit vollständig verarmbaren n- und p-Kanalgebieten und Verfahren
US12057499B2 (en) * 2018-09-25 2024-08-06 Nxp Usa, Inc. Transistor devices with termination regions
US11171206B2 (en) * 2019-07-11 2021-11-09 Micron Technology, Inc. Channel conduction in semiconductor devices
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TWI707438B (zh) 2019-07-19 2020-10-11 力晶積成電子製造股份有限公司 電路架構
CN112086517A (zh) * 2020-10-29 2020-12-15 珠海迈巨微电子有限责任公司 一种槽栅功率半导体器件及其制备方法

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US20150325638A1 (en) 2015-11-12
JP2016536781A (ja) 2016-11-24
CN105765718B (zh) 2019-10-08
US20150097231A1 (en) 2015-04-09
EP3053193A4 (en) 2017-07-26
US9240446B2 (en) 2016-01-19
EP3053193A1 (en) 2016-08-10
US9123802B2 (en) 2015-09-01
WO2015050792A1 (en) 2015-04-09
CN105765718A (zh) 2016-07-13

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