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  • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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  • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
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  • H10D30/66—Vertical DMOS [VDMOS] FETs
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  • H10D62/149—Source or drain regions of field-effect devices
  • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
  • H10D62/156—Drain regions of DMOS transistors
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  • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
  • H10D62/149—Source or drain regions of field-effect devices
  • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
  • H10D62/156—Drain regions of DMOS transistors
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  • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
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  • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
  • H10D64/311—Gate electrodes for field-effect devices
  • H10D64/411—Gate electrodes for field-effect devices for FETs
  • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
  • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
  • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
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  • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
  • H10D64/311—Gate electrodes for field-effect devices
  • H10D64/411—Gate electrodes for field-effect devices for FETs
  • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
  • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
  • H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts
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  • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
  • H10D30/66—Vertical DMOS [VDMOS] FETs
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  • H10D62/113—Isolations within a component, i.e. internal isolations
  • H10D62/115—Dielectric isolations, e.g. air gaps
  • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
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  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions
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  • H10D84/01—Manufacture or treatment
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  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0135—Manufacturing their gate conductors
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  • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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  • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
  • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]

Definitions

• This relates in general to semiconductor devices, and in particular to drain extended transistors in semiconductor devices.
• An extended drain metal oxide semiconductor (MOS) transistor may be characterized by the resistance of the transistor in the on state, the lateral area that the transistor occupies at the top surface of the substrate containing the transistor, and the breakdown potential between the drain node and the source node of the transistor, which limits the maximum operating potential of the transistor. It may be desirable to reduce the area of the transistor for given values of the on-state resistance and the breakdown potential.
• One technique to reduce the area is to configure the drift region in the extended drain in a vertical orientation, so that drain current in the drift region flows perpendicularly to the top surface of the substrate. Integrating a vertically oriented drift region in a semiconductor device using planar processing while maintaining desired fabrication cost and complexity may be problematic.
• a semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define at least one vertical drift region bounded on at least two opposite sides by the deep trench structures.
• the deep trench structures include dielectric liners.
• the deep trench structures are spaced to form RESURF regions for the drift region.
• Vertical gates are formed in vertically oriented gate trenches in the dielectric liners of the deep trench structures, abutting the vertical drift regions.
• a body implant mask for implanting dopants for the transistor body is also used as an etch mask for forming the vertically oriented gate trenches in the dielectric liners.
• FIG. 1 is a cross-sectional view of a semiconductor device having a vertical drain extended MOS transistor.
• FIG. 2 is a cross-sectional view of a semiconductor device having a vertical drain extended MOS transistor.
• FIG. 3 A through FIG. 3G are cross-sectional views of a semiconductor device, such as the semiconductor device of FIG. 1 or FIG. 2, in successive stages of fabrication.
• FIG. 4 is a cross-sectional view of a semiconductor device with example configurations of contacts.
• FIG. 5 is a cross-sectional view of a semiconductor device containing a vertical drain extended MOS transistor and a planar MOS transistor.
• a semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define at least one vertical drift region of the transistor.
• the deep trench structures include dielectric liners.
• the vertical drift regions are bounded on at least two opposite sides by the deep trench structures.
• the deep trench structures are spaced to form RESURF regions for the drift region.
• Vertical gates are formed in trenches in the dielectric liners of the deep trench structures, abutting the vertical drift regions.
• a body implant mask for implanting dopants for a body region of the transistor is also used as an etch mask for forming the vertically oriented gate trenches in the dielectric liners.
• An optional buried drain contact layer may connect to the vertical drift regions to provide drain connections, or vertical drain contact regions (adjacent to the vertical drift regions) may provide drain connections.
• the semiconductor device may be an integrated circuit containing the vertical drain extended MOS transistor and other transistors.
• the semiconductor device may be, in another example, a discrete device in which the vertical drain extended MOS transistor is the only transistor.
• a vertical drain contact region may possibly be disposed between adjacent portions of the deep trench structures.
• RESURF refers to a material that reduces an electric field in an adjacent semiconductor region.
• a RESURF region may be a semiconductor region with an opposite conductivity type from the adjacent semiconductor region.
• RESURF structures are described in Appels, et.al, "Thin Layer High Voltage Devices” Philips J, Res. 35 1-13, 1980.
• FIG. 1 is a cross-sectional view of a semiconductor device having a vertical drain extended MOS transistor.
• the semiconductor device 100 is formed in and on a p-type semiconductor substrate 102.
• the vertical drain extended MOS transistor 110 includes deep trench structures 104 disposed in the substrate 102 to define at least one n-type vertical drain contact region 106 and adjacent n-type vertically oriented drift regions 108 separated by instances of the deep trench structures 104.
• some instances of the deep trench structures 104 separating the vertically oriented drift regions 108 may have a linear configuration, as shown in FIG. 1; a linear configuration does not have a closed loop topology.
• the at least one vertical drain contact region 106 and the vertically oriented drift regions 108 contact an n-type buried layer 112 disposed in the substrate 102.
• the deep trench structures 104 are 1 to 5 microns deep, and 0.5 to 1.5 microns wide.
• the deep trench structures 104 are all substantially equal in depth.
• the deep trench structures 104 have dielectric liners 124 and may have optional electrically conductive central members 126.
• the vertically oriented drift regions 108 are bounded on at least two opposite sides by the deep trench structures 104, which are spaced 0.5 to 2 microns apart to provide RESURF regions for the vertically oriented drift regions 108.
• the vertical drain contact regions 106 are bounded on at least two opposite sides by the deep trench structures 104, which may be spaced, such as 0.5 to 2.5 microns apart.
• Vertical gates 114 and corresponding gate dielectric layers 116 are disposed in trenches in the dielectric liners 124 of the deep trench structures 104. In this example, the vertical gates 114 do not extend laterally into curved portions of the dielectric liners 124. At least one p-type body region 118 is disposed in the substrate 102 over the vertically oriented drift regions 108 and contacting the gate dielectric layers 116. The vertical gates 114 extend below the body regions 118 to the vertically oriented drift regions 108.
• N-type source regions 120 are disposed in the substrate 102 contacting the p-type body region 118 and the gate dielectric layers 116. Optional p-type body contact regions may be disposed in the substrate 102 contacting the body region 118.
• the depth of the deep trench structures 104 may be adjusted to provide a desired operation voltage for the vertical drain extended MOS transistor 110.
• deep trench structures 104 that are 2.5 microns deep may provide 30 volt operation.
• Deep trench structures 104 that are 4 microns deep may provide 50 volt operation.
• the electrically conductive central members 126 if any, may be electrically biased to reduce a peak electric field in the vertically oriented drift regions 108.
• the electrically conductive central members 126 may be connected to source regions 120, to the vertical gates 114 or to a bias source having a desired potential.
• Configuring the vertical drain extended MOS transistor 110 in parallel ones of the vertically oriented drift regions 108 having the vertical gates 114 in each dielectric liner 124 of the deep trench structures 104 abutting the vertically oriented drift regions 108 may provide a desired value of specific resistivity, which is a product of on-state resistance and transistor area, for the vertical drain extended MOS transistor 110.
• FIG. 2 is a cross-sectional view of a semiconductor device having a vertical drain extended MOS transistor.
• the semiconductor device 200 is formed in and on a p-type semiconductor substrate 202.
• the vertical drain extended MOS transistor 210 has deep trench structures 204 disposed in the substrate 202; the deep trench structures 204 have dielectric liners 224 and optional electrically conductive central members 226.
• the deep trench structures 204 define at least one vertical drain contact region 206 by bounding the vertical drain contact regions 206 on at least two opposite sides, and surround at least one vertically oriented drift region 208 adjacent to the vertical drain contact region 206.
• the deep trench structures 204 provide RESURF regions for the vertically oriented drift regions 208.
• Each vertically oriented drift region 208 is adjacent to two deep trench structures 204, as shown in FIG. 2.
• the vertical drain contact regions 206 are n-type and extends below bottoms of the deep trench structures 204, to make electrical connection to the vertical drain contact region 206 proximate to the bottoms of the deep trench structures 204.
• a deep trench structure 204 may surround the vertical drain extended MOS transistor 210 as shown in FIG. 2.
• the deep trench structures 204 have the same depths and spacings as described in reference to FIG. 1.
• Vertical gates 214 and corresponding gate dielectric layers 216 are disposed in trenches in the dielectric liners 224 of the deep trench structures 204.
• the vertical gates 214 extend laterally into curved portions of the dielectric liners 224 to laterally surround the vertically oriented drift regions 208 as shown in FIG. 2.
• P-type body regions 218 are disposed in the substrate 202 over the vertically oriented drift regions 208 and contacting the gate dielectric layers 216.
• the vertical gates 214 extend below the body regions 218 to the vertically oriented drift regions 208.
• N-type source regions 220 are disposed in the substrate 202 contacting the p-type body region 218 and the gate dielectric layers 216.
• Operation of the vertical drain extended MOS transistor 210 is similar to that described in reference to FIG. 1.
• Configuring the vertical drain extended MOS transistor 210, so that the deep trench structures 204 surround the vertically oriented drift regions 208, and so that the vertical gates 214 extend laterally around the vertically oriented drift regions 208 may provide a desired value of specific resistivity for the vertical drain extended MOS transistor 210.
• FIG. 3 A through FIG. 3G are cross-sectional views of a semiconductor device, such as the semiconductor device of FIG. 1 or FIG. 2, in successive stages of fabrication.
• the semiconductor device 300 is formed in and on a p-type semiconductor substrate 302.
• Deep trench structures 304 of a vertical drain extended MOS transistor 310 are formed in the substrate 302 by etching deep isolation trenches in the substrate, forming dielectric liners 324 and subsequently optionally forming electrically conductive central members 326 on the dielectric liners 324.
• the deep isolation trenches may be formed by a process stating with forming a layer of hard mask material over the top surface of the substrate 302.
• a hard mask may be formed by forming an etch mask by a photolithographic followed by removing the hard mask material over regions defined for the deep isolation trenches using a reactive ion etch (RIE) process. After patterning the hard mask, material is removed from the substrate 302 in the deep isolation trenches using an anisotropic etch process, such as a Bosch deep RIE process or a continuous deep RIE process.
• RIE reactive ion etch
• the dielectric liners 324 may include thermally grown silicon dioxide.
• the dielectric liners 324 may also include one or more layers of dielectric material, such as silicon dioxide, silicon nitride and/or silicon oxynitride, formed by a chemical vapor deposition (CVD) process.
• the electrically conductive central members 326 may include polycrystalline silicon, commonly referred to as polysilicon, formed by thermally decomposing SiH4 gas inside a low-pressure reactor at a temperature of 580 °C to 650 °C. The polysilicon may be doped during formation to provide a desired electrical resistance.
• the filled deep isolation trenches form the deep trench structures 304.
• Unwanted dielectric material over the top surface of the substrate 302 from formation of the dielectric liners 324 and unwanted conductive material over the top surface of the substrate 302 from formation of the electrically conductive central members 326 may be removed, such as by using an etchback and/or chemical mechanical polish (CMP) process.
• CMP chemical mechanical polish
• the vertical drain extended MOS transistor 310 includes a vertical drain contact region, not shown in FIG. 3A through FIG. 3G, and a vertically oriented drift region 308 formed in the substrate 302.
• a drain contact ion implant process is performed, which implants n-type dopants such as phosphorus into the substrate 302 in an area defined for the vertical drain contact region, to form a drain contact implanted region.
• a dose of the drain contact ion implant process may be l x lO 16 cm "2 to 3x 10 16 cm "2 .
• a drift region ion implant process is performed, which implants n-type dopants such as phosphorus into the substrate 302 in and over an area defined for the vertically oriented drift region 308, to form drift implanted regions.
• a dose of the drain contact ion implant process is at least ten times higher than the drift region ion implant dose.
• a thermal drive operation is performed, which heats the substrate 302 to activate and diffuse the implanted dopants in the drain contact implanted region and the drift implanted region and thereby form the vertical drain contact region and the vertically oriented drift region 308, respectively.
• Conditions of the thermal drive operation depend on a depth of the deep trench structures 304 and a desired lateral extent of the vertical drain contact region at the bottoms of the deep trench structures 304.
• a vertical drain extended MOS transistor 310 with deep trench structures 304 that are 2.5 microns deep may have a thermal drive operation that heats the substrate 302 at 1100 °C for 3.5 to 4 hours, or equivalent anneal conditions, such as 1125 °C for 2 hours, or 1050 °C for 12 hours.
• a body implant mask 328 is formed over the substrate 302 to expose an area of the vertically oriented drift region 308 defined for a body region of the vertical drain extended MOS transistor 310.
• the body implant mask 328 may include primarily photoresist, or may include hard mask material such as silicon nitride. The area exposed by the body implant mask 328 extends over the dielectric liners 324 abutting the area defined for the body region.
• a body implant process is performed, which implants p-type dopants such as boron into the substrate 302 in the area exposed by the body implant mask 328 to form a body implanted region 330.
• a dose of the body implant process may be I x l0 13 cm “2 to 5x l0 13 cm “2 .
• a gate trench etch operation is performed, which uses the body implant mask 328 as an etch mask.
• Dielectric material is removed from the dielectric liners 324 by the gate trench etch operation to form vertically oriented gate trenches 332 adjacent to, and extending below, the body implanted region 330.
• the gate trench etch operation may be a timed etch.
• a wet clean operation such as including a dilute aqueous solution of hydrofluoric acid, may be performed after the gate trench etch operation to remove residue from sides of the vertically oriented gate trenches 332.
• the body implant mask 328 may be removed after the gate trench etch operation is completed.
• a gate dielectric layer 316 is formed on the substrate 302 in the vertically oriented gate trenches 332 and possibly on other exposed semiconductor surfaces of the substrate 302.
• the gate dielectric layer 316 may be one or more layers of silicon dioxide, silicon oxy-nitride, aluminum oxide, aluminum oxy-nitride, hafnium oxide, hafnium silicate, hafnium silicon oxy-nitride, zirconium oxide, zirconium silicate, and/or zirconium silicon oxy-nitride.
• the gate dielectric layer 316 may include nitrogen as a result of exposure to a nitrogen containing plasma or a nitrogen-containing ambient gas at temperatures between 50 C and 800 C.
• the gate dielectric layer 316 may be formed by any of a variety of gate dielectric formation processes, such as thermal oxidation, plasma nitridation of an oxide layer, and/or dielectric material deposition by atomic layer deposition (ALD).
• a thickness of the gate dielectric layers 316 may be 2.5 to 3.3 nanometers per volt of gate-source bias on the vertical drain extended MOS transistor 310.
• an instance of the vertical drain extended MOS transistor 310 operating with 30 volts of gate-source bias may have the gate dielectric layer 316 with a thickness of 75 to 100 nanometers.
• Formation of the gate dielectric layer 316 may involve heating the substrate 302, so that the p-type dopants in the body implanted region 330 of FIG. 3C diffuse and become activated to form a p-type body region 318.
• growing a thermal oxide for the gate dielectric layer 316 may provide a sufficient thermal profile to diffuse the p-type dopants in the body implanted region 330, so that the body region 318 extends to a desired depth in the substrate 302.
• a thermal process such as an anneal may be performed to provide a desired depth for the body region 318.
• a layer of gate material 334 is formed on the gate dielectric layer 316 in the vertically oriented gate trenches 332, and possibly on other areas of the semiconductor device 300.
• the layer of gate material 334 may be polysilicon, or may be one or more layers of other conductive materials such as metal silicide or titanium nitride.
• the layer of gate material 334 of FIG. 3E is patterned to leave gate material in the vertically oriented gate trenches to form vertical gates 314.
• the vertical gates 314 extend below the body region 318.
• the vertical gates 314 may be electrically isolated from the electrically conductive central members 326 by dielectric material.
• an n-type source region 320 is formed in the substrate 302 adjacent to the gates 314 and abutting the body region 318 opposite from the vertically oriented drift region 308.
• One or more optional p-type body contact regions 322 may be disposed in the substrate 302 abutting the body region 318.
• FIG. 4 is a cross-sectional view of a semiconductor device with example configurations of contacts.
• the semiconductor device 300 is formed in and on a p-type semiconductor substrate 302.
• Deep trench structures 304 of a vertical drain extended MOS transistor 310 including dielectric liners 324 and electrically conductive central members 326 are disposed in the substrate 302.
• An n-type vertically oriented drift region 308 is disposed in the substrate 302 abutted on at least two sides by the deep trench structures 304, which provide RESURF regions for the vertically oriented drift region 308.
• a p-type body region 318 is disposed in the substrate 302 over the vertically oriented drift region 308.
• An n-type source region 320 is disposed in the substrate 302 above the body region 318.
• Vertical gates 314 and gate dielectric layers 316 are disposed in the deep trench structures 304 as described in reference to FIG. 1.
• the vertical gates 314 are patterned to overlap the electrically conductive central members 326.
• the vertical gates 314 may be patterned using a photolithographically generated etch mask followed by an RIE process.
• Gate contacts 336 are formed to make electrical connection to the vertical gates 314 on the overlap areas over the electrically conductive central members 326.
• Optional contacts 328 may be formed to make electrical connection to the electrically conductive central members 326.
• FIG. 5 is a cross-sectional view of a semiconductor device containing a vertical drain extended MOS transistor and a planar MOS transistor.
• the vertical drain extended MOS transistor 310 includes vertical gates 314 and gate dielectric layers 316 are formed in dielectric liners 324 of deep trench structures disposed in a substrate 302 of the semiconductor device 300.
• the gate dielectric layers 316 and the vertical gates 314 overlap a top surface of the substrate 302, which may simplify fabrication of the trench gates 314.
• the trench gates 314 may be formed by an RIE process using a photolithographically defined etch mask.
• the gate dielectric layers 316 and the trench gates 314 may be formed concurrently with a transistor gate dielectric layer 340 and a transistor gate 342 of a planar MOS transistor 344.

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• 2013
  • 2013-10-03 US US14/044,926 patent/US9123802B2/en active Active
• 2014
  • 2014-09-26 CN CN201480065238.0A patent/CN105765718B/zh active Active
  • 2014-09-26 EP EP14850299.0A patent/EP3053193A4/en not_active Withdrawn
  • 2014-09-26 WO PCT/US2014/057804 patent/WO2015050792A1/en not_active Ceased
  • 2014-09-26 JP JP2016520001A patent/JP6492068B2/ja active Active
• 2015
  • 2015-07-23 US US14/807,276 patent/US9240446B2/en active Active

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