JP6479815B2 - 電子回路のための高度にスケーラブルな製造技術及びパッケージングデバイス - Google Patents
電子回路のための高度にスケーラブルな製造技術及びパッケージングデバイス Download PDFInfo
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- JP6479815B2 JP6479815B2 JP2016541303A JP2016541303A JP6479815B2 JP 6479815 B2 JP6479815 B2 JP 6479815B2 JP 2016541303 A JP2016541303 A JP 2016541303A JP 2016541303 A JP2016541303 A JP 2016541303A JP 6479815 B2 JP6479815 B2 JP 6479815B2
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- 238000004519 manufacturing process Methods 0.000 title claims description 91
- 238000004806 packaging method and process Methods 0.000 title claims description 23
- 238000005516 engineering process Methods 0.000 title description 27
- 238000000034 method Methods 0.000 claims description 278
- 239000000758 substrate Substances 0.000 claims description 237
- 239000000463 material Substances 0.000 claims description 84
- 239000010410 layer Substances 0.000 claims description 56
- 238000000151 deposition Methods 0.000 claims description 39
- 239000012777 electrically insulating material Substances 0.000 claims description 33
- 238000013461 design Methods 0.000 claims description 27
- 229920001971 elastomer Polymers 0.000 claims description 20
- 239000000806 elastomer Substances 0.000 claims description 20
- 239000002245 particle Substances 0.000 claims description 18
- 239000010409 thin film Substances 0.000 claims description 18
- 239000007787 solid Substances 0.000 claims description 16
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 claims description 15
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 14
- 229920001721 polyimide Polymers 0.000 claims description 11
- 239000004642 Polyimide Substances 0.000 claims description 10
- 239000012530 fluid Substances 0.000 claims description 10
- 239000012790 adhesive layer Substances 0.000 claims description 8
- 229910052799 carbon Inorganic materials 0.000 claims description 7
- 239000002041 carbon nanotube Substances 0.000 claims description 7
- 229910021393 carbon nanotube Inorganic materials 0.000 claims description 7
- 238000001723 curing Methods 0.000 claims description 7
- 239000002070 nanowire Substances 0.000 claims description 7
- 229920001296 polysiloxane Polymers 0.000 claims description 7
- 229920001187 thermosetting polymer Polymers 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 6
- 238000000465 moulding Methods 0.000 claims description 5
- 230000003287 optical effect Effects 0.000 claims description 5
- 238000000016 photochemical curing Methods 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 3
- 238000002211 ultraviolet spectrum Methods 0.000 claims description 2
- 238000005266 casting Methods 0.000 description 38
- 239000012778 molding material Substances 0.000 description 25
- 239000010408 film Substances 0.000 description 24
- 229910052751 metal Inorganic materials 0.000 description 11
- 239000002184 metal Substances 0.000 description 11
- 230000006870 function Effects 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000012545 processing Methods 0.000 description 7
- 239000004205 dimethyl polysiloxane Substances 0.000 description 6
- 235000013870 dimethyl polysiloxane Nutrition 0.000 description 6
- 239000007788 liquid Substances 0.000 description 6
- CXQXSVUQTKDNFP-UHFFFAOYSA-N octamethyltrisiloxane Chemical compound C[Si](C)(C)O[Si](C)(C)O[Si](C)(C)C CXQXSVUQTKDNFP-UHFFFAOYSA-N 0.000 description 6
- 239000012071 phase Substances 0.000 description 6
- 238000004987 plasma desorption mass spectroscopy Methods 0.000 description 6
- 229920000435 poly(dimethylsiloxane) Polymers 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000013459 approach Methods 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 235000012431 wafers Nutrition 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 239000013536 elastomeric material Substances 0.000 description 4
- 229920000642 polymer Polymers 0.000 description 4
- 238000004528 spin coating Methods 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 2
- VRBFTYUMFJWSJY-UHFFFAOYSA-N 28804-46-8 Chemical group ClC1CC(C=C2)=CC=C2C(Cl)CC2=CC=C1C=C2 VRBFTYUMFJWSJY-UHFFFAOYSA-N 0.000 description 1
- 238000010146 3D printing Methods 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- WYTGDNHDOZPMIW-RCBQFDQVSA-N alstonine Natural products C1=CC2=C3C=CC=CC3=NC2=C2N1C[C@H]1[C@H](C)OC=C(C(=O)OC)[C@H]1C2 WYTGDNHDOZPMIW-RCBQFDQVSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000012993 chemical processing Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 229920005839 ecoflex® Polymers 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000000313 electron-beam-induced deposition Methods 0.000 description 1
- 229920005570 flexible polymer Polymers 0.000 description 1
- -1 for example Substances 0.000 description 1
- 238000005470 impregnation Methods 0.000 description 1
- 238000001727 in vivo Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000005459 micromachining Methods 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003223 poly(pyromellitimide-1,4-diphenyl ether) Polymers 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 229920002379 silicone rubber Polymers 0.000 description 1
- 238000010099 solid forming Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
- 239000011345 viscous material Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/118—Printed elements for providing electric connections to or between printed circuits specially for flexible printed circuits, e.g. using folded portions
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L23/145—Organic substrates, e.g. plastic
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5387—Flexible insulating substrates
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
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- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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- H05K1/02—Details
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- H05K1/18—Printed circuits structurally associated with non-printed electric components
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- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
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- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
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- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/465—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer having channels for the next circuit layer
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- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/2401—Structure
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H01L2224/2401—Structure
- H01L2224/2402—Laminated, e.g. MCM-L type
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24101—Connecting bonding areas at the same height
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
- H01L2224/251—Disposition
- H01L2224/2512—Layout
- H01L2224/25175—Parallel arrangements
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- H01L2224/82001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus
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- H01L2224/82009—Pre-treatment of the connector or the bonding area
- H01L2224/82051—Forming additional members
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- H01L2224/821—Forming a build-up interconnect
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Description
以下の実施例は、本技術の幾つか実施形態を例示するものである。本技術の他の例示的な実施形態は、以下にリストする実施例の前に、又は以下にリストする実施例の後に示す実施形態も含まれる。
Claims (55)
- 回路又は電子デバイスを製造する方法において、
フレキシブルな電気絶縁性材料を含む基板上の位置に電子部品を取り付けることであって、前記基板は、前記電子部品が取り付けられる側の反対側に平らな表面を含むことと、 前記電子部品及び前記基板の表面に順応する相の材料を堆積させ、前記材料を固体状態に変化させることによって、前記基板に取り付けられた前記電子部品を収容するテンプレートを形成することと、
前記基板に開口を形成し、前記電子部品の導電部分を露出させ、前記基板上に、特定の構成で前記導電部分の少なくとも幾つかに接続する電気相互接続を形成し、前記基板上で前記電気相互接続上に電気絶縁性のフレキシブル材料の層を堆積させて、回路のフレキシブルベースを形成することによって、前記テンプレートに収容された回路又は電子デバイスを作成することと、
前記作成された回路又は電子デバイスを前記テンプレートから解放することと、
を含む方法。 - 前記電子部品は、回路要素、回路又はマイクロチップを含む請求項1記載の方法。
- 前記導電部分は、前記回路又は前記マイクロチップのコンタクトパッドを含む請求項2記載の方法
- 前記マイクロチップはベアダイマイクロチップ又は薄膜マイクロチップを含む請求項2記載の方法。
- 前記回路は、集積回路、薄膜回路、センサ回路、トランスデューサ回路、増幅器回路、パワーコンバータ回路又はオプトカプラ回路を含む請求項2記載の方法。
- 前記回路要素は、ダイオード、発光ダイオード(LED)、トランジスタ、バッテリ又はインピーダンス素子を含む請求項2記載の方法。
- 前記取付けられた電子部品は、前記作成された回路又は電子デバイスの設計に基づく所定の位置に取り付けられた電子部品を含む請求項1記載の方法。
- 前記テンプレートは、前記電子部品が収容された面とは反対側の面である平らなベース面を含む請求項1記載の方法。
- 前記基板に電子部品を取り付けることは、前記電子部品の前記導電部分が前記基板に接触するように前記電子部品を向けることを含む請求項1記載の方法。
- 前記電子部品が取り付けられた前記基板を、前記基板の面積より大きい面積、及び前記基板上に取り付けられた前記電子部品の組み合わされた高さ以上の高さを有するウェル内に配置することを更に含み、前記配置は、前記基板が、前記ウェルの底部に配置され、前記電子部品が前記ウェルの開口に向くように行われる請求項1記載の方法。
- 前記テンプレートを形成することは、前記表面に順応する相の前記堆積された材料に対して、平らな表面を有する上位基板を適用して、前記固体状態の前記テンプレートの平らな表面を形成することを含む請求項10記載の方法。
- 前記ウェルから、前記基板に取り付けられた前記電子部品を収容する前記テンプレートを取り外すことと、
前記平らな表面上で電子部品を収容する前記テンプレートを、前記基板が上向きになり、前記テンプレートが前記平らな表面と接触するように配置することとを更に含む請求項11記載の方法。 - 前記テンプレートを形成することは、最初に、外面又はウェル内に前記表面に順応する相の前記材料を堆積させて、前記基板上に取り付けられた前記電子部品を前記堆積された材料に埋め込み、前記材料が前記電子部品の表面に順応することを含む請求項1記載の方法。
- 前記フレキシブルな電気絶縁性材料は、ポリイミド、シリコーンベースエラストマ、ベンゾシクロブタン(BCB)、SU−8、又はカーボン粒子、カーボンナノチューブ若しくはSiナノワイヤを含む付加的な導電性粒子を含むエラストマを含む請求項1記載の方法。
- 前記基板に前記電子部品を取り付ける前に前記基板上に更なる接着剤層を堆積させることを更に含む請求項1記載の方法。
- 前記作成された回路又は電子デバイスをプリント回路基板に統合することを更に含む請求項1記載の方法。
- 前記作成された回路又は電子デバイスの前記電子部品を有する側に、電気絶縁性材料を含む外側基板を形成することを更に含む請求項1記載の方法。
- 前記解放されたテンプレートを用いて、他の回路又は電子デバイスを製造することを更に含み、前記テンプレートは、前記テンプレートの形成プロセスから前記電子部品によって形成された空洞を含み、前記他の回路又は電子デバイスを製造することは、
前記テンプレートの前記空洞に電子部品を配置することと、
前記空洞に配置された前記電子部品を含む前記テンプレートの受取表面上にフレキシブルな電気絶縁性材料を含む基板を形成し、前記電子部品を基板に取り付け、前記基板は、前記電子部品が取り付けられる側の反対側に平らな表面を含むことと、
前記基板に開口を形成し、前記電子部品の導電部分を露出させ、前記基板上に、特定の構成で前記導電部分の幾つかに接続する電気相互接続を形成し、前記基板上で前記電気相互接続上に電気絶縁性のフレキシブル材料の層を堆積させて、回路のフレキシブルベースを形成することによって、前記テンプレートに収容され、前記テンプレートから解放可能な他の回路又は電子デバイスを作成することと、
を含む請求項1記載の方法。 - 前記テンプレートに収容された回路又は電子デバイスをプリント回路基板に統合することを更に含む請求項1記載の方法。
- 前記回路又は電子デバイスを作成することは、前記基板上で電子要素を形成することと、前記電子要素を前記電子部品又は前記電気相互接続に電気的に接続する更なる電気相互接続を形成することとを更に含む請求項1記載の方法。
- 前記電子要素は、ダイオード、発光ダイオード(LED)、トランジスタ、バッテリ、インピーダンス素子、集積回路、薄膜回路、センサ、トランスデューサ、増幅器、パワーコンバータ、オプトカプラ又はマイクロチップを含む請求項20記載の方法。
- 一方の側に1つ以上の電子部品を接着するように構成された、フレキシブルな電気絶縁性材料を含む基板であって、前記一方の側から前記基板の内部領域に亘る開口を含み、前記開口は、前記1つ以上の電子部品の導電コンタクトが配置されるように設計されている位置に整列する基板と、
デバイス設計に基づく特定の構成で前記基板の開口及び内部領域に配置され、前記1つ以上の電子部品を電気的に接続する導電性材料を含む相互接続ワイヤと、
前記基板の一方の側に取り付けられるコンタクト側を含むように構成された電気絶縁性材料を含むテンプレート構造と、を備え、
前記テンプレート構造は、前記コンタクト側において、前記基板の接着される対応する1つ以上電子部品を包含する特定の位置に1つ以上の空洞を含み、
前記基板は、20μmより小さい厚さを有する電子デバイスパッケージ。 - 前記基板に接着される1つ以上の電子部品は、回路要素、回路又はマイクロチップを含む請求項22記載の電子デバイスパッケージ。
- 前記回路は、集積回路、薄膜回路、センサ回路、トランスデューサ回路、増幅器回路、パワーコンバータ回路又はオプトカプラ回路を含む請求項23記載の電子デバイスパッケージ。
- 前記回路要素は、ダイオード、発光ダイオード(LED)、トランジスタ、バッテリ又はインピーダンス素子を含む請求項23記載の電子デバイスパッケージ。
- 前記マイクロチップは、ベアダイマイクロチップ又は薄膜マイクロチップを含む請求項23記載の電子デバイスパッケージ。
- 前記基板は、前記一方の側を含む平面において、前記ベアダイマイクロチップの対応する長さを超える長さが、200μm以下になるように構成されている請求項26記載の電子デバイスパッケージ。
- 前記フレキシブルな電気絶縁性材料は、ポリイミド、シリコーンベースエラストマ、ベンゾシクロブタン(BCB)、SU−8、又はカーボン粒子、カーボンナノチューブ若しくはSiナノワイヤを含む付加的な導電性粒子を含むエラストマを含む請求項22記載の電子デバイスパッケージ。
- 前記相互接続ワイヤは、前記内部領域における平らな層に形成され、前記電子デバイスパッケージングは、更に、
前記基板の内部領域に配置され、前記相互接続ワイヤの少なくとも幾つかに電気的に接続される更なる相互接続ワイヤの第2の層を備え、
前記第2の層は、前記基板の厚さが35μm未満となるように、15μm未満の厚さを有するように構成されている請求項22記載の電子デバイスパッケージ。 - 前記基板の内部領域又は前記基板の外面に配置されている電子要素を更に備え、
前記相互接続ワイヤは、前記電子要素の少なくとも幾つかを前記電子部品又は前記電気相互接続に電気的に接続するように構成されている請求項22記載の電子デバイスパッケージ。 - 前記電子要素は、ダイオード、発光ダイオード(LED)、トランジスタ、バッテリ、インピーダンス素子、集積回路、薄膜回路、センサ、トランスデューサ、増幅器、パワーコンバータ、オプトカプラ又はマイクロチップを含む請求項30記載の電子デバイスパッケージ。
- 回路又は電子デバイスを製造する方法において、
テンプレートの第1の側の空洞に電子部品を配置することであって、前記テンプレートの前記空洞は、前記電子部品と実質的に同じ幾何学的形状を有するように構成されており、前記配置は、前記電子部品の導電部分が露出し、前記第1の側が平らになるように前記電子部品を前記空洞に収容することと、
前記空洞に配置された前記電子部品を含む前記テンプレートの前記第1の側にフレキシブルな電気絶縁性材料を含む基板を形成し、前記電子部品を前記基板に取り付けることであって、前記基板は、前記電子部品が取り付けられる側の反対側に平らな表面を含むことと、
前記基板に開口を形成し、前記電子部品の導電部分を露出させ、前記基板上に特定の構成で前記導電部分の少なくとも幾つかに接続する電気相互接続を形成し、前記基板上で前記電気相互接続上に電気絶縁性のフレキシブル材料の層を堆積させて、回路のフレキシブルベースを形成することによって、前記テンプレートに収容された回路又は電子デバイスを作成することと、
を含む方法。 - 前記電子部品は、回路要素、回路又はマイクロチップを含む請求項32記載の方法。
- 前記取付けられた電子部品は、前記作成された回路又は電子デバイスの設計に基づく所定の位置に取り付けられた電子部品を含む請求項32記載の方法。
- 前記基板のフレキシブルな電気絶縁性材料は、光硬化材料であり、前記基板を形成することは、前記光硬化材料を堆積させて前記テンプレートの前記第1の側上に層を形成することと、前記光硬化材料層に光信号を適用し、前記光硬化材料を硬化させることとを含む請求項32記載の方法。
- 前記光信号は、紫外スペクトルの波長を有するように選択される請求項35記載の方法。
- 前記基板のフレキシブルな電気絶縁性材料は、熱硬化材料であり、前記基板を形成することは、前記熱硬化材料を堆積させて前記テンプレートの前記第1の側上に層を形成することと、前記層に熱を適用して前記熱硬化材料を硬化させることとを含む請求項32記載の方法。
- 前記適用される熱は、250℃を含む請求項37記載の方法。
- 前記電子部品が前記基板に配置される位置において、前記電子部品と同じ幾何学的形状を有するモデル部品をベース構造に取り付けることによってモールドマスタ構造を形成することと、
前記モデル部品及び前記ベースの表面に順応する層の材料を堆積させ、前記材料を固体状態に変化させてテンプレートを形成することと、
を含む請求項32記載の方法。 - 前記フレキシブルな電気絶縁性材料は、ポリイミド、シリコーンベースエラストマ、ベンゾシクロブタン(BCB)、SU−8、又はカーボン粒子、カーボンナノチューブ若しくはSiナノワイヤを含む付加的な導電性粒子を含むエラストマを含む請求項32記載の方法。
- 前記作成された回路又は電子デバイスを前記テンプレートから解放することを更に含む請求項32記載の方法。
- 前記作成された回路又は電子デバイスをプリント回路基板に統合することを更に含む請求項41記載の方法。
- 前記作成された回路又は電子デバイスの前記電子部品を有する側に、湿気、温度、圧力又はpHに起因する有害な状況から前記作成された回路又はデバイスを保護する能力を有する電気絶縁性材料を含む外側基板を形成することを更に含む請求項32記載の方法。
- 前記解放されたテンプレートを使用して、他の回路又は電子デバイスを製造することを更に含む請求項32記載の方法。
- 前記テンプレートに収容された回路又は電子デバイスをプリント回路基板に統合することを更に含む請求項32記載の方法。
- 前記回路又は電子デバイスを作成することは、前記基板上に電子要素を形成することと、前記電子要素の少なくとも幾つかを前記電気コンポーネント又は電気相互接続に電気的に接続する更なる電気相互接続を形成することとを更に含む請求項32記載の方法。
- 前記更なる電子要素は、ダイオード、発光ダイオード(LED)、トランジスタ、バッテリ、インピーダンス素子、集積回路、薄膜回路、センサ、トランスデューサ、増幅器、パワーコンバータ、オプトカプラ又はマイクロチップの少なくとも1つを含む請求項46記載の方法。
- 回路を製造する方法において、
フレキシブルな電気絶縁性材料を含む基板の選択された位置に電子部品を取り付けることと、
前記電子部品及び前記基板の表面に順応する流体状態のテンプレート材料を堆積させ、前記テンプレート材料を流体状態から固体状態に変化させることによって、前記基板に取り付けられた前記電子部品を収容するテンプレートを形成することと、
前記基板に前記電子部品の導電部分への開口を形成し、前記基板上に、選択された構成で前記導電部分間の電気相互接続を作成し、前記電気相互接続上及び露出した基板上に電気絶縁性のフレキシブル材料の層を堆積させ、回路のフレキシブルな絶縁のベースを形成することによって回路を形成することと、
前記テンプレートから前記回路を解放することと、
を含む方法。 - 前記電子部品は、回路要素又はマイクロチップの1つ以上を含む請求項48記載の方法。
- 前記導電部分は、前記回路要素又は前記マイクロチップのコンタクトパッドを含む請求項49記載の方法。
- 前記取り付けることは、前記電子部品の前記導電部分を前記基板に接触させることを含む請求項48記載の方法。
- 前記電子部品が取り付けられた基板をモールディング基板のウェルに配置し、前記配置は、前記基板が前記ウェルの底部に配置され、前記電子部品が前記ウェルの開口を向くように行われる請求項48記載の方法。
- 前記堆積されたテンプレート材料に対して、平らな表面を有する上位基板を適用して、前記硬化されたテンプレートの平らな表面を形成することを更に含む請求項52記載の方法。
- 前記基板に取り付けられた前記電子部品を収容するテンプレートを取り除くことと、
前記基板が上向きになり、前記硬化されたテンプレート材料が前記平らな表面と接触するように前記テンプレートを平らな表面に配置することとを更に含む請求項53記載の方法。 - 前記テンプレート材料を堆積させることは、前記基板に取り付けられた前記電子部品を前記流体状態のテンプレート材料内に埋め込むことを含む請求項48記載の方法。
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