JP6319141B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  As a semiconductor device, a power device capable of obtaining a high electric field breakdown strength is known (for example, Patent Document 1).

Japanese Patent No. 4798119

In a semiconductor device used as such a power device, when a trench gate structure is adopted, electric field concentration may occur in a gate oxide film formed in the trench. Therefore, in the technique described in Patent Document 1, by providing a p ⁺ -type deep layer that is the same as or deeper than the trench at a position away from the side surface of the trench, electric field concentration in the gate insulating film is reduced. It is relaxed.

However, although the technique described in Patent Document 1 can alleviate the electric field concentration in the trench, there is a possibility that the electric field concentrates on the corner on the trench side on the bottom surface of the p ⁺ type deep layer. For this reason, a technique that can further reduce electric field concentration has been desired. In addition, the conventional semiconductor device has been desired to be downsized, save resources, facilitate manufacturing, improve manufacturing accuracy, and improve workability.

SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms.
The first aspect of the present invention is:
A trench gate type semiconductor device,
A first N-type semiconductor layer formed of a hexagonal semiconductor;
A P-type semiconductor layer stacked on the first N-type semiconductor layer and formed of a hexagonal semiconductor;
A groove portion penetrating through the P-type semiconductor layer to reach the first N-type semiconductor layer,
The first N-type semiconductor layer includes a convex portion formed so as to cover the periphery of the groove portion,
A side surface of the convex portion is a {11-20} plane (including an equivalent plane),
The convex part is provided with a protruding part below the side surface,
The trench is provided with a gate electrode through an insulating film,
It is a semiconductor device. The present invention can also be realized as the following forms.

(1) According to an aspect of the present invention, a method for manufacturing a semiconductor device is provided. In this method for manufacturing a semiconductor device, a first N-type semiconductor layer formed of a hexagonal semiconductor is provided with a convex portion having a {11-20} plane (including an equivalent plane) as a side surface. And a second step of forming a P-type semiconductor layer with a hexagonal semiconductor on the first N-type semiconductor layer. According to the manufacturing method of this embodiment, the N-type protrusion is formed inside the P-type semiconductor layer below the side surface of the protrusion. For this reason, the end of the depletion layer formed in the P-type semiconductor layer is moved away from the lower side of the convex side surface, and the electric field concentration on the lower side of the convex side surface can be reduced. As a result, according to the manufacturing method of this embodiment, the electric field concentration of the semiconductor device can be relaxed.

(2) In the method of manufacturing a semiconductor device according to the above aspect, the first step and the second step may be performed by different apparatuses.

(3) In the method of manufacturing a semiconductor device according to the above aspect, the second step may be performed by an MOCVD method.

(4) According to an aspect of the present invention, a semiconductor device is provided. The semiconductor device includes a first N-type semiconductor layer formed of a hexagonal semiconductor, a P-type semiconductor layer stacked on the first N-type semiconductor layer, and formed of a hexagonal semiconductor; A groove portion that penetrates through the P-type semiconductor layer and reaches the first N-type semiconductor layer, and the first N-type semiconductor layer includes a convex portion that is formed to cover the periphery of the groove portion. The side surface of the convex portion is a {11-20} plane (including an equivalent surface), and the convex portion is provided with a protrusion below the side surface. According to the semiconductor device of this embodiment, since the N-type protrusion is provided inside the P-type semiconductor layer below the side surface of the convex portion, the end of the depletion layer formed in the P-type semiconductor layer is moved away from the lower side of the convex side surface, It is possible to alleviate electric field concentration below the side surface of the convex portion. As a result, the electric field concentration of the semiconductor device can be reduced.

(5) In the semiconductor device of the above aspect, the P-type semiconductor layer may be mainly formed of a nitride semiconductor containing gallium.

(6) In the semiconductor device of the above aspect, the P-type semiconductor layer may be mainly formed of gallium nitride.

(7) In the semiconductor device of the above aspect, the P-type semiconductor layer may contain magnesium (Mg) as a P-type impurity.

(8) In the semiconductor device of the above aspect, the P-type semiconductor layer may cover an upper surface of the convex portion.

(9) The semiconductor device of the above aspect may further include a second N-type semiconductor layer formed on the P-type semiconductor layer and formed of a hexagonal semiconductor.

(10) In the semiconductor device of the above aspect, the impurity concentration of the second N-type semiconductor layer may be higher than the impurity concentration of the first N-type semiconductor layer.

(11) In the semiconductor device of the above aspect, the impurity contained in the first N-type semiconductor layer and the second N-type semiconductor layer may be silicon.

(12) In the semiconductor device of the above aspect, the thickness of the convex portion may be larger than the thickness of the P-type semiconductor layer on the upper surface of the convex portion.

(13) In the semiconductor device of the above aspect, the impurity concentration of the P-type semiconductor layer may be higher than the impurity concentration of the first N-type semiconductor layer.

(14) In the semiconductor device of the above aspect, the thickness of the first N-type semiconductor layer excluding the convex portion may be 10 μm or more and less than 20 μm.

(15) The semiconductor device of the above aspect may further include a third N-type semiconductor layer formed of a hexagonal semiconductor below the first N-type semiconductor layer.

(16) In the semiconductor device of the above aspect, the first N-type semiconductor layer may be mainly formed of a nitride semiconductor containing gallium.

  A plurality of constituent elements of each aspect of the present invention described above are not indispensable, and some or all of the effects described in the present specification are to be solved to solve part or all of the above-described problems. In order to achieve the above, it is possible to appropriately change, delete, replace with another new component, and partially delete the limited contents of some of the plurality of components. In order to solve part or all of the above-described problems or to achieve part or all of the effects described in this specification, technical features included in one embodiment of the present invention described above. A part or all of the technical features included in the other aspects of the present invention described above may be combined to form an independent form of the present invention.

  The present invention can be realized in various forms other than the semiconductor device and the manufacturing method thereof. For example, the present invention can be realized in the form of an electrical apparatus in which the semiconductor device of the above form is incorporated, a manufacturing apparatus for manufacturing the semiconductor device of the above form, and the like.

  According to the manufacturing method of this embodiment, the N-type protrusion is formed inside the P-type semiconductor layer below the side surface of the protrusion. For this reason, the end of the depletion layer formed in the P-type semiconductor layer is moved away from the lower side of the convex side surface, and the electric field concentration on the lower side of the convex side surface can be reduced. As a result, according to the manufacturing method of this embodiment, the electric field concentration of the semiconductor device can be relaxed.

FIG. 3 is a cross-sectional view schematically showing the configuration of the semiconductor device 10 according to the first embodiment. The figure which shows typically the relationship between the groove part 184 and the convex part 122 when it sees from the + X-axis direction side. The figure explaining the reason that the effect that electric field concentration can be eased by providing the projection part 125 is acquired. FIG. 5 is a process diagram illustrating a method for manufacturing the semiconductor device 10. Process drawing which shows the formation process (process P100) of a semiconductor layer. Sectional drawing which shows the intermediate product of the semiconductor device 10 after process P105. Sectional drawing which shows the intermediate product of the semiconductor device 10 after process P110. Sectional drawing which shows the intermediate product of the semiconductor device 10 after process P115. Sectional drawing which shows the intermediate product of the semiconductor device 10 after process P120. Sectional drawing which shows the intermediate product of the semiconductor device 10 after process P125. Sectional drawing which shows the intermediate product of the semiconductor device 10 after process P130. Sectional drawing which shows the intermediate product of the semiconductor device 10 after process P135. Sectional drawing which shows the intermediate product of the semiconductor device 10 after process P140. Sectional drawing which shows the intermediate product of the semiconductor device 10 after process P145. Sectional drawing which shows the intermediate product of the semiconductor device 10 after process P150. The figure which shows the cross-sectional SCM (Scanning Capacitance Microscopy) image of the semiconductor device which used the side surface of the convex part 122 as m surface, and the semiconductor device which used the side surface of the convex part 122 as a surface. The figure which simulated the grade of the electric field concentration in the area | region t below the side surface of the convex part 122. FIG.

A. First embodiment:
A1. Configuration of the semiconductor device 10:
FIG. 1 is a cross-sectional view schematically showing the configuration of the semiconductor device 10 in the first embodiment. The semiconductor device 10 is a GaN-based semiconductor device formed using a hexagonal semiconductor. In this embodiment, the semiconductor device 10 is a trench gate type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), is used for power control, and is also called a power device. In this embodiment, gallium nitride (GaN) is used as the hexagonal semiconductor.

  The semiconductor device 10 includes a substrate 110, an N-type semiconductor layer 120, a P-type semiconductor layer 130, an N-type semiconductor layer 140, electrodes 210, 230, 240, 250, and an insulating film 340. The semiconductor device 10 is an NPN-type semiconductor device, and has a structure in which an N-type semiconductor layer 120, a P-type semiconductor layer 130, and an N-type semiconductor layer 140 are joined in order. The “substrate 110” is also referred to as the “semiconductor substrate 110”, the “N-type semiconductor layer 120” is also referred to as the “first N-type semiconductor layer 120”, and the “N-type semiconductor layer 140” is referred to as the “second semiconductor layer 110”. Also referred to as “N-type semiconductor layer 140”.

  The N-type semiconductor layer 120, the P-type semiconductor layer 130, and the N-type semiconductor layer 140 of the semiconductor device 10 are semiconductor layers formed by crystal growth by metal organic chemical vapor deposition (MOCVD). . In the semiconductor device 10, a recess 182, a groove 184, and a recess 186 are formed by dry etching.

  FIG. 1 shows XYZ axes orthogonal to each other. Of the XYZ axes in FIG. 1, the X axis is an axis along the stacking direction in which the N-type semiconductor layer 120 is stacked on the substrate 110. Among the X-axis directions along the X-axis, the + X-axis direction is a direction from the substrate 110 toward the N-type semiconductor layer 120, and the −X-axis direction is a direction facing the + X-axis direction. Among the XYZ axes in FIG. 1, the Y axis and the Z axis are axes that are orthogonal to the X axis and orthogonal to each other. Among the Y-axis directions along the Y-axis, the + Y-axis direction is a direction from the left side to the right side in FIG. 1, and the −Y-axis direction is a direction facing the + Y-axis direction. Among the Z-axis directions along the Z-axis, the + Z-axis direction is a direction from the front side of the paper in FIG. 1 toward the back of the paper surface, and the −Z-axis direction is a direction facing the + Z-axis direction.

  The substrate 110 of the semiconductor device 10 is a semiconductor layer extending along a plane direction defined by the Y axis and the Z axis. In the present embodiment, the substrate 110 is mainly formed of gallium nitride (GaN) and contains N-type impurities such as germanium (Ge), oxygen (O), and silicon (Si) at a higher concentration than the N-type semiconductor layer 120. Contains as a donor. The “substrate 110” is disposed under the N-type semiconductor layer 120 (on the −X-axis direction side) and is also referred to as a “third N-type semiconductor layer”. Note that “mainly formed from gallium nitride (GaN)” means that 90% or more of gallium nitride (GaN) is contained in a molar fraction.

The N-type semiconductor layer 120 of the semiconductor device 10 is a semiconductor layer that is stacked on the + X axis direction side of the substrate 110 and extends along the surface direction defined by the Y axis and the Z axis. The N-type semiconductor layer 120 is mainly formed of a nitride semiconductor containing gallium (Ga). In the present embodiment, the P-type semiconductor layer 130 is mainly formed of gallium nitride (GaN). The N-type semiconductor layer 120 contains silicon (Si) as a donor. The N-type semiconductor layer 120 is also called “n ⁻ -GaN”.

  The P-type semiconductor layer 130 of the semiconductor device 10 is a semiconductor layer that is stacked on the + X-axis direction side of the N-type semiconductor layer 120 and extends along the plane direction defined by the Y-axis and the Z-axis. The P-type semiconductor layer 130 is mainly formed of a nitride semiconductor containing gallium (Ga). In the present embodiment, the P-type semiconductor layer 130 is mainly formed of gallium nitride (GaN). The P-type semiconductor layer 130 contains magnesium (Mg) as a P-type impurity. The impurity concentration of the P-type semiconductor layer 130 is higher than the impurity concentration of the N-type semiconductor layer 120. The P-type semiconductor layer 130 is also called “p-GaN”.

The N-type semiconductor layer 140 of the semiconductor device 10 is a semiconductor layer that is stacked on the + X-axis direction side of the P-type semiconductor layer 130 and extends along the surface direction defined by the Y-axis and the Z-axis. The N-type semiconductor layer 140 is mainly formed from gallium nitride (GaN). The N-type semiconductor layer 140 contains silicon (Si) as an N-type impurity. That is, the impurity contained in the N-type semiconductor layer 120 and the N-type semiconductor layer 140 is silicon (Si). The impurity concentration of the N-type semiconductor layer 140 is higher than the impurity concentration of the N-type semiconductor layer 120. The N-type semiconductor layer 140 is also referred to as “n ⁺ -GaN”.

  The recess 182 of the semiconductor device 10 is formed by dry etching, and is a portion where the P-type semiconductor layer 130 is exposed from the + X-axis direction side of the N-type semiconductor layer 140.

  The groove 184 of the semiconductor device 10 is a portion that is formed by dry etching and is recessed from the + X-axis direction side of the N-type semiconductor layer 140 through the P-type semiconductor layer 130 to the N-type semiconductor layer 120. The groove 184 is also called a trench. The groove 184 corresponds to the “groove” in “Means for Solving the Problems”. In the present embodiment, the groove 184 is located on the + Y axis direction side of the recess 182.

An insulating film 340 is formed on the surface of the trench 184 so as to reach the + X-axis direction side of the N-type semiconductor layer 140. In the present embodiment, the insulating film 340 is made of silicon dioxide (SiO ₂ ).

  The recess 186 of the semiconductor device 10 is a portion that is formed by dry etching and is recessed from the + X-axis direction side of the N-type semiconductor layer 140 through the P-type semiconductor layer 130 to the N-type semiconductor layer 120. The recess 186 is a region provided for separating the semiconductor elements. In the present embodiment, the recess 186 is located on the −Y axis direction side of the groove 184.

  The electrode 210 of the semiconductor device 10 is a drain electrode formed on the −X axis direction side of the substrate 110. In the present embodiment, the electrode 210 is formed by stacking a layer formed of aluminum (Al) on a layer formed of titanium (Ti) and then firing.

  The electrode 230 of the semiconductor device 10 is a body electrode formed on the P-type semiconductor layer 130 exposed inside the recess 182. In the present embodiment, the electrode 230 is formed by stacking layers formed from palladium (Pd) and then firing.

  The electrode 240 of the semiconductor device 10 is a source electrode formed on the + X-axis direction side of the N-type semiconductor layer 140 between the recess 182 and the groove 184. In the present embodiment, the electrode 240 is formed by laminating a layer formed of aluminum (Al) on a layer formed of titanium (Ti) and then firing.

  The electrode 250 of the semiconductor device 10 is a gate electrode formed on the insulating film 340 in the trench 184. In this embodiment, the electrode 250 is formed from aluminum (Al).

  The N-type semiconductor layer 120 includes a convex part 122 formed so as to cover the periphery of the groove part 184. In the present embodiment, the P-type semiconductor layer 130 covers the upper surface of the convex portion 122. The thickness of the convex part 122 is larger than the thickness of the P-type semiconductor layer 130 on the upper surface of the convex part 122. In the present embodiment, the thickness of the N-type semiconductor layer 120 excluding the convex portion 122 is 10 μm or more and less than 20 μm.

  FIG. 2 is a diagram schematically showing the relationship between the groove 184 and the convex part 122 when viewed from the + X-axis direction side. As shown in FIG. 2, the groove 184 is formed so that the bottom surface of the groove 184 draws a hexagon. The side surfaces of the convex portion 122 are all {11-20} planes (including equivalent planes) (hereinafter also referred to as “a plane”). As shown in FIG. 1, the protrusion 122 includes an N-type protrusion 125 inside the P-type semiconductor layer 130 below the side surface. By providing the protrusion 125, the end of the depletion layer inside the P-type semiconductor layer 130 is moved away from the lower side of the side surface of the convex portion 122, and the electric field concentration on the lower side surface of the convex portion 122 can be reduced.

  FIG. 3 is a diagram for explaining the reason why the provision of the projecting portion 125 can provide the effect of reducing the electric field concentration. FIG. 3A is a cross-sectional view schematically showing a semiconductor device 10b that does not include the protrusion 122 and the protrusion 125. FIG. The semiconductor device 10b is different from the semiconductor device 10 in that it does not include the convex portion 122 and the protruding portion 125, but is otherwise the same. In the semiconductor device 10b, the electric field concentrates in the region s that is the region below the side surface of the insulating film 340.

  FIG. 3B is a cross-sectional view schematically showing a semiconductor device 10 c that does not include the protruding portion 125. The semiconductor device 10c is different from the semiconductor device 10 in that the protrusion 125 is not provided, but is otherwise the same. In the semiconductor device 10 c, the electric field concentrates in the region s that is a region below the side surface of the insulating film 340 and the region t that is a region below the side surface of the convex portion 122. That is, since the electric field is not concentrated only in one region, the electric field concentration is reduced as compared with the semiconductor device 10b. However, since the electric field is concentrated in the region t as compared with the region s, it is not sufficient as a method for reducing the electric field concentration.

  FIG. 3C is a cross-sectional view schematically showing the semiconductor device 10 according to this embodiment. In the semiconductor device 10, the electric field concentrates in a region s that is a region below the side surface of the insulating film 340 and a region t that is a region below the side surface of the protrusion 122. However, an N-type protrusion 125 is provided inside the P-type semiconductor layer 130 in a region t that is a region below the side surface of the convex portion 122. By providing the protrusion 125, the end of the depletion layer inside the P-type semiconductor layer 130 is moved away from the lower side of the side surface of the convex portion 122, and the electric field concentration on the lower side surface of the convex portion 122 can be reduced. As a result, the electric field concentration of the semiconductor device 10 can be relaxed.

A2. Manufacturing method of the semiconductor device 10:
FIG. 4 is a process diagram showing a method for manufacturing the semiconductor device 10. When manufacturing the semiconductor device 10, the manufacturer first forms the N-type semiconductor layer 120, the P-type semiconductor layer 130, and the N-type semiconductor layer 140 in this order on the substrate 110 (step P100). As a result, the manufacturer obtains an intermediate product of the semiconductor device 10 in which each semiconductor layer is formed on the substrate 110. That is, the manufacturer prepares an intermediate product of the semiconductor device 10 through the process P100. Note that the intermediate product refers to a semiconductor device in the manufacturing process. Process P100 includes processes P105 to P150.

  FIG. 5 is a process diagram showing a semiconductor layer forming process (process P100). Step P105 is a step of forming the N-type semiconductor layer 120.

FIG. 6 is a cross-sectional view showing an intermediate product of the semiconductor device 10 after the process P105. In this embodiment, the manufacturer introduces the substrate 110 into a MOCVD furnace and heats the substrate 110 to a temperature at which the N-type semiconductor layer 120 is grown (for example, 1050 ° C.). The MOCVD furnace has an atmosphere of hydrogen (H) as a carrier gas and ammonia (NH ₃ ) as a group V element. Thereafter, the manufacturer introduces trimethylgallium (TMGa) as a group III material and silane (SiH4) as an N-type impurity into the furnace, and forms an N-type semiconductor layer 120 with a donor concentration of about 1 × 10 ¹⁶ cm ⁻³ by about 15 μm. Grow. At this time, the ratio of the Group III material to the Group V material (Group V material / Group III material) is, for example, 900 to 3000.

FIG. 7 is a cross-sectional view showing an intermediate product of the semiconductor device 10 after the process P110. Step P110 is a step of forming a protective layer 810 (see FIG. 5). In the present embodiment, the manufacturer forms a silicon dioxide (SiO ₂ ) protective layer 810 on the N-type semiconductor layer 120 with a plasma CVD (Chemical Vapor Deposition) apparatus to a thickness of about 500 nm.

  FIG. 8 is a cross-sectional view showing an intermediate product of the semiconductor device 10 after the process P115. Step P115 is a step of forming a resist pattern 820 (see FIG. 5). In this embodiment, the manufacturer applies a resist on the protective layer 810. Thereafter, the manufacturer forms a hexagonal resist pattern 820 having the side a as the side.

  FIG. 9 is a cross-sectional view showing an intermediate product of the semiconductor device 10 after the process P120. Step P120 is a step of performing dry etching of the protective layer 810 (see FIG. 5). In this embodiment, the manufacturer dry-etches the protective layer 810 at the opening of the resist by performing reactive ion etching (RIE) using the resist as a mask.

  FIG. 10 is a cross-sectional view showing an intermediate product of the semiconductor device 10 after the process P125. Step P125 is a step of performing dry etching of the N-type semiconductor layer 120 (see FIG. 5). In this embodiment, first, the manufacturer removes the resist pattern 820 by immersing the intermediate product of the semiconductor device 10 in a stripping solution. Then, the manufacturer dry-etches the N-type semiconductor layer 120 by about 1 μm using a dry etching apparatus employing an inductively coupled plasma (ICP). By the process P125, the convex part 122 whose side surface is the a-plane is formed in the N-type semiconductor layer 120. The thickness A of the convex portion 122 (see FIG. 10) is about 1 μm. “Process P125” is a process of forming the convex portion 122 having the a-plane as a side surface in the N-type semiconductor layer 120, and is also referred to as “first process”.

  FIG. 11 is a cross-sectional view showing an intermediate product of the semiconductor device 10 after the process P130. Step P130 is a step of performing wet etching of the protective layer 810 (see FIG. 5). In the present embodiment, the manufacturer performs wet etching of the protective layer 810 by immersing the intermediate product of the semiconductor device 10 in buffered hydrofluoric acid (BHF).

FIG. 12 is a cross-sectional view showing an intermediate product of the semiconductor device 10 after the process P135. Step P135 is a step of forming a protective layer 830 on the back surface of the substrate 110 (see FIG. 5). In this embodiment, the manufacturer forms a protective layer 830 of silicon dioxide (SiO ₂ ) on the back surface of the substrate 110 as a protective layer 830 with a thickness of about 300 nm.

  Step P137 is a step of immersing in TMAH (Tetramethylammonium hydroxide) (see FIG. 5). In Step P137, the manufacturer removes damage that the intermediate product of the semiconductor device 10 has been subjected to dry etching by immersing the intermediate product of the semiconductor device 10 in TMAH for about 30 minutes.

  FIG. 13 is a cross-sectional view showing an intermediate product of the semiconductor device 10 after the process P140. Step P140 is a step of performing wet etching of the protective layer 830 (see FIG. 5). In this embodiment, the manufacturer removes the protective layer 830 by immersing the intermediate product of the semiconductor device 10 in buffered hydrofluoric acid (BHF).

FIG. 14 is a cross-sectional view showing an intermediate product of the semiconductor device 10 after the process P145. Step P145 is a step of forming the P-type semiconductor layer 130 (see FIG. 5). Step P145 is performed by the MOCVD method. In this embodiment, the manufacturer introduces the intermediate product of the semiconductor device 10 into the MOCVD furnace and heats it to a temperature at which the P-type semiconductor layer 130 is grown (for example, 1050 ° C.). The MOCVD furnace has an atmosphere of hydrogen (H) as a carrier gas and ammonia (NH ₃ ) as a group V element. Thereafter, the manufacturer introduces trimethylgallium (TMGa) as a Group III raw material and biscyclopentadienyl magnesium (Cp ₂ Mg) as a P-type impurity into the furnace, and a magnesium (Mg) concentration of 4 A P-type semiconductor layer 130 of about × 10 ¹⁸ cm ⁻³ is grown so that the thickness of the upper surface of the protrusion 122 is about 0.7 μm. At this time, it becomes thicker on the side of the convex portion 122 than the thickness of the upper surface of the convex portion 122. The ratio of the Group III material to the Group V material (Group V material / Group III material) during the growth of the P-type semiconductor layer 130 is, for example, 900 to 3000. Step P145 is a step of forming the P-type semiconductor layer 130 on the N-type semiconductor layer 120. The process P145 is a process in which the protrusion 125 is formed by setting the side surface of the convex part 122 to the a-plane in the process P125. “Process P145” is also referred to as “second process”. The first process (process P125) and the second process (process P145) are performed by different apparatuses.

FIG. 15 is a cross-sectional view showing an intermediate product of the semiconductor device 10 after the process P150. Step P150 is a step of forming the N-type semiconductor layer 140 (see FIG. 5). In the present embodiment, the manufacturer introduces trimethylgallium (TMGa) as a group III material and silane (SiH4) as an N-type impurity into the furnace, and an N-type semiconductor layer 140 having a donor concentration of about 1 × 10 ¹⁸ cm ^−3. For about 0.2 μm. At this time, the ratio of the Group III material to the Group V material (Group V material / Group III material) is, for example, 900 to 3000. Through the above steps, the N-type semiconductor layer 120, the P-type semiconductor layer 130, and the N-type semiconductor layer 140 are formed in this order on the substrate 110 (step P100).

  After the process P100, the manufacturer divides the intermediate product of the semiconductor device 10 into a recess 182 reaching from the N-type semiconductor layer 140 to the P-type semiconductor layer 130, and a recess 186 reaching from the N-type semiconductor layer 140 to the N-type semiconductor layer 120. (Step P215 (see FIG. 4)). As a method for forming the recess 182 and the recess 186, an insulating film serving as a mask is first laminated and then patterned with a photoresist. Thereafter, the manufacturer forms the recess 182 and the recess 186 by performing etching. In this embodiment, dry etching is employed as the etching. Note that wet etching may be performed after dry etching in order to remove a damaged layer by etching.

  Next, in order to form a groove 184 that penetrates the P-type semiconductor layer 130 and reaches the N-type semiconductor layer 120 in the intermediate product of the semiconductor device 10, first, the manufacturer firstly surfaces the intermediate product (surface in the + X direction). ) Is laminated with an insulating film serving as a mask, and then patterned with a photoresist 400 (process P220).

  Next, the manufacturer etches the insulating film along the pattern of the photoresist 400, and then peels off the photoresist 400 (process P225). As an etching method, at least one of dry etching or wet etching can be employed.

Thereafter, the manufacturer forms the groove 184 by performing dry etching (process P230). As the dry etching conditions in the present embodiment, for example, a plasma generation power is 100 W, a bias power is 45 W, and a SiCl ₄ / Cl ₂ gas flow rate ratio is 0.1. The present invention is not limited to this condition. For example, Cl ₂ and BCl ₃ may be used as the etching gas.

  Next, the manufacturer deposits an insulating film 340 on the entire surface of the intermediate product of the semiconductor device 10 and forms contact holes in the portions where the electrodes 230 and 240 are formed. Thereafter, the manufacturer forms the electrode 230 and the electrode 240 (process P240).

  After the electrodes 230 and 240 are formed, the manufacturer performs a heat treatment to reduce the contact resistance of each electrode (process P245). Thereafter, the manufacturer forms the electrode 250 in the groove 184 in which the insulating film 340 is stacked (process P250).

  Finally, the manufacturer forms the electrode 210 on the −X side of the intermediate product of the semiconductor device 10 (process P255). Through these steps, the semiconductor device 10 shown in FIG. 1 is completed.

B. Performance evaluation:
FIG. 16 illustrates a semiconductor device in which the side surface of the convex portion 122 is a {1-100} plane (including an equivalent surface) (hereinafter also referred to as “m plane”), and a semiconductor in which the side surface of the convex portion 122 is an a plane. It is a figure which shows the cross-sectional SCM (Scanning Capacitance Microscopy) image with an apparatus. A semiconductor device in which the side surface of the convex portion 122 is a-plane was manufactured by the above manufacturing method. The semiconductor device in which the side surface of the convex portion 122 was an m-plane was manufactured by the same manufacturing method as the above manufacturing method except that the side surface of the convex portion 122 was an m-plane.

  In the cross-sectional SCM image of the semiconductor device, the white portion indicates the N-type semiconductor layer and the black portion indicates the P-type semiconductor layer. In order to facilitate understanding, FIG. 16 further shows an outline of the sample structure. From the results shown in FIG. 16, the protrusion 125 is not formed in the semiconductor device in which the side surface of the protrusion 122 is an m-plane, whereas the protrusion 125 in the semiconductor device in which the side surface of the protrusion 122 is an a-plane. It can be seen that is formed. The protruding portion 125 protrudes from the lower side of the side surface of the convex portion 122, has a long side of 0.5 μm to 1 μm, and extends linearly, for example. Although this mechanism is unknown, the inventors have discovered that this phenomenon occurs.

  FIG. 17 is a diagram simulating the degree of electric field concentration in a region t that is a region below the side surface of the convex portion 122. FIG. 17A is a diagram illustrating a semiconductor device including the protrusion 125 on the protrusion 122, and FIG. 17B is a diagram illustrating a semiconductor device not including the protrusion 125 on the protrusion 122. This simulation assumes that a voltage of 500 V is applied. A line indicated by a bold line indicates a PN junction interface, a line indicated by a white line indicates a P-side depletion layer end, and other lines indicate equipotential lines.

  As shown in FIG. 17B, the interval between equipotential lines in the region t in the case where the protrusions 125 are not provided is narrower than in other regions. However, compared to the equipotential line interval in the region t without the protrusion 125 (see FIG. 17B), the equipotential line interval in the region t with the protrusion 125 (see FIG. 17B). A) see) is wide. From this result, it can be seen that the electric field concentration is reduced in the semiconductor device including the protrusion 125 compared to the semiconductor device not including the protrusion 125.

C. Variations:
The present invention is not limited to the above-described embodiment, and can be implemented in various forms without departing from the gist thereof. For example, the following modifications are possible.

C1. Modification 1:
In this embodiment, silicon (Si) is used as a donor contained in at least one of the substrate and the N-type semiconductor layer, but the present invention is not limited to this. As the donor, germanium (Ge) or oxygen (O) may be used.

C2. Modification 2:
In this embodiment, magnesium (Mg) is used as an acceptor included in the P-type semiconductor layer, but the present invention is not limited to this. As the acceptor, zinc (Zn) or carbon (C) may be used.

C3. Modification 3:
In this embodiment, gallium nitride which is a hexagonal semiconductor is used as the semiconductor. However, the present invention is not limited to this. As the semiconductor, other hexagonal semiconductors may be used.

C4. Modification 4:
In this embodiment, the electrode 230 which is a body electrode is formed from palladium (Pd). However, the present invention is not limited to this. The electrode 230 may be formed of other materials, and may have a multilayer structure. For example, the electrode 230 may be an electrode including at least one of conductive materials such as nickel (Ni), platinum (Pt), and cobalt (Co), a nickel (Ni) / palladium (Pd) configuration, A two-layer configuration such as a platinum (Pt) / palladium (Pd) configuration (palladium is on the semiconductor substrate side) may be used.

C5. Modification 5:
In this embodiment, the electrode 250 which is a gate electrode is formed from aluminum (Al). However, the present invention is not limited to this. The electrode 250 may be made of polysilicon. Further, the electrode 250 may be formed of other materials, and may have a multi-layer configuration. For example, the electrode 250 may have a gold (Au) / nickel (Ni) configuration, an aluminum (Al) / titanium (Ti) configuration, or an aluminum (Al) / titanium nitride (TiN) configuration (nickel, titanium, and titanium nitride, respectively). A two-layer structure such as a gate insulating film side) or a three-layer structure such as a titanium nitride (TiN) / aluminum (Al) / titanium nitride (TiN) structure may be used.

C6. Modification 6:
In the present embodiment, the semiconductor device 10 uses a MOSFET. However, the present invention is not limited to this. That is, the semiconductor device 10 may be a semiconductor. Examples of the semiconductor other than the MOSFET include a semiconductor having a trench gate such as an IGBT (Insulated Gate Bipolar Transistor).

  The present invention is not limited to the above-described embodiments and modifications, and can be realized with various configurations without departing from the spirit thereof. For example, the technical features in the embodiments and the modifications corresponding to the technical features in each embodiment described in the summary section of the invention are to solve some or all of the above-described problems, or In order to achieve part or all of the effects, replacement or combination can be performed as appropriate. Further, if the technical feature is not described as essential in the present specification, it can be deleted as appropriate.

DESCRIPTION OF SYMBOLS 10 ... Semiconductor device 10b ... Semiconductor device 10c ... Semiconductor device 110 ... Substrate 120 ... N type semiconductor layer 122 ... Convex part 125 ... Protrusion part 130 ... P type semiconductor layer 140 ... N type semiconductor layer 182 ... Concave part 184 ... Groove part 186 ... Concave part 210 ... Electrode 230 ... Electrode 240 ... Electrode 250 ... Electrode 300 ... Insulating film 400 ... Photoresist 810 ... Protective layer 820 ... Resist pattern 830 ... Protective layer s ... Region t ... Region

Claims (13)

A trench gate type semiconductor device,
A first N-type semiconductor layer formed of a hexagonal semiconductor;
A P-type semiconductor layer stacked on the first N-type semiconductor layer and formed of a hexagonal semiconductor;
A groove portion penetrating through the P-type semiconductor layer to reach the first N-type semiconductor layer,
The first N-type semiconductor layer includes a convex portion formed so as to cover the periphery of the groove portion,
A side surface of the convex portion is a {11-20} plane (including an equivalent plane),
The convex part is provided with a protruding part below the side surface ,
The trench is provided with a gate electrode through an insulating film,
Semiconductor device. The semiconductor device according to claim 1 ,
The P-type semiconductor layer is a semiconductor device mainly formed of a nitride semiconductor containing gallium. The semiconductor device according to claim 1 or 2 , wherein
The semiconductor device, wherein the P-type semiconductor layer is mainly formed of gallium nitride. The semiconductor device according to any one of claims 1 to 3,
The P-type semiconductor layer contains magnesium (Mg) as a P-type impurity. The semiconductor device according to any one of claims 1 to 4,
The semiconductor device, wherein the P-type semiconductor layer covers an upper surface of the convex portion. The semiconductor device according to any one of claims 1 to 5, further
A semiconductor device comprising a second N-type semiconductor layer stacked on the P-type semiconductor layer and formed of a hexagonal semiconductor. The semiconductor device according to claim 6 ,
The semiconductor device, wherein an impurity concentration of the second N-type semiconductor layer is higher than an impurity concentration of the first N-type semiconductor layer. The semiconductor device according to claim 6 or 7 , wherein
The semiconductor device, wherein the impurity contained in the first N-type semiconductor layer and the second N-type semiconductor layer is silicon. The semiconductor device according to any one of claims 1 to 8,
The thickness of the said convex part is a semiconductor device larger than the thickness of the said P-type semiconductor layer in the upper surface of the said convex part. The semiconductor device according to any one of claims 1 to 9,
The semiconductor device, wherein an impurity concentration of the P-type semiconductor layer is higher than an impurity concentration of the first N-type semiconductor layer. The semiconductor device according to any one of claims 1 to 1 0,
The thickness of the 1st N type semiconductor layer except the convex part is a semiconductor device which is 10 micrometers or more and is less than 20 micrometers. The semiconductor device according to any one of claims 1 to 1 1, further
A semiconductor device comprising a third N-type semiconductor layer formed of a hexagonal semiconductor under the first N-type semiconductor layer. The semiconductor device according to any one of claims 1 to 1 2,
The first N-type semiconductor layer is a semiconductor device mainly formed of a nitride semiconductor containing gallium.

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