JP5158470B2 - Manufacturing method of nitride semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a nitride semiconductor device , and more particularly to a method for manufacturing a nitride semiconductor device including an electrode for a channel in which a carrier formed in a heterojunction structure travels .

  GaN, which is a nitride semiconductor material having a large band gap, has features such as a high breakdown voltage and a high saturation drift speed. Therefore, if a GaN material is used, the resistance can be reduced without sacrificing the withstand voltage characteristics as compared with a silicon-based electronic device. Further, since it is chemically stable and thus stable at a high temperature, it can be used as a material for an electronic device that requires high output.

  GaN used for electronic devices is a wurtzite crystal belonging to the hexagonal system capable of high-quality crystal growth, and has polarization in the c-axis direction of the crystal orientation. Therefore, if a heterojunction structure such as an AlGaN / GaN junction is formed in parallel to the c-plane, a positive space fixed charge can be generated at the heterojunction interface due to the piezoelectric effect. By utilizing this, a two-dimensional electron gas can be formed at the heterojunction interface.

  Therefore, in a transistor or the like, an AlGaN / GaN heterojunction or an InAlN / GaN heterojunction formed in parallel with the c-plane is used to form a channel portion in which carriers travel, that is, in this case, an electron travels. . In order to reduce the resistance of an electronic device such as a transistor using this channel, it is necessary to attach an electrode having a low contact resistance to the channel formed in the heterojunction.

  An electronic device using a channel formed in a heterojunction mainly manufactured at present is an AlGaN / GaN heterojunction field effect transistor. This transistor is manufactured as follows. As a layer structure, about 2 to 3 μm of non-doped GaN is grown on a substrate, and an AlGaN barrier layer is grown on it to about 20 to 40 nm. The AlGaN barrier layer is n-type doped to reduce ohmic resistance. The source electrode and the drain electrode are formed on the AlGaN barrier layer using a metal such as Ti / Al / Au. A metal such as Ni / Au or Pt is used for the gate electrode.

  In such a source or drain structure, an AlGaN barrier layer exists between the electrode metal and the channel. Since nitride semiconductors such as AlGaN are chemically stable, they are not alloyed with electrode materials. Thus, current is injected into or extracted from the channel through the AlGaN barrier layer.

  In this case, the barrier whose height is determined by the work function of the drain or source metal and the work function or band gap of the AlGaN barrier layer is between the AlGaN barrier layer and the metal. Also, the crystal quality is poor and current must flow through the high resistance AlGaN barrier layer. As a result, it is difficult to reduce the contact resistance of the electrode.

  There is also a method in which the AlGaN barrier layer is removed and the electrode is brought into direct contact with the channel. The portion where the drain and source electrode structures are formed is removed by dry etching or the like deeper than the thickness of the AlGaN barrier layer. Then, an electrode is formed so as to be in contact with the side surface of the appearing AlGaN / GaN heterojunction portion. In this case, since the current can be injected without passing through the AlGaN barrier layer, the contact resistance of the electrode can be lowered.

  However, damage due to dry etching or surface oxidation occurs. In dry etching, reattachment to the side surface occurs. Further, the metal of the electrode does not always adhere to the side surface. Therefore, there is a problem in reproducibility.

  Therefore, the problem to be solved by the present invention is to form an electrode with good reproducibility and low contact resistance in a channel on which a carrier formed in a heterojunction structure travels.

The above challenges are understood determined by the providing a method for manufacturing a following nitride semiconductor devices.
(1) A method of manufacturing a nitride semiconductor device comprising a first nitride semiconductor in which a channel in which carriers travel is formed and a second nitride semiconductor that forms a heterojunction with the first nitride semiconductor. A plurality of different electrode metal particles are sequentially discharged from the crucible by an electron beam evaporation method, and the particle metal electrode is discharged from the surface of the second nitride semiconductor to the second nitride semiconductor. In order to reach the region where the channel is formed in the first nitride semiconductor, the plurality of different electrode metals are stacked, and the plurality of holes An electrode forming step of forming an electrode structure in contact with the channel on the side surface on the surface of the second nitride semiconductor, and an electric power obtained by laminating the plurality of different electrode metals formed by the electrode forming step. The method for manufacturing a nitride semiconductor device which comprises a annealing step of annealing for the structure to function as one electrode as a whole alloyed.
(2) The second nitride semiconductor is characterized in that the thickness of the position where the electrode structure is formed by the electrode forming step is made thinner than the thickness of the position where the electrode structure is not formed. The manufacturing method of the nitride semiconductor device as described in (1).

  According to the present invention, in a nitride semiconductor device using a channel formed in a heterojunction structure, the contact resistance of an electrode can be reduced and a low loss operation can be performed.

  The nitride semiconductor material that can be used in the present invention is a semiconductor containing nitrogen composed of a group III element and a group V element. The main crystal structure is a wurtzite crystal belonging to the hexagonal system capable of high-quality crystal growth, and has polarization in the c-axis direction of the crystal orientation.

  A crystal composed of two elements such as GaN is suitable for the channel portion where the carrier travels. This is because a mixed crystal of three elements such as AlGaN, InGaN, and InAlN, and further a mixed crystal of four elements has a large alloy scattering resulting from the nonuniform composition. However, since the effective mass of electrons can be reduced for In, in the case of InGaN and InAlN, improvement in mobility can be expected.

  Further, the channel structure generally used in the FET at present is a single heterostructure such as an AlGaN / GaN heterojunction. However, it can also be used for double heterostructures such as AlGaN / GaN / AlGaN and InAlN / GaN / InAlN. Currently, the n-type channel on which electrons travel is mainly used, but a p-type channel on which holes travel can also be used.

Hereinafter, the present invention will be described in detail by way of examples used for AlGaN / GaN heterojunction field effect transistors.
Example 1
FIG. 1 shows the structure of an AlGaN / GaN heterojunction field effect transistor using an electrode structure according to the present invention. As the crystal substrate 1, a sapphire substrate, a SiC substrate, a silicon substrate, a GaN substrate, or the like is used. For crystal growth, MOCVD may be used. After forming a structure for improving crystallinity such as the low temperature growth GaN buffer layer 2 from the substrate side, the high resistance GaN layer 3 is first grown.

  Thereafter, an AlGaN barrier layer 4 is grown. The channel is formed on the high resistance GaN layer 3 side of the heterojunction surface of the high resistance GaN layer 3 and the AlGaN barrier layer 4. The AlGaN barrier layer 4 is partly or wholly n-type doped as necessary.

  Next, a mesa structure is formed in order to electrically isolate the elements. Using a photoresist, a rectangular photoresist mesa pattern of 20 μm in the direction in which the source electrode 10, gate electrode 11, and drain electrode 12 are arranged and 50 μm in the gate width direction is formed. The width and length of the mesa may be changed as necessary. The width of the gate electrode 11 and the width of the mesa are the same.

  As a method for producing a photoresist pattern, an exposure method using a commonly used stepper may be used. Thereafter, the grown substrate is processed into a mesa pattern by dry etching using a photoresist in the shape of a mesa as a mask.

  The dry etching is performed using, for example, chlorine plasma using an electron cyclotron resonance (ECR) method. Dry etching has an etching direction as compared with wet etching, and the etching rate is easily controlled. The etching rate varies depending on the crystal quality of the epitaxial film, the pressure of chlorine plasma, acceleration energy (plasma extraction voltage), etc., but is 200 to 300 nm per hour. Etching is performed to about 100 nm to remove the AlGaN layer and the like other than the mesa.

  By forming the mesa, the elements on the same substrate are separated from each other, so that no current flows between the elements. The element isolation can be performed not only by dry etching using a chlorine-based gas but also by ion implantation. By isolating nitrogen ions or the like at a high speed, the elements may be electrically isolated from each other.

  After the mesa etching, an insulating film is formed in a portion other than the mesa. As the insulating film, a silicon oxide film, a silicon nitride film, or the like can be used. For example, after an insulating film is formed on the entire wafer surface with a thickness of about 100 nm by using plasma CVD or the like, portions other than the mesa are covered with a photoresist, and only the insulating film on the mesa is removed by etching. Pay attention to the part where the gate electrode 11 is located at the edge of the mesa. When the gate electrode 11 is in contact with the channel of the AlGaN / GaN heterojunction portion on the side surface of the mesa, the gate leakage current increases, so that the mesa side surface is also covered with the insulating film.

  Thereafter, the source electrode 10 and the drain electrode 12 are formed. As the electrode metal of the source electrode 10 and the drain electrode 12, a Ti / Al / Ni / Au (30/220/40/50 nm) structure or the like is used from the substrate surface side.

  One of the methods for forming the electrode structure of the present invention is a method using an electron beam evaporation method. In the electron beam evaporation method, a metal source contained in a crucible is heated by an electron beam and evaporated. By controlling the deposition conditions such as the diameter of the electron beam that hits the metal source in the crucible and the amount of current of the electron beam, that is, the deposition rate, relatively large particles of metal are emitted from the crucible and fly toward the substrate surface. be able to.

  In the present invention, in electron beam evaporation, a metal material is directly filled into a hearth liner made of copper so as to be cooled well. For this reason, only a part is heated by the electron beam.

  In this way, the metal jumping out of the crucible becomes particles having a diameter of several tens of nanometers or more. When the metal reaches the substrate surface and the kinetic energy is large, a hole penetrating through the thin AlGaN barrier layer is formed and stopped. As a result, an electrode structure is formed through the small hole from the surface and contacting the channel at the side of the hole.

  In FIG. 1, the holes are opened at equal intervals, but it is not always necessary to do so. It is better to make small holes with high density. Actually, holes having a diameter of several hundreds of nm or less may be present at intervals similar to the diameter at intervals of submicron or less.

When the method of the present invention is not used, a contact resistance of about 10 ⁻⁵ Ωcm ² is obtained at present. Unless a small contact resistance smaller than this is obtained by the present invention, it cannot be said to be effective. From this, it can be examined how much the hole density is necessary.

Assume that an electrode having a contact resistance of about 10 ⁻⁵ Ωcm ² is attached to a channel having a sheet resistance of 500 to 600Ω. Since the current that has passed through the channel has contact resistance, not all current immediately enters the electrode from the channel, but rather enters the electrode metal after passing through the channel below the electrode to some extent. According to the TLM (Transmission Line Model) method or the like, when the sheet resistance is 500 to 600Ω with a contact resistance of 10 ⁻⁵ Ωcm ² , the current passes through the channel under the electrode at a distance of about 1 to 2 μm.

  Therefore, even in the method of the present invention, if the distance between the holes is less than this distance, the effect is almost the same as that of a normal electrode. In view of this, in order for the present invention to be effective, the holes need to exist at submicron intervals.

  After the electron beam evaporation, the metal other than the source and drain portions is removed by a lift-off method. Acetone may be used as the lift-off solution. Thereafter, annealing is performed for alloying the electrode metal. Annealing is performed at 800 ° C. for 30 seconds using a high-speed lamp annealing method (RTA).

  Thereafter, the gate electrode 11 is formed. Photolithography is used for patterning the gate, but when the gate length is short and a fine pattern is used, electron beam lithography is used. For example, when the gate length is 200 nm or less, an electron beam lithography method is used. As the gate electrode metal, Ni / Au (50/200 nm) is used from the substrate surface side. A high vacuum electron beam evaporation method may be used to form the gate metal. In this case, the evaporation source is heated by an electron beam and thermally evaporated.

  Although not shown in FIG. 1, a silicon nitride film or a silicon oxide film is formed on the element surface such as the surface between the source and drain by plasma CVD or the like in order to reduce current collapse and improve breakdown voltage. To do.

  FIG. 2 shows the results of measuring the on-resistance of the element having the source and drain electrodes formed by the method of the present invention in Example 1. The channel resistance of the used wafer is 540Ω to 600Ω. This figure shows the on-resistance as a function of drain-source spacing. The gate length is 0.6 to 5 μm, and the gate width is 50 μm. The on-resistance is obtained from the magnitude of the drain current when the gate voltage is 0V and the drain voltage is 1V.

The contact resistance of the source and drain electrodes estimated from the TLM pattern produced on the same wafer simultaneously with the production of this element was 0.8 × 10 ⁻⁶ Ωcm ² . This was an order of magnitude smaller than the conventional method of forming on the AlGaN barrier layer. The on-resistance of the actual element shown in FIG. 2 is the contact resistance between the drain and the source electrode, the sheet resistance between the drain and the gate, the resistance of the channel under the gate electrode kept at 0V, and the source resistance between the gate and the source. Is the sum of Therefore, contact resistance cannot be estimated only by comparing on-resistance.

  However, in FIG. 2, the value of the intercept with the Y axis of the straight line connecting the measured values does not include the channel resistance between the source and the drain. Included are the contact resistance between the source and drain and the increase in resistance generated by keeping the gate voltage constant at 0V. In the device manufactured by the method of the present invention, the Y-axis intercept was 1 Ω / mm as shown in FIG.

  For comparison, FIG. 3 shows the measurement results of a device in which the source and drain electrodes were made such that the AlGaN barrier layer was removed and the channel was in contact with the side surface. The on-resistance measurement method is the same as in FIG. A wafer having a sheet resistance of 500Ω was used for making this device.

  As shown in FIG. 3, the Y-axis intercept was 1.3 Ω / mm. The elements whose results are shown in FIGS. 2 and 3 use the same photomask and have the same structure except for the electrodes. Also, the sheet resistance is lower in the element shown in FIG. The only structural difference is the electrode structure. Therefore, the result shown in FIG. 2 is better because the contact resistance between the source and drain electrodes is better in the method of the present invention.

  Furthermore, in FIG. 3, the on-resistance varies, and a low resistance is not stably obtained. This is considered to be because the AlGaN barrier layer is removed and the electrode is deposited so as to be in contact with the channel from the side surface, but is not necessarily in contact with the side surface. In addition, if the side surface is completely exposed, the strain of the AlGaN barrier layer is relaxed, and the carrier density at that portion may be reduced. Further, dry etching is used to remove the barrier layer, but at that time, the etched semiconductor may be reattached to the side surface.

(Example 2)
FIG. 4 shows a structure that is almost the same as that of FIG. 1, except that the AlGaN barrier layer is slightly thinned only in the portions where the source and drain electrodes are formed. In the method of the present invention, since a small hole is formed, in principle, it is simpler that the AlGaN barrier layer is thinner. In particular, when using a granular deposit during electron beam evaporation, it is difficult to reach the channel unless it is thin. Specifically, the effect was obtained in the present invention by setting the thickness to 20 nm or less.

  The structure of FIG. 4 is particularly effective when a thick AlGaN barrier layer of about 40 nm is used between the gate and the drain in order to reduce current collapse.

(Example 3)
It is also effective to arrange a plurality of holes reaching the channel at an equal distance from the electrode end toward the electrode and in an array shape in a direction perpendicular to the channel. In this case, a photoresist or the like is patterned into a desired shape by exposure using a stepper or the like, and a hole reaching the channel is formed by dry etching or the like using that as a mask for etching. When dry etching is used, there are problems of damage during etching and reattachment to the side surface, but it is possible to make the electrode resistance smaller than in the case of the normal recess ohmic shown in FIG. This is because the length in which the electrode metal contacts the channel from the side surface of the hole can be increased.

  However, when a small hole is made by dry etching, the problem of reattachment to the side surface of the hole occurs. In that case, it is preferable to connect a plurality of holes located in an array at equal distances from the electrode end toward the electrode and in a direction orthogonal to the channel at positions away from the electrode end. If it does in this way, the reattachment to the hole side surface can be reduced.

  The current flows into the channel mainly from the side surface near the electrode end of the hole. For example, in the case of a drain electrode of a transistor, it flows into the channel from an end close to the gate side of the drain electrode. Therefore, the length of the electrode metal contacting the channel can be kept long at the electrode end portion where the current mainly flows. In this case, a large hole having a wavy contour is formed in the electrode end portion, and the electrode metal is brought into contact with the side surface.

FIG. 5 shows a surface photograph in which a plurality of holes located at an equal distance from the electrode end toward the electrode and arrayed in a direction perpendicular to the channel are formed by dry etching. In FIG. 5, a plurality of holes located in the form of an array in the direction orthogonal to the channel are dry-etched at an equal distance from the electrode end to the electrode, leaving the AlGaN barrier layer only in the center, and the plurality of holes are electrically connected. Similarly, dry etching is performed so as to be connected at a position away from the extreme.
In the case of manufacturing a transistor, the drain electrode and the source electrode are formed so as to cover the plurality of corrugated hole portions. The gate electrode is located at the center. Even when this structure is used, the contact resistance can be reduced by an order of magnitude.

  It can be used for inverters and converters for household power supplies. Since the lateral element can increase the breakdown voltage with low loss, for example, it can be integrated with other electronic components, and the AC-DC converter of a household DC power source can be downsized. In addition, high-speed operation is possible, which is effective for energy saving.

It is a schematic diagram of a transistor having a source and a drain electrode that contact a channel having a double hetero structure through a small hole. This is the dependence of the on-resistance of the transistor shown in FIG. It is a measurement result of the on-resistance of the element produced by removing the AlGaN barrier layer and bringing the source and drain electrodes into contact with the channel from the side surface. FIG. 3 is a schematic diagram of a transistor in which an AlGaN barrier layer where a source and drain electrodes are formed is thinned to form an electrode structure of the present invention. It is the surface photograph which formed the hole which reaches a channel by dry etching.

Explanation of symbols

1: Substrate 2: Buffer layer 3: GaN layer 4: AlGaN barrier layer 10: Source electrode 11: Gate electrode 12: Drain electrode

Claims (2)

A method of manufacturing a nitride semiconductor device comprising: a first nitride semiconductor in which a channel on which carriers travel is formed; and a second nitride semiconductor that forms a heterojunction with the first nitride semiconductor,
A plurality of different electrode metal particles are sequentially discharged from the crucible by electron beam evaporation, and the hole is formed in the second nitride semiconductor from the surface of the second nitride semiconductor. In order to open and reach the region where the channel is formed in the first nitride semiconductor, the plurality of different electrode metals are laminated, and the side surface of the plurality of holes Forming an electrode structure in contact with the channel on the surface of the second nitride semiconductor;
An annealing process for alloying the electrode structure in which the plurality of different electrode metals formed in the electrode forming process are laminated to function as one electrode as a whole,
A method for manufacturing a nitride semiconductor device comprising : 2. The second nitride semiconductor is characterized in that the thickness of the position where the electrode structure is formed by the electrode forming step is made thinner than the thickness of the position where the electrode structure is not formed. The manufacturing method of the nitride semiconductor device of description.