JP6107597B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  As a structure of a semiconductor device (semiconductor device, semiconductor element), a trench gate structure in which a gate electrode is formed in a trench (groove) is known. Patent Documents 1 to 4 describe forming a p-type semiconductor in the vicinity of the bottom of the trench in order to alleviate the electric field concentration generated at the bottom of the trench in the trench gate structure. Thereby, the withstand voltage of the semiconductor device can be improved.

JP-A-6-224437 JP 2001-267570 A JP 2009-117593 A JP 2011-44513 A

  Since the trench gate structures of Patent Documents 1 and 2 form a p-type semiconductor in the vicinity of the bottom of the trench by ion implantation, a semiconductor that is difficult to form a p-type semiconductor by ion implantation (for example, gallium nitride (GaN There is a problem that it cannot be applied to a group III nitride semiconductor represented by (1).

  The trench gate structures of Patent Documents 3 and 4 have a problem that the manufacturing process becomes complicated because a p-type semiconductor is formed in the vicinity of the bottom of the trench by selective regrowth in which a crystal is grown in a region selected by masking. . In addition, the trench gate structure disclosed in Patent Documents 3 and 4 has a p-type semiconductor dopant already formed in an already formed n-type semiconductor layer when a p-type semiconductor is formed near the bottom of the trench by selective regrowth. Due to the diffusion of (impurities), there is a problem that the electrical characteristics of the n-type semiconductor layer that has already been formed deteriorate (for example, an increase in on-resistance). Further, the termination structure using the trench in the semiconductor device has the same problem as the trench gate structure.

  Therefore, a technique capable of improving the electrical characteristics of a semiconductor device having a trench has been desired. In addition, for semiconductor devices, miniaturization, cost reduction, resource saving, easy manufacturing, improved usability, and improved durability have been desired.

SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms.
According to one embodiment of the present invention, a semiconductor device is provided. The semiconductor device includes a first n-type semiconductor layer having a first interface and a second interface constituting a top surface of a convex portion protruding from the first interface; and the first n-type semiconductor layer The p-type semiconductor layer is a p-type semiconductor layer in which the first portion laminated at the first interface and the second portion laminated at the second interface are uniformly connected. A second n-type semiconductor layer stacked on the p-type semiconductor layer; and the convex portion of the first n-type semiconductor layer penetrating the p-type semiconductor layer from the second n-type semiconductor layer. A height Hm at which the convex portion protrudes from the first interface is a thickness Tp of the p-type semiconductor layer at the first portion, and the first portion. Less than the combined thickness Tu of the second n-type semiconductor layer Tn2. According to this embodiment, the electric field concentration in the groove can be relaxed by the p-type semiconductor layer. As a result, the electrical characteristics of the semiconductor device can be improved. Moreover, the crystal quality of each type semiconductor layer formed on the convex portion can be improved.
According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided. The method for manufacturing a semiconductor device includes a step of forming a first n-type semiconductor layer; a step of forming a convex portion on the first n-type semiconductor layer by dry etching; Forming a p-type semiconductor layer on the surface including the convex portion by crystal growth; forming a second n-type semiconductor layer on the surface of the p-type semiconductor layer by crystal growth; and forming, by dry etching, a groove portion that penetrates from the n-type semiconductor layer through the p-type semiconductor layer to the inside of the convex portion in the first n-type semiconductor layer; The step of forming includes a step of performing wet etching on the first n-type semiconductor layer after performing the dry etching. According to this embodiment, the p-type semiconductor layer can be formed so that the electric field concentration in the trench can be relaxed without using ion implantation and selective regrowth. As a result, the manufacturing cost can be suppressed. In addition, an increase in on-resistance due to diffusion of the dopant of the p-type semiconductor layer into at least one of the first n-type semiconductor layer and the second n-type semiconductor layer can be suppressed. In addition, since damage due to dry etching on the surface of the first n-type semiconductor layer can be alleviated by wet etching, crystal growth of the p-type semiconductor layer can be easily performed.

(1) According to one aspect of the present invention, a semiconductor device is provided. The semiconductor device includes a first n-type semiconductor layer having a first interface and a second interface constituting a top surface of a convex portion protruding from the first interface; and the first n-type semiconductor layer The p-type semiconductor layer is a p-type semiconductor layer in which the first portion laminated at the first interface and the second portion laminated at the second interface are uniformly connected. A second n-type semiconductor layer stacked on the p-type semiconductor layer; and the convex portion of the first n-type semiconductor layer penetrating the p-type semiconductor layer from the second n-type semiconductor layer. And a groove portion that is depressed to the inside. According to this embodiment, the electric field concentration in the groove can be relaxed by the p-type semiconductor layer. As a result, the electrical characteristics of the semiconductor device can be improved.

(2) In the semiconductor device of the above aspect, the p-type semiconductor layer may include a first raised portion that is raised along the convex portion in a protruding direction in which the convex portion protrudes. The second n-type semiconductor layer may have a second raised portion that is raised along the first raised portion in the protruding direction. According to this embodiment, the electric field concentration in the groove formed in each semiconductor layer having each raised portion can be reduced.

(3) The semiconductor device of the said form may be further equipped with the electrode formed in the said groove part via the insulating film. According to this embodiment, the electric field concentration in the groove portion where the electrode is formed via the insulating film can be relaxed.

(4) In the semiconductor device of the above aspect, the height Hm at which the protrusion protrudes from the first interface is the thickness Tp of the p-type semiconductor layer in the first part and the height in the first part. The total thickness Tu may be smaller than the total thickness Tn2 of the second n-type semiconductor layer. According to this aspect, the crystal quality of each type semiconductor layer formed on the convex portion can be improved.

(5) In the semiconductor device of the above aspect, a depth h1 at which the groove portion falls with respect to the upper surface of the convex portion is 0.0 μm or more, and a height Hm at which the convex portion protrudes from the first interface. Or less than the depth of 0.4 μm. According to this embodiment, it is possible to effectively reduce the electric field concentration in the groove while ensuring the forward current flow.

(6) In the semiconductor device of the above aspect, the height h2 from the first interface to the bottom surface of the groove along the X-axis direction from which the convex portion protrudes is from the first interface to the second It may be 1.0 μm or less on the + X-axis direction side toward the interface, and 0.4 μm or less on the −X-axis direction side from the second interface toward the first interface. According to this aspect, it is possible to effectively reduce the electric field concentration in the groove portion while suppressing an increase in the thickness of the first n-type semiconductor layer.

(7) In the semiconductor device of the above aspect, the distance w1 between the side end of the convex portion and the bottom surface of the groove portion may satisfy 0.1 μm ≦ w1 ≦ 2.0 μm. According to this embodiment, an increase in on-resistance due to the distance w1 being too close can be suppressed, and an increase in electric field concentration in the groove due to the distance w1 being too far away can be suppressed.

(8) In the semiconductor device of the above aspect, the distance w1 between the side end of the convex portion and the bottom surface of the groove portion may satisfy 0.2 μm ≦ w1 ≦ 1.0 μm. According to this embodiment, an increase in on-resistance due to the distance w1 being too close can be further suppressed, and an increase in electric field concentration in the groove due to the distance w1 being too far can be further suppressed.

(9) The semiconductor device according to the above aspect may further include a third n-type semiconductor layer stacked between the first n-type semiconductor layer and the p-type semiconductor layer. According to this embodiment, the crystal quality of the p-type semiconductor layer can be improved.

(10) The semiconductor device of the above aspect may further include an intrinsic semiconductor layer stacked between the first n-type semiconductor layer and the p-type semiconductor layer. According to this embodiment, the crystal quality of the p-type semiconductor layer can be improved.

(11) In the semiconductor device of the above aspect, the acceptor concentration in the first part may be the same as the acceptor concentration in the second part. According to this embodiment, the electric field concentration in the groove can be relaxed by the homogeneous p-type semiconductor layer from the first part to the second part.

(12) In the semiconductor device according to the above aspect, the first n-type semiconductor layer, the p-type semiconductor layer, and the second n-type semiconductor layer are semiconductor layers mainly made of gallium nitride (GaN). Also good. According to this embodiment, the withstand voltage can be improved in a GaN-based semiconductor device in which it is difficult to form a p-type semiconductor by ion implantation.

(13) In the semiconductor device according to the above aspect, the plurality of groove portions are provided, and the convex portion is at least the first interface on the end side from the groove portion located on the end side of the semiconductor device among the plurality of groove portions. You may protrude from. According to this embodiment, the electric field concentration at least in the groove located on the terminal side can be reduced.

(14) In the semiconductor device according to the above aspect, the first n-type semiconductor layer is formed from the second n-type semiconductor layer to the first n-type semiconductor layer through the p-type semiconductor layer. An insulating film that has electrical insulating properties and covers the stepped portion; and an electrode that has conductivity and is stacked on the insulating film and sandwiches the insulating film between the stepped portion and the stepped portion. You may prepare. According to this embodiment, the field plate structure including the insulating film and the electrode in the step portion can alleviate electric field concentration generated in the pn junction portion between the first n-type semiconductor layer and the p-type semiconductor layer in the step portion.

(15) In the semiconductor device according to the above aspect, a source electrode formed in a recess extending from the second n-type semiconductor layer to the p-type semiconductor layer; and a gate electrode formed in the trench through an insulating film And a part of the source electrode and the gate electrode in a cross section along the stacking direction in which the first n-type semiconductor layer, the p-type semiconductor layer, and the second n-type semiconductor layer are stacked. A part may be alternately arranged. According to this embodiment, it is possible to alleviate electrode concentration in each of the plurality of elements configured by the portions of the source electrode and the gate electrode.

(16) According to an aspect of the present invention, a method for manufacturing a semiconductor device is provided. The manufacturing method includes a step of forming a first n-type semiconductor layer; a step of forming a convex portion on the first n-type semiconductor layer by dry etching; and the convex portion in the first n-type semiconductor layer. Forming a p-type semiconductor layer by crystal growth on the surface containing the crystal; and forming a second n-type semiconductor layer by crystal growth on the surface of the p-type semiconductor layer; and the second n-type semiconductor. Forming a groove portion that penetrates from the layer through the p-type semiconductor layer to the inside of the convex portion in the first n-type semiconductor layer by dry etching. According to this embodiment, the p-type semiconductor layer can be formed so that the electric field concentration in the trench can be relaxed without using ion implantation and selective regrowth. As a result, the manufacturing cost can be suppressed. In addition, an increase in on-resistance due to diffusion of the dopant of the p-type semiconductor layer into at least one of the first n-type semiconductor layer and the second n-type semiconductor layer can be suppressed.

(17) In the method of manufacturing a semiconductor device according to the above aspect, the step of forming the convex portion may include a step of performing wet etching on the first n-type semiconductor layer after performing the dry etching. . According to this embodiment, since damage caused by dry etching on the surface of the first n-type semiconductor layer can be reduced by wet etching, crystal growth of the p-type semiconductor layer can be easily performed.

  The present invention can be realized in various forms other than the semiconductor device and the manufacturing method thereof. For example, the present invention can be realized in the form of an electrical apparatus in which the semiconductor device of the above form is incorporated, a manufacturing apparatus for manufacturing the semiconductor device of the above form, and the like.

  According to the present invention, the electric field concentration in the groove can be relaxed by the p-type semiconductor layer. As a result, the electrical characteristics of the semiconductor device can be improved.

  In addition, the p-type semiconductor layer can be formed so that the electric field concentration in the groove can be relaxed without using ion implantation and selective regrowth. As a result, the manufacturing cost of the semiconductor device can be suppressed. In addition, an increase in on-resistance due to diffusion of the dopant of the p-type semiconductor layer into at least one of the first n-type semiconductor layer and the second n-type semiconductor layer can be suppressed.

It is sectional drawing which shows typically the structure of the semiconductor device in 1st Embodiment. It is sectional drawing which shows typically the structure of the semiconductor device expanded centering on the convex part and the groove part. It is process drawing which shows the manufacturing method of a semiconductor device. It is explanatory drawing which shows the structure of the semiconductor device in the middle of manufacture. It is explanatory drawing which shows the structure of the semiconductor device in the middle of manufacture. It is explanatory drawing which shows the structure of the semiconductor device in the middle of manufacture. It is explanatory drawing which shows the structure of the semiconductor device in the middle of manufacture. It is explanatory drawing which shows the structure of the semiconductor device in the middle of manufacture. It is sectional drawing which shows typically the structure of the semiconductor device used for the evaluation test. It is explanatory drawing which shows the result of an evaluation test. It is sectional drawing which shows typically the structure of the semiconductor device in 2nd Embodiment. It is sectional drawing which shows typically the structure of the semiconductor device in 3rd Embodiment. It is sectional drawing which shows typically the structure of the semiconductor device in 4th Embodiment. It is sectional drawing which shows typically the structure of the semiconductor device in 5th Embodiment. It is sectional drawing which shows typically the structure of the semiconductor device in the modification of 5th Embodiment. It is sectional drawing which shows typically the structure of the semiconductor device in 6th Embodiment. It is sectional drawing which shows typically the structure of the semiconductor device in the modification of 6th Embodiment.

A. First Embodiment A-1. Configuration of Semiconductor Device FIG. 1 is a cross-sectional view schematically showing the configuration of a semiconductor device 10 in the first embodiment. The semiconductor device 10 is a GaN-based semiconductor device formed using gallium nitride (GaN). In this embodiment, the semiconductor device 10 is a trench gate type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), is used for power control, and is also called a power device.

  The semiconductor device 10 includes a substrate 110, an n-type semiconductor layer 120, a p-type semiconductor layer 130, an n-type semiconductor layer 140, electrodes 210, 230, 250, and an insulating film 340. In the semiconductor device 10, a groove 170 and a recess 180 are formed. The semiconductor device 10 has a structure in which an n-type semiconductor layer 120, a p-type semiconductor layer 130, and an n-type semiconductor layer 140 are sequentially stacked. The semiconductor device 10 has a trench gate structure in which an electrode 250 is formed in the groove 170.

  FIG. 1 shows XYZ axes orthogonal to each other. Of the XYZ axes in FIG. 1, the X axis is an axis along the stacking direction in which the n-type semiconductor layer 120 is stacked on the substrate 110. Among the X-axis directions along the X-axis, the + X-axis direction is a direction from the substrate 110 toward the n-type semiconductor layer 120, and the −X-axis direction is a direction facing the + X-axis direction. Of the XYZ axes in FIG. 1, the Y axis and the Z axis are axes that are orthogonal to the Z axis and orthogonal to each other. Among the Y-axis directions along the Y-axis, the + Y-axis direction is a direction from the left side to the right side in FIG. 1, and the −Y-axis direction is a direction facing the + Y-axis direction. Among the Z-axis directions along the Z-axis, the + Z-axis direction is a direction from the front side of the paper in FIG. 1 toward the back of the paper surface, and the −Z-axis direction is a direction facing the + Z-axis direction.

The substrate 110 of the semiconductor device 10 is a semiconductor layer extending along the Y axis and the Z axis. In the present embodiment, the substrate 110 is mainly made of gallium nitride (GaN) and contains silicon (Si) as a donor at a higher concentration than the n-type semiconductor layer 120. In another embodiment, in this embodiment, the average concentration of Si in the entire region of the substrate 110 is 1.0 × 10 ¹⁸ cm ⁻³ or more.

The n-type semiconductor layer 120 of the semiconductor device 10 is a first n-type semiconductor layer that is stacked on the + X-axis direction side of the substrate 110 by crystal growth and extends along the Y-axis and the Z-axis. The n-type semiconductor layer 120 is mainly made of gallium nitride (GaN) and contains silicon (Si) as a donor at a lower concentration than the n-type semiconductor layer 140. In the present embodiment, the average concentration of Si in the entire area of the n-type semiconductor layer 120 is 1.0 × 10 ¹⁶ cm ⁻³ or less. The n-type semiconductor layer 120 is also referred to as “n ⁻ -GaN”.

  The n-type semiconductor layer 120 has a convex portion 150 that protrudes toward the p-type semiconductor layer 130 side (+ X-axis direction side). In the present embodiment, the protrusion 150 has a plate-like mesa structure extending in the Z-axis direction. In the present embodiment, the cross-sectional shape of the convex portion 150 is a rectangle in which the width on the + X-axis direction side is equal to the width on the −X-axis direction side. In the present embodiment, the convex portion 150 has a structure formed by dry etching and wet etching.

  The n-type semiconductor layer 120 has a first interface 121 and a second interface 122. The first interface 121 in the n-type semiconductor layer 120 is a surface facing the + X-axis direction and is adjacent to the p-type semiconductor layer 130. The second interface 122 in the n-type semiconductor layer 120 is a surface facing the + X-axis direction that constitutes the upper surface of the convex portion 150, and is adjacent to the p-type semiconductor layer 130. In the present embodiment, the first interface 121 and the second interface 122 are surfaces formed by dry etching and wet etching.

The p-type semiconductor layer 130 of the semiconductor device 10 is a semiconductor layer that is stacked on the + X-axis direction side of the n-type semiconductor layer 120 by crystal growth and extends along the Y-axis and the Z-axis. The p-type semiconductor layer 130 is mainly made of gallium nitride (GaN) and contains magnesium (Mg) as an acceptor. In the present embodiment, the average concentration of Mg in the entire region of the p-type semiconductor layer 130 is 1.0 × 10 ¹⁷ cm ⁻³ or more and 1.0 × 10 ²⁰ cm ⁻³ or less. The p-type semiconductor layer 130 is also called “p-GaN”.

  The p-type semiconductor layer 130 has a first part 131 and a second part 132. The first portion 131 in the p-type semiconductor layer 130 is a portion of the p-type semiconductor layer 130 that is stacked on the first interface 121 in the n-type semiconductor layer 120. The second portion 132 in the p-type semiconductor layer 130 is a portion of the p-type semiconductor layer 130 that is stacked on the second interface 122 in the n-type semiconductor layer 120. The first part 131 and the second part 132 are uniformly connected to each other. In the present embodiment, the acceptor concentration in the first part 131 is the same as the acceptor concentration in the second part 132. In other embodiments, the acceptor concentration at the first site 131 may be different from the acceptor concentration at the second site 132, where the change in acceptor concentration from the first site 131 to the second site 132 is It will be moderate.

  The p-type semiconductor layer 130 has a raised portion 135. The raised portion 135 is a first raised portion that is raised along the protruding portion 150 in the protruding direction (+ X-axis direction) in which the protruding portion 150 of the n-type semiconductor layer 120 protrudes. In the present embodiment, the p-type semiconductor layer 130 is divided by the groove 170 at the raised portion 135.

The n-type semiconductor layer 140 of the semiconductor device 10 is a second n-type semiconductor layer that is stacked on the + X-axis direction side of the p-type semiconductor layer 130 by crystal growth and extends along the Y-axis and the Z-axis. The n-type semiconductor layer 140 is mainly made of gallium nitride (GaN), and contains silicon (Si) as a donor at a higher concentration than the n-type semiconductor layer 120. In the present embodiment, the average concentration of Si in the entire area of the n-type semiconductor layer 140 is 3.0 × 10 ¹⁸ cm ⁻³ or more. The n-type semiconductor layer 140 is also referred to as “n ⁺ -GaN”.

  The n-type semiconductor layer 140 has a raised portion 145. The raised portion 145 is a second raised portion that is raised along the raised portion 135 of the p-type semiconductor layer 130 in the + X-axis direction. In the present embodiment, the n-type semiconductor layer 140 is divided by the groove 170 at the raised portion 145.

  The groove 170 of the semiconductor device 10 is a trench that penetrates from the + X-axis direction side of the n-type semiconductor layer 140 to the n-type semiconductor layer 120 through the p-type semiconductor layer 130. The groove portion 170 has a shape that falls into the convex portion 150 of the n-type semiconductor layer 120. In the present embodiment, the groove 170 has a shape extending in the Z-axis direction. In this embodiment, the groove part 170 is formed by being processed by wet etching after being processed by dry etching.

An insulating film 340 is formed on the surface of the trench 170 so as to reach the + X-axis direction side of the n-type semiconductor layer 140. In the present embodiment, the insulating film 340 is made of silicon dioxide (SiO ₂ ).

  The recess 180 of the semiconductor device 10 is formed by dry etching and wet etching, and is a recess that drops from the + X-axis direction side of the n-type semiconductor layer 140 to the p-type semiconductor layer 130.

  The electrode 210 of the semiconductor device 10 is a drain electrode formed on the −X axis direction side of the substrate 110. In this embodiment, the electrode 210 is formed by laminating a layer made of aluminum (Al) on a layer made of titanium (Ti) and then firing.

  The electrode 230 of the semiconductor device 10 is a source electrode formed in the recess 180. In the present embodiment, the electrode 230 is formed by laminating a layer made of titanium (Ti) and a layer made of aluminum (Al) on a layer made of palladium (Pd) and then firing.

  The electrode 250 of the semiconductor device 10 is a gate electrode formed in the groove 170 with the insulating film 340 interposed therebetween. In the present embodiment, the electrode 250 is made of aluminum (Al).

  FIG. 2 is a cross-sectional view schematically showing a configuration of the semiconductor device 10 enlarged around the convex portion 150 and the groove portion 170. The convex 150 has a part 152 and a part 158. The part 152 of the convex part 150 is a starting point from which the convex part 150 projects in the + X-axis direction. A portion 158 of the convex portion 150 is a vertex of the convex portion 150. The part 152 and the part 158 are also the side ends of the convex part 150. The groove 170 has a portion 172 that is an end of the bottom surface of the groove 170.

  The height Hm of the protrusion 150 is such that the protrusion 150 protrudes from the first interface 121 from the viewpoint of improving the crystal quality of the p-type semiconductor layer 130 and the n-type semiconductor layer 140 formed on the protrusion 150. The height Hm is preferably smaller than the combined thickness Tu of the thickness Tp of the p-type semiconductor layer 130 and the thickness Tn2 of the n-type semiconductor layer 140, and more preferably smaller than the thickness Tp of the p-type semiconductor layer 130. . In the present embodiment, the height Hm of the convex portion 150 is 0.3 μm (micrometer), and the thickness Tp of the p-type semiconductor layer 130 is 1.0 μm. In the present embodiment, the width Wm of the convex portion 150 along the Y-axis direction is 2.0 μm.

  From the viewpoint of ensuring the forward current flow, the depth h1 at which the groove 170 falls with respect to the upper surface of the convex portion 150 is 0.0 μm or more. In other words, the groove 170 reaches the convex portion 150. It is preferable. From the viewpoint of effectively realizing the relaxation of the electric field concentration in the groove portion 170, the depth h1 is preferably equal to or less than the depth obtained by adding 0.4 μm to the height Hm of the convex portion 150. In the present embodiment, the depth h1 is 0.2 μm.

  From the viewpoint of effectively realizing relaxation of the electric field concentration in the groove portion 170, the height h2 from the portion 152 to the portion 172 along the X-axis direction is 0.4 μm or less on the −X-axis direction side, in other words, It is preferable that the portion 172 exists on the + X axis direction side from the position of 0.4 μm on the −X axis direction side from the portion 152. From the viewpoint of increasing the avalanche resistance by avoiding damage at the bottom of the groove 170, the height h2 is 0.0 μm or more on the + X-axis direction side, in other words, the site 172 from the site 152 to the + X-axis direction side. It is even more preferred that be present. From the viewpoint of suppressing an increase in the thickness of the n-type semiconductor layer 120 and thus reducing the manufacturing cost, the height h2 is preferably 1.0 μm or less on the + X axis direction side.

  The distance w1 between the portion 152 and the portion 172 along the Y-axis direction preferably satisfies 0.1 μm ≦ w1 ≦ 2.0 μm, and more preferably satisfies 0.2 μm ≦ w1 ≦ 1.0 μm. In the present embodiment, the distance w1 is 0.5 μm. When the distance w1 is shorter than 0.1 μm, the depletion layer spreads at the bottom of the groove 170 during forward operation due to the influence of the p-type semiconductor layer 130 located on the Y-axis direction side, and thus the current hardly flows. The on-resistance increases. When the distance w1 exceeds 2.0 μm, the p-type semiconductor layer 130 cannot sufficiently relax the electric field concentration at the portion 172.

A-2. Semiconductor Device Manufacturing Method FIG. 3 is a process diagram showing a method for manufacturing the semiconductor device 10. When manufacturing the semiconductor device 10, the manufacturer first forms the n-type semiconductor layer 120 on the substrate 110 by crystal growth (process P110). In this embodiment, the manufacturer forms the n-type semiconductor layer 120 on the substrate 110 by crystal growth using an MOCVD apparatus that realizes metal organic chemical vapor deposition (MOCVD).

  FIG. 4 is an explanatory diagram showing a configuration of the semiconductor device 10a being manufactured. The semiconductor device 10a is manufactured by crystal growth of the n-type semiconductor layer 120 on the substrate 110 (process P110). The semiconductor device 10 a has a structure in which an n-type semiconductor layer 120 is stacked on a substrate 110. In the present embodiment, the thickness of the n-type semiconductor layer 120 formed by crystal growth (process P110) is 10 μm.

  Returning to the description of FIG. 3, after forming the n-type semiconductor layer 120 (process P110), the manufacturer forms the convex portion 150 on the n-type semiconductor layer 120 by dry etching and wet etching (process P120). In the present embodiment, the manufacturer forms an etching mask at a portion that becomes the convex portion 150 in the n-type semiconductor layer 120, and then moves a portion from the + X-axis direction side to the depth of 0.3 μm in the n-type semiconductor layer 120. It is removed by dry etching. Following dry etching, the manufacturer treats the surface of the n-type semiconductor layer 120 exposed by dry etching by wet etching, and then cleans the surface of the n-type semiconductor layer 120. Following the wet etching, the manufacturer removes the etching mask and then cleans the surface of the n-type semiconductor layer 120. Through these treatments, the convex portion 150 is formed in the n-type semiconductor layer 120. In another embodiment, the manufacturer may form the convex portion 150 only by dry etching without performing wet etching.

  FIG. 5 is an explanatory diagram showing the configuration of the semiconductor device 10b in the middle of manufacture. The semiconductor device 10b is manufactured by dry etching and wet etching (process P120) for the n-type semiconductor layer 120 of the semiconductor device 10a. The semiconductor device 10b includes an n-type semiconductor layer 120 having a convex portion 150 formed on the + X axis direction side. In the present embodiment, the height of the convex portion 150 along the X-axis direction is 0.3 μm.

  Returning to the description of FIG. 3, after forming the convex portion 150 (process P120), the manufacturer forms a p-type semiconductor layer by crystal growth on the surface of the n-type semiconductor layer 120 including the convex portion 150 on the + X-axis direction side. 130 is formed (process P130). In the present embodiment, the p-type semiconductor layer 130 has a shape that protrudes along the convex portion 150 of the n-type semiconductor layer 120 toward the + X-axis direction side. In another embodiment, the p-type semiconductor layer 130 may have a shape having a flat surface on the + X-axis direction side along the YZ plane.

  In this embodiment, the manufacturer forms the p-type semiconductor layer 130 on the n-type semiconductor layer 120 by crystal growth using an MOCVD apparatus. In this embodiment, the manufacturer forms the p-type semiconductor layer 130 on the entire surface of the n-type semiconductor layer 120 on the + X-axis direction side by crystal growth. In the present embodiment, the thickness of the p-type semiconductor layer 130 formed by crystal growth (process P130) is 1.0 μm.

  FIG. 6 is an explanatory diagram showing the configuration of the semiconductor device 10c being manufactured. The semiconductor device 10c is manufactured by crystal growth (process P130) of the p-type semiconductor layer 130 with respect to the n-type semiconductor layer 120 of the semiconductor device 10b. The semiconductor device 10 c includes a p-type semiconductor layer 130 having a raised portion 135. The raised portion 135 of the p-type semiconductor layer 130 is a portion raised on the + X-axis direction side along the convex portion 150 of the n-type semiconductor layer 120.

  Returning to the description of FIG. 3, after forming the p-type semiconductor layer 130 (process P130), the manufacturer forms the n-type semiconductor layer 140 by crystal growth on the surface in the + X-axis direction side of the p-type semiconductor layer 130. (Step P140). In the present embodiment, the n-type semiconductor layer 140 has a shape that rises toward the + X-axis direction along the raised portion 135 of the p-type semiconductor layer 130. In another embodiment, the n-type semiconductor layer 140 may have a shape having a uniformly flat surface on the + X axis direction side along the YZ plane.

  In this embodiment, the manufacturer forms the n-type semiconductor layer 140 on the p-type semiconductor layer 130 by crystal growth using an MOCVD apparatus. In this embodiment, the manufacturer forms the n-type semiconductor layer 140 by crystal growth on the entire surface of the p-type semiconductor layer 130 on the + X-axis direction side. In the present embodiment, the thickness of the n-type semiconductor layer 140 formed by crystal growth (process P140) is 0.3 μm.

  FIG. 7 is an explanatory diagram showing the configuration of the semiconductor device 10d being manufactured. The semiconductor device 10d is manufactured by crystal growth of the n-type semiconductor layer 140 with respect to the p-type semiconductor layer 130 of the semiconductor device 10c (process P140). The semiconductor device 10 d includes an n-type semiconductor layer 140 having a raised portion 145. The raised portion 145 of the n-type semiconductor layer 140 is a portion raised toward the + X-axis direction along the raised portion 135 of the p-type semiconductor layer 130. The raised portion 145 is also a portion raised on the + X-axis direction side along the convex portion 150 of the n-type semiconductor layer 120.

  Returning to FIG. 3, after forming the n-type semiconductor layer 140 (process P140), the manufacturer forms the groove 170 by dry etching and wet etching (process P150). In the present embodiment, the manufacturer forms an etching mask around the portion that becomes the groove 170 in the n-type semiconductor layer 140, and then penetrates the p-type semiconductor layer 130 from the n-type semiconductor layer 140 to the n-type semiconductor layer 120. The part up to the inside of the convex part 150 is removed by dry etching. Following dry etching, the manufacturer treats the surface of each semiconductor layer exposed by dry etching by wet etching, and then cleans the surface of each semiconductor layer. Following the wet etching, the manufacturer cleans the surface of each semiconductor layer after removing the etching mask. Through these processes, the groove 170 is formed. In another embodiment, the manufacturer may form the groove 170 only by dry etching without performing wet etching.

  FIG. 8 is an explanatory diagram showing the configuration of the semiconductor device 10e being manufactured. The semiconductor device 10e is manufactured by dry etching and wet etching (process P150) for the semiconductor device 10d. The semiconductor device 10e includes a groove 170 that penetrates from the n-type semiconductor layer 140 through the p-type semiconductor layer 130 to the inside of the protrusion 150 in the n-type semiconductor layer 120.

Returning to the description of FIG. 3, after forming the groove 170 (process P150), the manufacturer performs a heat treatment (process P160). In the heat treatment (process P170), the manufacturer heats (anneals) the semiconductor device 10e on which the insulating film 340 is formed in a gas containing oxygen (O ₂ ). As a result, damage to each semiconductor layer due to dry etching is recovered, and Mg that is an acceptor of the p-type semiconductor layer 130 is activated. In the present embodiment, the temperature of the gas used for the heat treatment (process P160) is 800 ° C. In the present embodiment, the time for heating the semiconductor device 10e in the heat treatment (process P160) is 5 minutes.

  After performing the heat treatment (process P160), the manufacturer forms the insulating film 340 on the surfaces of the groove 170 and the n-type semiconductor layer 140 (process P170).

  After forming the insulating film 340 (process P170), the manufacturer forms the electrodes 210, 230, and 250 on the semiconductor device 10e on which the insulating film 340 is formed (process P180). Through these steps, the semiconductor device 10 is completed.

A-3. Evaluation Test FIG. 9 is a cross-sectional view schematically showing the configuration of the semiconductor device 90 used in the evaluation test. FIG. 9 shows the XYZ axes as in FIG. The semiconductor device 90 includes a substrate 910, an n-type semiconductor layer 920, a p-type semiconductor layer 930, an n-type semiconductor layer 940, electrodes 991, 993 and 995, and an insulating film 994. In the semiconductor device 90, a groove portion 970 and a concave portion 980 are formed.

  The substrate 910 of the semiconductor device 90 is similar to the substrate 110 of the semiconductor device 10.

  The n-type semiconductor layer 920 of the semiconductor device 90 is the same as the n-type semiconductor layer 120 of the semiconductor device 10 except that the convex portion 150 is not formed.

  The p-type semiconductor layer 930 of the semiconductor device 90 is the same as the p-type semiconductor layer 130 of the semiconductor device 10 except that the raised portion 135 is not formed.

  The n-type semiconductor layer 940 of the semiconductor device 90 is the same as the n-type semiconductor layer 140 of the semiconductor device 10 except that the raised portion 145 is not formed.

  The groove part 970 of the semiconductor device 90 is a groove part 170 of the semiconductor device 10 except that the groove part 970 penetrates the p-type semiconductor layer 930 from the + X-axis direction side of the n-type semiconductor layer 940 to the n-type semiconductor layer 920. It is the same.

  The recess 980 of the semiconductor device 90 is the same as the recess 180 of the semiconductor device 10 except that the recess 980 is a recess that extends from the + X-axis direction side of the n-type semiconductor layer 940 to the p-type semiconductor layer 930.

  The electrodes 991, 993, 995 of the semiconductor device 90 are the same as 210, 230, 250 of the semiconductor device 10, respectively. The insulating film 994 is the same as the insulating film 340 of the semiconductor device 10 except that the insulating film 994 is formed on the surfaces of the trench 970 and the n-type semiconductor layer 940.

  FIG. 10 is an explanatory diagram showing the results of the evaluation test. In the evaluation test of FIG. 10, the tester prepared the semiconductor device 10 as the sample 1 and prepared the semiconductor device 90 as the sample 2. The tester measured the on-resistance and withstand voltage of each sample. As shown in FIG. 10, the withstand voltage of the semiconductor device 10 was 1400 to 1500 V (volts), and the withstand voltage of the semiconductor device 90 was 800 to 900 V. That is, the withstand voltage of the semiconductor device 10 is improved by 50% or more with respect to the semiconductor device 90. The on-resistance of the semiconductor device 10 was increased by 3 to 5% with respect to the semiconductor device 90.

A-4. Effect According to the first embodiment described above, the electric field concentration in the groove 170 can be reduced by the p-type semiconductor layer 130. As a result, the electrical characteristics of the semiconductor device 10 can be improved. Further, the withstand voltage can be improved in the GaN-based semiconductor device 10 in which it is difficult to form a p-type semiconductor by ion implantation.

  In addition, the p-type semiconductor layer 130 can be formed so that the electric field concentration in the groove 170 can be relaxed without using ion implantation and selective regrowth. As a result, the manufacturing cost can be suppressed. Further, an increase in on-resistance due to diffusion of the dopant of the p-type semiconductor layer 130 into at least one of the n-type semiconductor layer 120 and the n-type semiconductor layer 140 can be suppressed.

  Further, since the height Hm of the convex portion 150 is smaller than the thickness Tu, which is the sum of the thickness Tp of the p-type semiconductor layer 130 and the thickness Tn2 of the n-type semiconductor layer, the p-type semiconductor formed on the convex portion 150. The crystal quality of the layer 130 and the n-type semiconductor layer 140 can be improved.

  Further, since the depth H1 of the groove portion 170 is 0.0 μm or more and not more than a depth obtained by adding 0.4 μm to the height Hm of the convex portion 150, the forward current flow is ensured while ensuring the forward current flow. The electric field concentration can be effectively reduced.

  In addition, since the height h2 from the first interface 121 to the groove 170 is 1.0 μm or less on the + X axis direction side and 0.4 μm or less on the −X axis direction side, the thickness of the n-type semiconductor layer 120 is reduced. It is possible to effectively reduce the concentration of the electric field in the groove 170 while suppressing the increase.

  In addition, since the distance w1 satisfies 0.1 μm ≦ w1 ≦ 2.0 μm, an increase in on-resistance due to the distance w1 being too close can be suppressed, and an increase in electric field concentration in the groove 170 due to the distance w1 being too far away can be suppressed. it can.

B. Second Embodiment FIG. 11 is a cross-sectional view schematically showing a configuration of a semiconductor device 12 in a second embodiment. FIG. 11 shows the XYZ axes as in FIG. The semiconductor device 12 of the second embodiment is the same as the semiconductor device 10 of the first embodiment except that the semiconductor device 12 further includes a semiconductor layer 125.

  The semiconductor layer 125 is a semiconductor layer stacked between the n-type semiconductor layer 120 and the p-type semiconductor layer 130, and the semiconductor layer 125 can be regarded as a part of the n-type semiconductor layer 120. In the present embodiment, the semiconductor layer 125 of the semiconductor device 12 is a third n-type semiconductor layer having a donor concentration lower than that of the p-type semiconductor layer 130. In another embodiment, the semiconductor layer 125 may be an intrinsic semiconductor layer (undoped semiconductor layer) having a concentration lower than that of the p-type semiconductor layer 130, and is composed of at least one of an n-type semiconductor layer and an intrinsic semiconductor layer. There may be a plurality of semiconductor layers.

  The manufacturer of the semiconductor device 12 forms the projection 150 on the n-type semiconductor layer 120 by dry etching and wet etching (process P120), and then forms the n-type semiconductor prior to forming the p-type semiconductor layer 130 (process P130). A semiconductor layer 125 is formed over the layer 120. In this embodiment, the manufacturer forms the semiconductor layer 125 by crystal growth on the entire surface of the n-type semiconductor layer 120 on the + X-axis direction side. The temperature for growing the crystal of the semiconductor layer 125 is preferably 50 ° C. to 100 ° C. lower than the temperature for growing the crystal of the p-type semiconductor layer 130 in order to obtain good crystal quality. It may be the same temperature as the temperature at which 130 crystals are grown.

  The manufacturer of the semiconductor device 12 forms the semiconductor layer 125 on the n-type semiconductor layer 120, and then forms the p-type semiconductor layer 130 on the surface of the semiconductor layer 125 on the + X-axis direction side by crystal growth (process P130). ).

  According to the second embodiment described above, the electrical characteristics of the semiconductor device 12 can be improved as in the first embodiment. Further, as in the first embodiment, the manufacturing cost can be suppressed. In addition, when the crystal growth on the surface of the n-type semiconductor layer 120 is hindered by the influence of dry etching and wet etching (process P120) for forming the convex portion 150 (for example, rough surface morphology, adhesion of foreign matters on the surface, etc.) Even so, the p-type semiconductor layer 130 can be easily crystal-grown by forming the semiconductor layer 125. As a result, the crystal quality of the p-type semiconductor layer 130 can be improved.

C. Third Embodiment FIG. 12 is a cross-sectional view schematically showing a configuration of a semiconductor device 13 in a third embodiment. FIG. 12 shows the XYZ axes as in FIG. The semiconductor device 13 of the third embodiment is different from the electrode 230 in that it includes an electrode 232 suitable for the p-type semiconductor layer 130 and an electrode 234 suitable for the n-type semiconductor layer 140 except for the point of the first embodiment. Similar to the semiconductor device 10.

  In the present embodiment, the electrode 232 is an electrode made of palladium (Pd). In this embodiment, the electrode 234 is formed by laminating a layer made of aluminum (Al) on a layer made of titanium (Ti) and then firing.

  According to the second embodiment described above, the electrical characteristics of the semiconductor device 13 can be improved as in the first embodiment.

D. Fourth Embodiment FIG. 13 is a cross-sectional view schematically showing a configuration of a semiconductor device 14 in a fourth embodiment. FIG. 13 shows the XYZ axes as in FIG. The semiconductor device 14 of the fourth embodiment is the same as that of the first embodiment except that it has a termination structure using the groove 170D. The semiconductor device 14 has, as a termination structure, in addition to the groove portion 170D, the convex portion 150D, the first interface 121D, the second interface 122D, the first portion 131D, the second portion 132D, and the raised portion 135D. And a raised portion 145D and an insulating film 340D.

  The convex portion 150D of the fourth embodiment is the same as the convex portion 150 of the first embodiment except that the convex portion 150D is provided at a position corresponding to the groove portion 170F.

  Similar to the first interface 121 of the first embodiment, the first interface 121D in the n-type semiconductor layer 120 is a surface facing the + X-axis direction and is adjacent to the p-type semiconductor layer 130. The second interface 122D in the n-type semiconductor layer 120 is the same as the second interface 122 of the first embodiment, except that the second interface 122D is a surface facing the + X-axis direction that constitutes the upper surface of the convex portion 150D.

  The first portion 131D in the p-type semiconductor layer 130 is a portion of the p-type semiconductor layer 130 that is stacked on the first interface 121D in the n-type semiconductor layer 120. The second portion 132D in the p-type semiconductor layer 130 is a portion of the p-type semiconductor layer 130 that is stacked on the second interface 122D in the n-type semiconductor layer 120. The first portion 131D and the second portion 132D are uniformly connected to each other. In the present embodiment, the acceptor concentration in the first part 131D is the same as the acceptor concentration in the second part 132D. In other embodiments, the acceptor concentration at the first site 131D may be different from the acceptor concentration at the second site 132D, in which case the change in acceptor concentration from the first site 131D to the second site 132D is It will be moderate.

  The raised portions 135D and 145D of the fourth embodiment are the same as the raised portions 135 and 145 of the first embodiment, except that the raised portions 135D and 145D are provided at positions corresponding to the groove portions 170D.

  The groove part 170D of the fourth embodiment is the same as the groove part 170 of the first embodiment except that the groove part 170D is a trench that constitutes a termination structure. The groove 170 </ b> D is a trench penetrating from the + X-axis direction side of the n-type semiconductor layer 140 to the n-type semiconductor layer 120 through the p-type semiconductor layer 130. The groove 170 </ b> D has a shape that falls into the convex portion 150 </ b> D of the n-type semiconductor layer 120. In other embodiments, the configurations of the second embodiment and the third embodiment may be applied to the groove 170D.

  The insulating film 340D according to the fourth embodiment is the same as the insulating film 340 according to the first embodiment except that the groove 170D has a filling portion 345D. In other embodiments, the groove 170D may be provided with an electrode in the same manner as the electrode 250 of the first embodiment, instead of the filling portion 345D.

  According to the fourth embodiment described above, the electric field concentration in the groove 170D can be relaxed by the p-type semiconductor layer 130 as in the first embodiment. As a result, the electrical characteristics of the semiconductor device 14 can be improved.

E. Fifth Embodiment FIG. 14 is a cross-sectional view schematically showing a configuration of a semiconductor device 15 in a fifth embodiment. FIG. 14 shows the XYZ axes as in FIG.

  Similar to the first embodiment, the semiconductor device 15 of the fifth embodiment includes a substrate 110, an n-type semiconductor layer 120, a p-type semiconductor layer 130, and an n-type semiconductor layer 140. The semiconductor device 15 includes a step portion 192 and a termination portion 194 as a termination structure on the −Y axis direction side. In the present embodiment, the semiconductor device 15 has a termination structure on the + Y axis direction side, similarly to the −Y axis direction side.

  The step portion 192 of the semiconductor device 15 forms a step from the n-type semiconductor layer 140 to the n-type semiconductor layer 120 through the p-type semiconductor layer 130. The step portion 192 faces the −Y-axis direction of the n-type semiconductor layer 140, the interface of the p-type semiconductor layer 13 that faces the −Y-axis direction, and the −Y-axis direction of the n-type semiconductor layer 120. Interface.

  The terminal portion 194 of the semiconductor device 15 is an end portion of the semiconductor device 15 located on the −Y axis direction side from the step portion 192. The terminal portion 194 includes an interface facing the −Y axis direction in the n-type semiconductor layer 120 and an interface facing the −Y axis direction in the substrate 110. In the n-type semiconductor layer 120, an interface 129 facing the + X axis direction is formed between the stepped portion 192 and the terminal end portion 194.

  The semiconductor device 15 includes an electrode 210, an electrode 230, an electrode 250, and an insulating film 340, as in the first embodiment. In the semiconductor device 15, there are a plurality of electrodes 230 and electrodes 250, and the electrodes 230 and the electrodes 250 are alternately arranged in the Y-axis direction. In the present embodiment, the electrode 230 and the electrode 250 each extend along the Z-axis direction. In the present embodiment, the plurality of electrodes 250 in the semiconductor device 15 are connected in parallel at a portion not shown.

  The semiconductor device 15 has a plurality of trench gate structures in which electrodes 250 are formed in the groove 170. The n-type semiconductor layer 120 of the semiconductor device 15 has a convex portion 150E. The convex portion 150 </ b> E is closer to the end side (−Y axis direction side) than the groove portion 170 located on the end side of the semiconductor device 15 (that is, the −Y axis direction side where the end portion 194 is formed) among the plurality of groove portions 170. , Projecting from the first interface 121. In the present embodiment, the convex portion 150E extends from the groove portion 170 on the termination structure side on the −Y axis direction side to the groove portion 170 on the termination structure side on the + Y axis direction side, toward the p-type semiconductor layer 130 side (+ X axis direction side). This is a protruding part.

  The semiconductor device 15 further includes an electrode 260E and an insulating film 350E.

The insulating film 350E of the semiconductor device 15 has electrical insulation and covers the interface 129, the stepped portion 192, the electrode 230, the electrode 250, and the insulating film 340. The insulating film 350E has a portion 359E that covers the step portion 192. In the present embodiment, the insulating film 350E is made of silicon dioxide (SiO ₂ ).

  The electrode 260E of the semiconductor device 15 has conductivity and is stacked on the insulating film 350E. The electrode 260E is a source wiring electrode having a plurality of connection portions 262E connected to each of the plurality of electrodes 230. Thereby, a plurality of elements corresponding to the plurality of electrodes 250 are connected in parallel. In the present embodiment, the electrode 260E is made of aluminum (Al).

  The electrode 260E has a portion 269E that sandwiches the insulating film 350E between the step portion 192 and the electrode 260E. The portion 269E of the electrode 260E constitutes a field plate structure 410E together with the portion 359E of the insulating film 350E.

  According to the fifth embodiment described above, the electric field concentration can be relaxed by the p-type semiconductor layer 130 in the groove portion 170 on the terminal side, as in the first embodiment. As a result, the electrical characteristics of the semiconductor device 15 can be improved.

  In addition, since the first interface 121 that is the pn junction on the termination side is located on the −X axis direction side from the groove 170 on the termination side and the second interface 122, the first interface 121 is high between the electrode 210 and the electrode 230. When a voltage is applied, an avalanche breakdown occurs at the first interface 121 that is a pn junction on the termination side. Thus, by avoiding damage to the groove 170, the avalanche resistance can be increased.

  In addition, the field plate structure 410E can alleviate electric field concentration occurring at the first interface 121, which is the terminal-side pn junction in the stepped portion 192.

  FIG. 15 is a cross-sectional view schematically showing the configuration of the semiconductor device 16 in a modification of the fifth embodiment. FIG. 15 shows the XYZ axes as in FIG. The semiconductor device 16 is the same as the semiconductor device 15 of FIG. 14 except that the semiconductor device 16 includes the semiconductor layer 125 as in the second embodiment. According to the semiconductor device 16, as with the semiconductor device 15, the electrical characteristics of the semiconductor device 15 can be improved.

F. Sixth Embodiment FIG. 16 is a cross-sectional view schematically showing a configuration of a semiconductor device 17 in a sixth embodiment. FIG. 16 shows the XYZ axes as in FIG.

  Similar to the first embodiment, the semiconductor device 17 of the sixth embodiment includes a substrate 110, an n-type semiconductor layer 120, a p-type semiconductor layer 130, and an n-type semiconductor layer 140. Similar to the semiconductor device 15 of the fifth embodiment, the semiconductor device 17 includes a step portion 192 and a termination portion 194 as a termination structure on the −Y axis direction side. In the present embodiment, the semiconductor device 17 has a termination structure on the + Y axis direction side, similarly to the −Y axis direction side.

  Similar to the first embodiment, the semiconductor device 17 includes an electrode 210, an electrode 230, an electrode 250, and an insulating film 340. In the semiconductor device 17, there are a plurality of electrodes 230 and electrodes 250, and the electrodes 230 and the electrodes 250 are alternately arranged in the Y-axis direction. In the present embodiment, the electrode 230 and the electrode 250 each extend along the Z-axis direction. In the present embodiment, the plurality of electrodes 250 in the semiconductor device 17 are connected in parallel at a portion not shown.

  The semiconductor device 17 has a plurality of trench gate structures in which electrodes 250 are formed in the groove 170. The n-type semiconductor layer 120 of the semiconductor device 17 has a plurality of convex portions 150 at positions corresponding to the plurality of groove portions 170, respectively.

  The semiconductor device 17 further includes an insulating film 350F and an electrode 260F.

  The insulating film 350F of the semiconductor device 17 is the same as the insulating film 350E of the fifth embodiment except that it has a shape corresponding to the plurality of convex portions 150. The insulating film 350F has a portion 359F that covers the step portion 192.

  The electrode 260F of the semiconductor device 17 is the same as the electrode 260E of the fifth embodiment except that the electrode 260F has a shape corresponding to the plurality of convex portions 150. The electrode 260F is a source wiring electrode having a plurality of connection portions 262F connected to each of the plurality of electrodes 230.

  The electrode 260F has a portion 269F that sandwiches the insulating film 350F between the step portion 192 and the electrode 260F. The part 269F of the electrode 260F constitutes the field plate structure 410F together with the part 359F of the insulating film 350F.

  According to the sixth embodiment described above, the electric field concentration can be reduced by the p-type semiconductor layer 130 in the plurality of groove portions 170 as in the first embodiment. As a result, the electrical characteristics of the semiconductor device 15 can be improved. Further, as in the fifth embodiment, the avalanche resistance can be increased. Further, the field plate structure 410F can alleviate electric field concentration occurring at the first interface 121, which is the terminal-side pn junction in the stepped portion 192.

  FIG. 17 is a cross-sectional view schematically showing the configuration of the semiconductor device 18 in a modification of the sixth embodiment. FIG. 17 shows the XYZ axes as in FIG. The semiconductor device 18 is the same as the semiconductor device 17 of FIG. 16 except that the semiconductor device 18 includes the semiconductor layer 125 as in the second embodiment. According to the semiconductor device 18, as with the semiconductor device 17, the electrical characteristics of the semiconductor device 15 can be improved.

G. Other Embodiments The present invention is not limited to the above-described embodiments, examples, and modifications, and can be realized with various configurations without departing from the spirit thereof. For example, the technical features in the embodiments, examples, and modifications corresponding to the technical features in each embodiment described in the summary section of the invention are to solve some or all of the above-described problems, or In order to achieve part or all of the above-described effects, replacement or combination can be performed as appropriate. Further, if the technical feature is not described as essential in the present specification, it can be deleted as appropriate.

  In the above-described embodiment, the convex portion 150 may have a shape extending in an arbitrary direction along the YZ plane. In the above-described embodiment, the cross-sectional shape of the protrusion 150 may be a shape that protrudes in the + X-axis direction, and may form a trapezoid whose width on the −X-axis direction side is wider than the width on the + X-axis direction side. A trapezoid whose width on the + X-axis direction side is wider than the width on the −X-axis direction side may be formed. In the above-described embodiment, the protrusion 150 may be formed only by dry etching without being processed by wet etching.

  In the embodiment described above, the groove 170 may have a shape extending in an arbitrary direction along the YZ plane. In the above-described embodiment, the groove 170 may be formed only by dry etching without being processed by wet etching.

  In the above-described embodiment, the p-type semiconductor layer 130 has a shape having a uniformly flat surface on the + X axis direction side along the YZ plane, that is, a shape in which the raised portions 135 and 135D are not formed. Good. In the above-described embodiment, the portion of the p-type semiconductor layer 130 located on the + Y axis direction side from the groove portion 170 and the portion of the p-type semiconductor layer 130 located on the −Y axis direction side from the groove portion 170 are not shown. It may be connected through a part of the p-type semiconductor layer 130.

  In the above-described embodiment, the n-type semiconductor layer 140 has a shape having a uniformly flat surface on the + X-axis direction side along the YZ plane, that is, a shape in which the raised portions 145 and 145D are not formed. Good. In the above-described embodiment, the portion of the n-type semiconductor layer 140 located on the + Y axis direction side from the groove portion 170 and the portion of the n-type semiconductor layer 140 located on the −Y axis direction side from the groove portion 170 are not shown. The n-type semiconductor layer 140 may be connected through a site.

  In the above-described embodiment, an intrinsic semiconductor layer may be formed between the substrate and the n-type semiconductor layer, or an intrinsic semiconductor layer may be formed between the n-type semiconductor layer and the p-type semiconductor layer.

In the above-described embodiment, the material of the substrate is not limited to gallium nitride (GaN), but may be silicon (Si), sapphire (Al ₂ O ₃ ), silicon carbide (SiC), or the like.

  In the above-described embodiment, the donor contained in at least one of the substrate and the n-type semiconductor layer is not limited to silicon (Si), but may be germanium (Ge), oxygen (O), or the like.

  In the above-described embodiment, the acceptor included in the p-type semiconductor layer is not limited to magnesium (Mg) but may be zinc (Zn), carbon (C), or the like.

In the above embodiment, the material of the insulating film is not limited to silicon dioxide (SiO ₂ ), but silicon nitride (SiN), silicon nitride oxide (SiON), aluminum oxide (Al ₂ O ₃ ), aluminum nitride oxide (AlON) Zirconium dioxide (ZrO ₂ ), titanium oxide (TiO ₂ ), tantalum pentoxide (Ta ₂ O ₅ ), niobium pentoxide (Nb ₂ O ₅ ), hafnium dioxide (HfO ₂ ), aluminum nitride (AlN), etc. May be. In the above-described embodiment, the insulating film is not limited to a single layer, and may be configured by a plurality of layers made of different materials.

  The trench gate structure in the above-described embodiment is not limited to the MOSFET, but may be applied to other semiconductor devices (for example, an insulated gate bipolar transistor (IGBT)).

  In the fifth embodiment and the sixth embodiment, the plurality of electrodes 250 are each part of an electrode having a mesh shape having a plurality of meshes (for example, hexagonal meshes) when viewed from the + X-axis direction side. The electrode 230 may be formed in each of the plurality of meshes. In the fifth and sixth embodiments, the plurality of electrodes 230 and the plurality of electrodes 250 each extend along the Z-axis direction, and the plurality of electrodes 230 are connected to each other on the + Z-axis direction side. The plurality of electrodes 250 may be connected to each other on the −Z axis direction side.

DESCRIPTION OF SYMBOLS 10 ... Semiconductor device 10a-10e ... Semiconductor device in process of manufacture 12, 13, 14, 15, 16, 17, 18 ... Semiconductor device 90 ... Semiconductor device 110 ... Substrate 120 ... N-type semiconductor layer 121, 121D ... 1st Interface 122, 122D ... Second interface 125 ... Semiconductor layer 130 ... P-type semiconductor layer 131, 131D ... First portion 132, 132D ... Second portion 135, 135D ... Raised portion 140 ... N-type semiconductor layer 145, 145D ... Bump 150,150E ... Convex 152 ... Part 158 ... Part 170,170D ... Groove 172 ... Part 180 ... Concave 192 ... Step 194 ... Terminal 210 ... Electrode 230 ... Electrode 232 ... Electrode 234 ... Electrode 250 ... Electrode 260E , 260F ... Electrodes 269E, 269F ... Sites 340, 340D ... Insulating film 345D ... Filling part 35 E, 350F ... Insulating film 359E, 359F ... Site 410E, 410F ... Field plate structure 910 ... Substrate 920 ... n-type semiconductor layer 930 ... p-type semiconductor layer 940 ... n-type semiconductor layer 970 ... groove 980 ... concave part 991, 993, 995 ... Electrode 994 ... Insulating film

Claims (17)

A semiconductor device,
A first n-type semiconductor layer having a first interface and a second interface constituting the upper surface of the convex portion protruding from the first interface;
A p-type semiconductor layer laminated on the first n-type semiconductor layer, wherein a first part laminated on the first interface and a second part laminated on the second interface A uniform p-type semiconductor layer;
A second n-type semiconductor layer stacked on the p-type semiconductor layer;
A groove portion penetrating from the second n-type semiconductor layer through the p-type semiconductor layer to the inside of the convex portion in the first n-type semiconductor layer , and
The height Hm at which the protrusion protrudes from the first interface is the thickness Tp of the p-type semiconductor layer in the first part and the thickness Tn2 of the second n-type semiconductor layer in the first part. A semiconductor device smaller than the combined thickness Tu . The semiconductor device according to claim 1,
The p-type semiconductor layer has a first raised portion raised along the convex portion in a protruding direction in which the convex portion protrudes,
The second n-type semiconductor layer includes a second raised portion that is raised along the first raised portion in the protruding direction.   The semiconductor device according to claim 1, further comprising an electrode formed in the groove through an insulating film. The depth h1 at which the groove portion falls with respect to the upper surface of the convex portion is 0.0 μm or more, and is a depth obtained by adding 0.4 μm to the height Hm at which the convex portion protrudes from the first interface. The semiconductor device according to any one of claims 1 to 3 , wherein: A height h2 from the first interface to the bottom surface of the groove along the X-axis direction from which the convex portion protrudes is 1. on the + X-axis direction side from the first interface toward the second interface. 0μm or less and wherein the second interface is a first 0.4μm or less in the -X-axis direction side toward the interface, the semiconductor device according to any one of claims 1 to 4. The distance w1 between the bottom surface of the side edge and the groove portion of the convex portion satisfies 0.1 [mu] m ≦ w1 ≦ 2.0 .mu.m, the semiconductor device according to any one of claims 1 to 5. The distance w1 between the bottom surface of the side edge and the groove portion of the convex portion satisfies 0.2 [mu] m ≦ w1 ≦ 1.0 .mu.m, the semiconductor device according to any one of claims 1 to 6. The semiconductor device according to any one of claims 1 to 7 , further comprising a third n-type semiconductor layer stacked between the first n-type semiconductor layer and the p-type semiconductor layer. . The semiconductor device according to any one of claims 1 to 8 , further comprising an intrinsic semiconductor layer stacked between the first n-type semiconductor layer and the p-type semiconductor layer. The first acceptor concentration at the site are the same as the acceptor concentration in the second region, the semiconductor device according to any one of claims 1 to 9. The first n-type semiconductor layer, the p-type semiconductor layer, and the second n-type semiconductor layer is a semiconductor layer made primarily of gallium nitride (GaN), any of the preceding claims 10 The semiconductor device according to claim 1. A semiconductor device according to any one of claims 1 to 11 ,
The groove is plural,
The semiconductor device, wherein the convex portion protrudes from the first interface on the end side from a groove portion located on the end side of the semiconductor device among at least the plurality of groove portions. The semiconductor device according to any one of claims 1 to 12 , further comprising:
A step portion formed on the terminal side of the semiconductor device from the groove portion and extending from the second n-type semiconductor layer through the p-type semiconductor layer to the first n-type semiconductor layer;
An insulating film having electrical insulation and covering the stepped portion;
A semiconductor device comprising: an electrode that is conductive, stacked on the insulating film, and sandwiches the insulating film between the stepped portion. The semiconductor device according to any one of claims 1 to 13 , further comprising:
A source electrode formed in a recess extending from the second n-type semiconductor layer to the p-type semiconductor layer;
A gate electrode formed through an insulating film in the groove,
In a cross section along the stacking direction in which the first n-type semiconductor layer, the p-type semiconductor layer, and the second n-type semiconductor layer are stacked, a part of the source electrode and a part of the gate electrode are The semiconductor devices are arranged alternately. A method for manufacturing a semiconductor device, comprising:
Forming a first n-type semiconductor layer;
Forming a protrusion on the first n-type semiconductor layer by dry etching;
Forming a p-type semiconductor layer by crystal growth on a surface of the first n-type semiconductor layer including the convex portion;
Forming a second n-type semiconductor layer on the surface of the p-type semiconductor layer by crystal growth;
Forming, by dry etching, a groove portion that penetrates from the second n-type semiconductor layer through the p-type semiconductor layer and reaches the inside of the convex portion in the first n-type semiconductor layer , and
The height Hm at which the convex portion protrudes from the first interface of the first n-type semiconductor layer is the p-type semiconductor in the first portion of the p-type semiconductor layer stacked on the first interface. A method for manufacturing a semiconductor device , wherein the thickness Tp of the layer and the thickness Tu combined with the thickness Tn2 of the second n-type semiconductor layer in the first part are smaller .   A method for manufacturing a semiconductor device, comprising:
  Forming a first n-type semiconductor layer;
  Forming a protrusion on the first n-type semiconductor layer by dry etching;
  Forming a p-type semiconductor layer by crystal growth on a surface of the first n-type semiconductor layer including the convex portion;
  Forming a second n-type semiconductor layer on the surface of the p-type semiconductor layer by crystal growth;
  Forming, by dry etching, a groove portion that penetrates from the second n-type semiconductor layer through the p-type semiconductor layer and reaches the inside of the convex portion in the first n-type semiconductor layer;
  With
  The step of forming the convex portion includes a step of performing wet etching on the first n-type semiconductor layer after performing the dry etching. 17. The method of manufacturing a semiconductor device according to claim 15, wherein a distance w <b> 1 between a side end of the convex portion and a bottom surface of the groove satisfies 0.1 μm ≦ w <b> 1 ≦ 2.0 μm.

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