JP6306160B2 - メソクロナスｄｄｒシステムのための低レイテンシ同期スキーム - Google Patents

メソクロナスｄｄｒシステムのための低レイテンシ同期スキーム Download PDF

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Publication number
JP6306160B2
JP6306160B2 JP2016515324A JP2016515324A JP6306160B2 JP 6306160 B2 JP6306160 B2 JP 6306160B2 JP 2016515324 A JP2016515324 A JP 2016515324A JP 2016515324 A JP2016515324 A JP 2016515324A JP 6306160 B2 JP6306160 B2 JP 6306160B2
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Japan
Prior art keywords
data
clock signal
sampled
clean
flip
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JP2016515324A
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Japanese (ja)
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JP2016522499A5 (enExample
JP2016522499A (ja
Inventor
ホセ、エドウィン
ドロップ、マイケル
ファン、シュハオ
サンクラトリ、ラグー
スリラマジリ、ディープティ
ペドラリ−ノイ、マルツィオ
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Qualcomm Inc
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Qualcomm Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
JP2016515324A 2013-05-24 2014-06-02 メソクロナスｄｄｒシステムのための低レイテンシ同期スキーム Expired - Fee Related JP6306160B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/902,705 US9123408B2 (en) 2013-05-24 2013-05-24 Low latency synchronization scheme for mesochronous DDR system
PCT/US2014/000141 WO2014189551A1 (en) 2013-05-24 2014-06-02 Low latency synchronization scheme for mesochronous ddr system

Publications (3)

Publication Number Publication Date
JP2016522499A JP2016522499A (ja) 2016-07-28
JP2016522499A5 JP2016522499A5 (enExample) 2017-06-22
JP6306160B2 true JP6306160B2 (ja) 2018-04-04

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016515324A Expired - Fee Related JP6306160B2 (ja) 2013-05-24 2014-06-02 メソクロナスｄｄｒシステムのための低レイテンシ同期スキーム

Country Status (5)

Country Link
US (2) US9123408B2 (enExample)
EP (1) EP3028161B1 (enExample)
JP (1) JP6306160B2 (enExample)
KR (1) KR20160040140A (enExample)
WO (1) WO2014189551A1 (enExample)

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US9123408B2 (en) 2013-05-24 2015-09-01 Qualcomm Incorporated Low latency synchronization scheme for mesochronous DDR system
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US9478268B2 (en) * 2014-06-12 2016-10-25 Qualcomm Incorporated Distributed clock synchronization
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US9209961B1 (en) * 2014-09-29 2015-12-08 Apple Inc. Method and apparatus for delay compensation in data transmission
US10187067B2 (en) * 2014-10-14 2019-01-22 Qatar University Phase-locked loop (PLL)-type resolver/converter method and apparatus
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US9324397B1 (en) * 2015-01-16 2016-04-26 Qualcomm Incorporated Common die for supporting different external memory types with minimal packaging complexity
US9369139B1 (en) 2015-02-14 2016-06-14 Integrated Device Technology, Inc. Fractional reference-injection PLL
US9336896B1 (en) 2015-03-23 2016-05-10 Integrated Device Technology, Inc. System and method for voltage regulation of one-time-programmable (OTP) memory programming voltage
US9455045B1 (en) 2015-04-20 2016-09-27 Integrated Device Technology, Inc. Controlling operation of a timing device using an OTP NVM to store timing device configurations in a RAM
US9362928B1 (en) 2015-07-08 2016-06-07 Integrated Device Technology, Inc. Low-spurious fractional N-frequency divider and method of use
US9362924B1 (en) * 2015-07-08 2016-06-07 Integrated Device Technology, Inc. Method and apparatus for fast frequency acquisition in PLL system
US9954516B1 (en) 2015-08-19 2018-04-24 Integrated Device Technology, Inc. Timing device having multi-purpose pin with proactive function
US9590637B1 (en) 2015-08-28 2017-03-07 Integrated Device Technology, Inc. High-speed programmable frequency divider with 50% output duty cycle
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US9847869B1 (en) 2015-10-23 2017-12-19 Integrated Device Technology, Inc. Frequency synthesizer with microcode control
US9614508B1 (en) 2015-12-03 2017-04-04 Integrated Device Technology, Inc. System and method for deskewing output clock signals
US9893877B2 (en) * 2016-01-15 2018-02-13 Analog Devices Global Circuits, systems, and methods for synchronization of sampling and sample rate setting
US10075284B1 (en) 2016-01-21 2018-09-11 Integrated Device Technology, Inc. Pulse width modulation (PWM) to align clocks across multiple separated cards within a communication system
US9852039B1 (en) 2016-02-03 2017-12-26 Integrated Device Technology, Inc Phase locked loop (PLL) timing device evaluation system and method for evaluating PLL timing devices
US9859901B1 (en) 2016-03-08 2018-01-02 Integrated Device Technology, Inc. Buffer with programmable input/output phase relationship
US9692394B1 (en) 2016-03-25 2017-06-27 Integrated Device Technology, Inc. Programmable low power high-speed current steering logic (LPHCSL) driver and method of use
US9698787B1 (en) 2016-03-28 2017-07-04 Integrated Device Technology, Inc. Integrated low voltage differential signaling (LVDS) and high-speed current steering logic (HCSL) circuit and method of use
US9581973B1 (en) 2016-03-29 2017-02-28 Integrated Device Technology, Inc. Dual mode clock using a common resonator and associated method of use
US9954541B1 (en) 2016-03-29 2018-04-24 Integrated Device Technology, Inc. Bulk acoustic wave resonator based fractional frequency synthesizer and method of use
US9654121B1 (en) 2016-06-01 2017-05-16 Integrated Device Technology, Inc. Calibration method and apparatus for phase locked loop circuit
US10164758B2 (en) 2016-11-30 2018-12-25 Taiwan Semicondcutor Manufacturing Co., Ltd. Read-write data translation technique of asynchronous clock domains
KR102371264B1 (ko) * 2017-04-21 2022-03-07 에스케이하이닉스 주식회사 메모리 시스템
US10965442B2 (en) * 2018-10-02 2021-03-30 Qualcomm Incorporated Low-power, low-latency time-to-digital-converter-based serial link
US11580048B1 (en) 2019-03-18 2023-02-14 Cadence Designs Systems, Inc. Reference voltage training scheme
CN110059036B (zh) * 2019-04-15 2022-04-26 西安微电子技术研究所 一种存储体内部多异步接口访问控制装置及方法
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Also Published As

Publication number Publication date
US9123408B2 (en) 2015-09-01
KR20160040140A (ko) 2016-04-12
EP3028161B1 (en) 2018-07-18
US9437278B2 (en) 2016-09-06
US20150340078A1 (en) 2015-11-26
EP3028161A1 (en) 2016-06-08
US20140347941A1 (en) 2014-11-27
WO2014189551A1 (en) 2014-11-27
JP2016522499A (ja) 2016-07-28

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