JP6249571B2 - 適応電荷平衡ｍｏｓｆｅｔ技法 - Google Patents

適応電荷平衡ｍｏｓｆｅｔ技法 Download PDF

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JP6249571B2
JP6249571B2 JP2015550821A JP2015550821A JP6249571B2 JP 6249571 B2 JP6249571 B2 JP 6249571B2 JP 2015550821 A JP2015550821 A JP 2015550821A JP 2015550821 A JP2015550821 A JP 2015550821A JP 6249571 B2 JP6249571 B2 JP 6249571B2
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field plate
region
type dopant
semiconductor layer
heavily doped
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JP2016506082A (ja
JP2016506082A5 (cg-RX-API-DMAC10.html
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ナヴィーン ティピルネニ，
ナヴィーン ティピルネニ，
ディーヴァ エヌ． パタナヤク，
ディーヴァ エヌ． パタナヤク，
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ヴィシェイ−シリコニックス
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/112—Field plates comprising multiple field plate segments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/222—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the angle between the ion beam and the crystal planes or the main crystal surface

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
JP2015550821A 2012-12-31 2013-12-27 適応電荷平衡ｍｏｓｆｅｔ技法 Active JP6249571B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/732,284 2012-12-31
US13/732,284 US9853140B2 (en) 2012-12-31 2012-12-31 Adaptive charge balanced MOSFET techniques
PCT/US2013/078129 WO2014106127A1 (en) 2012-12-31 2013-12-27 Adaptive charge balanced mosfet techniques

Publications (3)

Publication Number Publication Date
JP2016506082A JP2016506082A (ja) 2016-02-25
JP2016506082A5 JP2016506082A5 (cg-RX-API-DMAC10.html) 2017-10-26
JP6249571B2 true JP6249571B2 (ja) 2017-12-20

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JP2015550821A Active JP6249571B2 (ja) 2012-12-31 2013-12-27 適応電荷平衡ｍｏｓｆｅｔ技法

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Country Link
US (1) US9853140B2 (cg-RX-API-DMAC10.html)
EP (1) EP2939272B1 (cg-RX-API-DMAC10.html)
JP (1) JP6249571B2 (cg-RX-API-DMAC10.html)
KR (1) KR101786278B1 (cg-RX-API-DMAC10.html)
CN (1) CN105027290B (cg-RX-API-DMAC10.html)
WO (1) WO2014106127A1 (cg-RX-API-DMAC10.html)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11721732B2 (en) 2021-08-18 2023-08-08 Kabushiki Kaisha Toshiba Semiconductor device with control electrodes provided in trenches of different widths

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9853140B2 (en) 2012-12-31 2017-12-26 Vishay-Siliconix Adaptive charge balanced MOSFET techniques
WO2016080322A1 (ja) 2014-11-18 2016-05-26 ローム株式会社 半導体装置および半導体装置の製造方法
TWI599041B (zh) * 2015-11-23 2017-09-11 節能元件控股有限公司 具有底部閘極之金氧半場效電晶體功率元件及其製作方法
WO2017130374A1 (ja) * 2016-01-29 2017-08-03 新電元工業株式会社 パワー半導体装置及びパワー半導体装置の製造方法
EP4235753A3 (en) * 2021-02-17 2023-11-08 Infineon Technologies Austria AG Semiconductor power device and method of manufacturing the same
JP7470075B2 (ja) 2021-03-10 2024-04-17 株式会社東芝 半導体装置

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US6252288B1 (en) 1999-01-19 2001-06-26 Rockwell Science Center, Llc High power trench-based rectifier with improved reverse breakdown characteristic
JP2002100772A (ja) 2000-07-17 2002-04-05 Toshiba Corp 電力用半導体装置及びその製造方法
US7132712B2 (en) 2002-11-05 2006-11-07 Fairchild Semiconductor Corporation Trench structure having one or more diodes embedded therein adjacent a PN junction
US6677641B2 (en) 2001-10-17 2004-01-13 Fairchild Semiconductor Corporation Semiconductor structure with improved smaller forward voltage loss and higher blocking capability
DE10235198B4 (de) 2001-08-02 2011-08-11 Fuji Electric Systems Co., Ltd. Leistungs-Halbleitergleichrichter mit ringförmigen Gräben
JP4209260B2 (ja) 2003-06-04 2009-01-14 Ｎｅｃエレクトロニクス株式会社 半導体装置およびその製造方法
WO2005065385A2 (en) 2003-12-30 2005-07-21 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
US7326617B2 (en) * 2005-08-23 2008-02-05 United Microelectronics Corp. Method of fabricating a three-dimensional multi-gate device
EP2109879A4 (en) * 2007-01-09 2011-05-18 Maxpower Semiconductor Inc Semiconductor device and method of manufacturing the same
US20080272429A1 (en) 2007-05-04 2008-11-06 Icemos Technology Corporation Superjunction devices having narrow surface layout of terminal structures and methods of manufacturing the devices
JP2011512677A (ja) 2008-02-14 2011-04-21 マックスパワー・セミコンダクター・インコーポレイテッド 半導体素子構造及び関連プロセス
US20100264486A1 (en) 2009-04-20 2010-10-21 Texas Instruments Incorporated Field plate trench mosfet transistor with graded dielectric liner thickness
US10026835B2 (en) 2009-10-28 2018-07-17 Vishay-Siliconix Field boosted metal-oxide-semiconductor field effect transistor
US8354711B2 (en) * 2010-01-11 2013-01-15 Maxpower Semiconductor, Inc. Power MOSFET and its edge termination
WO2011087994A2 (en) 2010-01-12 2011-07-21 Maxpower Semiconductor Inc. Devices, components and methods combining trench field plates with immobile electrostatic charge
JP5762689B2 (ja) 2010-02-26 2015-08-12 株式会社東芝 半導体装置
TWI407564B (zh) * 2010-06-07 2013-09-01 科軒微電子股份有限公司 具有溝槽底部多晶矽結構之功率半導體及其製造方法
JP5580150B2 (ja) 2010-09-09 2014-08-27 株式会社東芝 半導体装置
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US9853140B2 (en) 2012-12-31 2017-12-26 Vishay-Siliconix Adaptive charge balanced MOSFET techniques

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11721732B2 (en) 2021-08-18 2023-08-08 Kabushiki Kaisha Toshiba Semiconductor device with control electrodes provided in trenches of different widths

Also Published As

Publication number Publication date
JP2016506082A (ja) 2016-02-25
US9853140B2 (en) 2017-12-26
WO2014106127A1 (en) 2014-07-03
KR20150103017A (ko) 2015-09-09
CN105027290A (zh) 2015-11-04
US20140183624A1 (en) 2014-07-03
KR101786278B1 (ko) 2017-10-17
EP2939272A4 (en) 2016-09-14
CN105027290B (zh) 2018-08-10
EP2939272A1 (en) 2015-11-04
EP2939272B1 (en) 2021-02-03

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