JP6186380B2 - 半導体層に対するオーミックコンタクトを含むデバイスヘテロ構造を形成することを含む方法および半導体層に対するオーミックコンタクトを含むデバイスヘテロ構造を含むデバイス - Google Patents
半導体層に対するオーミックコンタクトを含むデバイスヘテロ構造を形成することを含む方法および半導体層に対するオーミックコンタクトを含むデバイスヘテロ構造を含むデバイス Download PDFInfo
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- JP6186380B2 JP6186380B2 JP2014558905A JP2014558905A JP6186380B2 JP 6186380 B2 JP6186380 B2 JP 6186380B2 JP 2014558905 A JP2014558905 A JP 2014558905A JP 2014558905 A JP2014558905 A JP 2014558905A JP 6186380 B2 JP6186380 B2 JP 6186380B2
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
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Description
本出願は、同時係属中の「Ohmic Contact to Semiconductors and the Process of Producing the Same」の名称において2012年2月23日に出願された米国特許仮出願第61/602,155号の恩典を主張するものであり、なお、当該仮出願は、参照により本明細書に組み入れられる。
Claims (16)
- 半導体層をエッチングすることなく、デバイスヘテロ構造の一セットの半導体層において半導体層に対するオーミックコンタクトを含む前記デバイスヘテロ構造を形成することを含む方法であって、
前記デバイスへテロ構造を形成することは、
前記半導体層の表面上の前記オーミックコンタクトに対応する一セットのコンタクト領域上にマスキング材料を適用し、
前記マスキング材料を適用した後に、前記半導体層の表面の一セットのマスクされていない領域を覆う隆起領域を形成し、
前記一セットのコンタクト領域上に一セットの高導電性半導体層を形成し、
前記隆起領域の形成後に前記一セットの高導電性半導体層上にオーミックコンタクトを形成することを含み、
前記一セットの高導電性半導体層を形成することは、前記一セットのコンタクト領域からの距離に関して前記一セットの高導電性半導体層を形成する材料の少なくとも1つの元素のモル分率に傾斜を持たせることを含み、
前記オーミックコンタクトを形成することは、デバイスヘテロ構造に前記一セットの半導体層のいずれかを形成する材料の品質が損なわれる温度範囲よりも低い処理温度において実施されることを特徴とする方法。 - 前記オーミックコンタクトを形成する前に、前記隆起領域上に少なくとも1つの追加の半導体層を形成することをさらに含む、請求項1に記載の方法。
- 前記オーミックコンタクトを形成する前に、前記一セットのコンタクト領域のそれぞれから前記マスキング材料を除去することをさらに含む、請求項1に記載の方法。
- 前記オーミックコンタクトを形成する前に、前記一セットのマスクされていない領域に対応する前記デバイスヘテロ構造の表面にマスキング材料を適用することをさらに含む、請求項1に記載の方法。
- 前記一セットの高導電性半導体層がIII族窒化物材料で形成され、
前記一セットの高導電性半導体層が、前記半導体層と前記一セットの高導電性半導体層との界面において前記半導体層と格子整合される、請求項1に記載の方法。 - 前記一セットの高導電性半導体層を形成することが、前記一セットの高導電性半導体層をデルタドーピングする工程を含む、請求項1に記載の方法。
- 前記一セットの高導電性半導体層が、III族窒化物材料で形成され、
前記傾斜を持たせることが、前記一セットのコンタクト領域から離れる方向にアルミニウムのモル分率が増加することである、請求項1に記載の方法。 - 前記傾斜を持たせることが、前記一セットのコンタクト領域から離れる方向にインジウムのモル分率が減少することである、請求項7に記載の方法。
- 前記一セットのコンタクト領域と前記一セットの高導電性半導体層との界面において、前記アルミニウムのモル分率が0である、請求項7または8に記載の方法。
- 前記傾斜が、前記一セットのコンタクト領域において逆キャリアの蓄積の誘起を避けるように構成される、請求項1に記載の方法。
- 前記デバイスヘテロ構造の前記一セットの半導体層がIII族窒化物材料で形成される、請求項1に記載の方法。
- デバイスヘテロ構造の一セットの半導体層において半導体層に対するオーミックコンタクトを含むデバイスヘテロ構造を含むデバイスであって、
前記オーミックコンタクトが、前記半導体層の一セットのコンタクト領域上に形成された一セットの高導電性半導体層を含み、
前記一セットの高導電性半導体層が、前記半導体層と前記一セットの高導電性半導体層との界面において前記半導体層と格子整合されることを特徴とするデバイス。 - 前記一セットの高導電性半導体層がIII族窒化物材料で形成される、請求項12に記載のデバイス。
- 前記一セットの高導電性半導体層がデルタドーピングされる、請求項12に記載のデバイス。
- 前記一セットの高導電性半導体層が、前記一セットのコンタクト領域からの距離に関して前記一セットの高導電性半導体層を形成する材料の少なくとも1つの元素の傾斜したモル分率を有する、請求項12に記載のデバイス。
- 前記傾斜が、前記一セットのコンタクト領域での逆キャリアの蓄積の誘起を避けるように構成される、請求項15に記載のデバイス。
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PCT/US2013/027496 WO2013126828A1 (en) | 2012-02-23 | 2013-02-22 | Ohmic contact to semiconductor |
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