JP6169250B2 - Power semiconductor device - Google Patents

Power semiconductor device Download PDF

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JP6169250B2
JP6169250B2 JP2016506087A JP2016506087A JP6169250B2 JP 6169250 B2 JP6169250 B2 JP 6169250B2 JP 2016506087 A JP2016506087 A JP 2016506087A JP 2016506087 A JP2016506087 A JP 2016506087A JP 6169250 B2 JP6169250 B2 JP 6169250B2
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electrode
pole
semiconductor element
heat sink
semiconductor device
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JPWO2015133024A1 (en
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護 神蔵
護 神蔵
慶多 ▲高▼橋
慶多 ▲高▼橋
延是 春名
延是 春名
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Mitsubishi Electric Corp
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
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Description

この発明は、直流から交流、あるいは交流から直流に電力を変換する電力変換装置に用いる電力用半導体装置に関するものである。   The present invention relates to a power semiconductor device used in a power conversion device that converts power from direct current to alternating current or from alternating current to direct current.

半導体素子を用いた電力用半導体装置においては、半導体素子の片面が、薄い絶縁体の表面に形成された導電体の薄板である表面電極に接合され、薄い絶縁体を金属のヒートシンクに接触させて半導体素子の冷却経路を確保することが多い。そして、半導体素子の製造プロセス上、ＩＧＢＴの場合はコレクタ側、ＭＯＳＦＥＴの場合はドレイン側、ダイオードの場合はカソード側が表面電極と接合されることが一般的である。このため電力用半導体装置として上アームの半導体素子と下アームの半導体素子を直列接続したセミブリッジ回路が構成されている場合、セミブリッジ回路の正極側は表面電極に接合されることから、正極側とヒートシンク間に大きい浮遊容量が生じる。一方でセミブリッジ回路の負極側は表面電極に接合されず、ヒートシンクからは離れた位置にあるため、負極側とヒートシンク間に生じる浮遊容量は正極側とヒートシンク間の浮遊容量に比べて微小となる。よって、半導体素子とヒートシンク間の浮遊容量は正極側と負極側で不平衡になってノイズが増加してしまい、しばしば不要放射の原因となる。   In a power semiconductor device using a semiconductor element, one surface of the semiconductor element is bonded to a surface electrode which is a thin plate of a conductor formed on the surface of a thin insulator, and the thin insulator is brought into contact with a metal heat sink. In many cases, a cooling path of the semiconductor element is secured. In the manufacturing process of the semiconductor element, the collector side in the case of IGBT, the drain side in the case of MOSFET, and the cathode side in the case of a diode are generally joined to the surface electrode. For this reason, when a semi-bridge circuit in which an upper-arm semiconductor element and a lower-arm semiconductor element are connected in series as a power semiconductor device is configured, the positive side of the semi-bridge circuit is joined to the surface electrode. A large stray capacitance is generated between the heat sink and the heat sink. On the other hand, since the negative side of the semi-bridge circuit is not joined to the surface electrode and is away from the heat sink, the stray capacitance generated between the negative side and the heat sink is smaller than the stray capacitance between the positive side and the heat sink. . Therefore, the stray capacitance between the semiconductor element and the heat sink becomes unbalanced on the positive electrode side and the negative electrode side, increasing noise, and often causing unnecessary radiation.

このような課題に対し、例えば特許文献１では、半導体素子の両側をヒートシンクで覆った構造とし、絶縁基板を挟んで正極側および負極側の回路の金属パターンとヒートシンクとでコンデンサを形成することで、浮遊容量の平衡化を図りノイズを抑制している。   For example, Patent Document 1 discloses a structure in which both sides of a semiconductor element are covered with a heat sink, and a capacitor is formed by a metal pattern of a positive side and negative side circuit and a heat sink with an insulating substrate interposed therebetween. The noise is suppressed by balancing the stray capacitance.

また、正極側端子および負極側端子から伸ばした配線板の間に、ヒートシンクに電気的に接続された電極を設けることで、正極側端子および負極側端子と、ヒートシンクに電気的に接続された電極との間でコンデンサを形成することで、浮遊容量の平衡化を図りノイズを抑制しているものもある（たとえば特許文献２）。   Also, by providing an electrode electrically connected to the heat sink between the wiring board extended from the positive electrode side terminal and the negative electrode side terminal, the positive electrode side terminal and the negative electrode side terminal and the electrode electrically connected to the heat sink In some cases, a capacitor is formed between them to balance the stray capacitance and suppress noise (for example, Patent Document 2).

特開２０１３−１５０４８８号公報JP 2013-150488 A 特開２０１０−２５１７５０号公報JP 2010-251750 A

特許文献１の電力用半導体装置にあっては、正極側および負極側の金属パターンと半導体素子の両側ヒートシンクで半導体素子を両面冷却するヒートシンクを用いなければならず、片面冷却のヒートシンクには適用できない。   In the power semiconductor device of Patent Document 1, it is necessary to use a heat sink that cools both sides of the semiconductor element with the metal pattern on the positive electrode side and the negative electrode side and the heat sink on both sides of the semiconductor element, and it cannot be applied to a heat sink that is cooled on one side. .

また、特許文献２の電力用半導体装置にあっては、半導体素子と正極側端子、負極側端子から伸ばした配線板を使うため、配線板の距離が構造上長くなって寄生インダクタンスが生じるためコンデンサとして作用しにくく、ノイズを低減しにくい。   Further, in the power semiconductor device disclosed in Patent Document 2, since a wiring board extended from the semiconductor element, the positive terminal, and the negative terminal is used, the distance between the wiring boards is structurally long and parasitic inductance is generated. As a result, it is difficult to reduce noise.

この発明は、上記のような問題点を解決するためになされたものであり、片面冷却のヒートシンクを用いた電力用半導体装置にも適用することができ、かつ、簡単な構成で寄生インダクタンスを極力低減できて、効果的にノイズを抑制できる電力用半導体装置を得ることを目的としている。   The present invention has been made in order to solve the above-described problems, and can be applied to a power semiconductor device using a single-side cooled heat sink, and can reduce parasitic inductance as much as possible with a simple configuration. An object of the present invention is to obtain a power semiconductor device that can reduce noise and effectively suppress noise.

この発明は、片面に第一極側表面電極と中間側表面電極が形成された絶縁基板と、第一極側表面電極に第一極側の主極が接合された第一極側半導体素子と中間側表面電極に第一極側の主極が接合された第二極側半導体素子と、中間側表面電極と第一極側半導体素子の第二極側の主極を接続する中間側導体と、絶縁基板の第一極側表面電極が形成された面とは反対側の面に接合されたヒートシンクと、第一極側半導体素子、第二極側半導体素子、絶縁基板、および中間側導体を封止する封止樹脂と、第二極側半導体素子の第二極側の主極に接続され封止樹脂の外側に延在する板状の第二極側端子を備えた電力用半導体装置において、ヒートシンクに接続され、封止樹脂、または積層コンデンサを介して第二極側端子と対向配置された調整用電極を設けたものである。 The present invention relates to an insulating substrate having a first pole-side surface electrode and an intermediate-side surface electrode formed on one side, a first pole-side semiconductor element having a first pole-side main electrode joined to a first pole-side surface electrode, A second pole-side semiconductor element in which a first pole-side main electrode is joined to the intermediate-side surface electrode; and an intermediate-side conductor connecting the intermediate-side surface electrode and the second pole-side main pole of the first pole-side semiconductor element; A heat sink joined to a surface of the insulating substrate opposite to the surface on which the first electrode surface electrode is formed, a first electrode semiconductor element, a second electrode semiconductor element, an insulating substrate, and an intermediate conductor; In a power semiconductor device comprising: a sealing resin to be sealed; and a plate-like second pole side terminal connected to the second pole side main electrode of the second pole side semiconductor element and extending to the outside of the sealing resin , is connected to the heat sink, the second polar terminal and oppositely disposed adjusting electrode through the sealing resin or a multilayer capacitor, It is those provided.

この発明によれば、簡単な構成で寄生インダクタンスを極力低減でき、効果的にノイズを抑制できる電力用半導体装置を得ることができる。   According to the present invention, it is possible to obtain a power semiconductor device capable of reducing parasitic inductance as much as possible with a simple configuration and effectively suppressing noise.

この発明の実施の形態１による電力用半導体装置の実装状態を示す斜視図である。It is a perspective view which shows the mounting state of the power semiconductor device by Embodiment 1 of this invention. この発明の電力用半導体装置を適用する電力変換装置の一例を示す回路図である。It is a circuit diagram which shows an example of the power converter device to which the power semiconductor device of this invention is applied. この発明の実施の形態１による電力用半導体装置の要部の構成を示す上面図である。It is a top view which shows the structure of the principal part of the power semiconductor device by Embodiment 1 of this invention. この発明の実施の形態１による電力用半導体装置の構成を示す側面断面図である。1 is a side sectional view showing a configuration of a power semiconductor device according to a first embodiment of the present invention. この発明の実施の形態１による電力用半導体装置の作用を説明するための等価回路図である。It is an equivalent circuit diagram for demonstrating the effect | action of the power semiconductor device by Embodiment 1 of this invention. この発明の実施の形態１による電力用半導体装置の別の構成の実装状態を示す斜視図である。It is a perspective view which shows the mounting state of another structure of the power semiconductor device by Embodiment 1 of this invention. この発明の実施の形態２による電力用半導体装置の構成を示す側面断面図である。It is side surface sectional drawing which shows the structure of the power semiconductor device by Embodiment 2 of this invention. この発明の実施の形態２による電力用半導体装置の別の構成を示す側面断面図である。It is side surface sectional drawing which shows another structure of the power semiconductor device by Embodiment 2 of this invention. この発明の実施の形態３による電力用半導体装置の構成を示す側面断面図である。It is side surface sectional drawing which shows the structure of the power semiconductor device by Embodiment 3 of this invention. この発明の実施の形態４による電力用半導体装置の構成を示す側面断面図である。It is side surface sectional drawing which shows the structure of the power semiconductor device by Embodiment 4 of this invention. この発明の実施の形態５による電力用半導体装置の作用を説明するための等価回路図である。It is an equivalent circuit diagram for demonstrating the effect | action of the power semiconductor device by Embodiment 5 of this invention.

実施の形態１．
図１は、本発明の実施の形態１による電力用半導体装置の実装状態を示す斜視図である。図２は、本発明の電力用半導体装置を適用する電力変換装置の一例としてのインバータを示す回路図である。ここでは半導体素子としてＭＯＳＦＥＴを使用しているとする。図２において、電力変換装置１１は上アームの半導体素子１２ａ、１２ｂ、１２ｃおよび下アームの半導体素子１３ａ、１３ｂ、１３ｃを備えており、上アームの半導体素子１２ａと下アームの半導体素子１３ａを直列接続した第一のセミブリッジ回路、上アームの半導体素子１２ｂと下アームの半導体素子１３ｂを直列接続した第二のセミブリッジ回路、上アームの半導体素子１２ｃと下アームの半導体素子１３ｃを直列接続した第三のセミブリッジ回路を並列接続した構成となっている。上アームの半導体素子１２ａ〜１２ｃにはそれぞれ並列に上アームのダイオード１７ａ〜１７ｃが接続されており、下アームの半導体素子１３ａ〜１３ｃにはそれぞれ並列に下アームのダイオード１８ａ〜１８ｃが接続されている。上アームの半導体素子のドレイン側は直流電源１４および平滑用コンデンサ１５の正極側（図２中Ｐで示す）に接続され、下アームの半導体素子のソース側は直流電源１４および平滑用コンデンサ１５の負極側（図２中Ｍで示す）に接続される。また、上アームの半導体素子と下アームの半導体素子の接続部（図２中Ｃで示す。中間側とも称する）はモータ１６に接続される。Embodiment 1 FIG.
FIG. 1 is a perspective view showing a mounted state of the power semiconductor device according to the first embodiment of the present invention. FIG. 2 is a circuit diagram showing an inverter as an example of a power conversion device to which the power semiconductor device of the present invention is applied. Here, it is assumed that a MOSFET is used as the semiconductor element. In FIG. 2, the power conversion apparatus 11 includes upper arm semiconductor elements 12a, 12b, and 12c and lower arm semiconductor elements 13a, 13b, and 13c. The upper arm semiconductor element 12a and the lower arm semiconductor element 13a are connected in series. First semi-bridge circuit connected, second semi-bridge circuit in which upper arm semiconductor element 12b and lower arm semiconductor element 13b are connected in series, upper arm semiconductor element 12c and lower arm semiconductor element 13c are connected in series The third semi-bridge circuit is connected in parallel. Upper arm diodes 17a to 17c are connected in parallel to the upper arm semiconductor elements 12a to 12c, respectively, and lower arm diodes 18a to 18c are connected in parallel to the lower arm semiconductor elements 13a to 13c, respectively. Yes. The drain side of the upper arm semiconductor element is connected to the DC power supply 14 and the positive side of the smoothing capacitor 15 (indicated by P in FIG. 2), and the source side of the lower arm semiconductor element is connected to the DC power supply 14 and the smoothing capacitor 15. Connected to the negative electrode side (indicated by M in FIG. 2). A connecting portion (indicated by C in FIG. 2, also referred to as an intermediate side) of the upper arm semiconductor element and the lower arm semiconductor element is connected to the motor 16.

ここでは３個のセミブリッジ回路を並列接続した回路構成を示したが、本発明はセミブリッジ回路の並列接続数にかかわらず適用することができる。また、ここでは半導体素子としてＭＯＳＦＥＴの例を示しているが、ＩＧＢＴ、サイリスタなどＭＯＳＦＥＴ以外の半導体素子を用いる場合も適用可能である。また、ここでは電力変換装置としてインバータを例に挙げたが、セミブリッジ回路を有するＤＣＤＣコンバータ回路やダイオードをブリッジ接続した整流回路に対しても本発明を適用可能である。なお、本願では、ＭＯＳＦＥＴのドレインや、ＩＧＢＴのコレクタなど、電圧の高い側に接続される極を正側の主極、ＭＯＳＦＥＴのソースや、ＩＧＢＴのエミッタなど、電圧の低い側に接続される極を負側の主極と呼ぶこととする。   Although a circuit configuration in which three semi-bridge circuits are connected in parallel is shown here, the present invention can be applied regardless of the number of semi-bridge circuits connected in parallel. In addition, although an example of a MOSFET is shown here as a semiconductor element, a semiconductor element other than a MOSFET such as an IGBT or a thyristor is also applicable. In addition, although an inverter is exemplified here as the power converter, the present invention can also be applied to a DCDC converter circuit having a semi-bridge circuit and a rectifier circuit in which diodes are bridge-connected. In the present application, the pole connected to the high voltage side, such as the drain of the MOSFET or the collector of the IGBT, is the main pole on the positive side, and the pole connected to the low voltage side, such as the source of the MOSFET or the emitter of the IGBT. Is called the negative main pole.

電力変換装置１１の各セミブリッジ回路は複数の半導体を備えた半導体モジュールで構成されている。図１に示す本発明の実施の形態１による電力用半導体装置は、図２における１相分の上アームの半導体素子と下アームの半導体素子を直列接続した構造となっている。ヒートシンク５の上に半導体モジュール１が実装され、半導体モジュール１は正極側端子２、負極側端子３、中間側端子４を備え、各端子はモジュール内からモジュール外に引き出されている。そして、ヒートシンク５に電気的に接続された調整用電極６と板状の負極側端子３の間でコンデンサを形成している。   Each semi-bridge circuit of the power converter 11 includes a semiconductor module including a plurality of semiconductors. The power semiconductor device according to the first embodiment of the present invention shown in FIG. 1 has a structure in which the upper-arm semiconductor element and the lower-arm semiconductor element for one phase in FIG. 2 are connected in series. A semiconductor module 1 is mounted on a heat sink 5, and the semiconductor module 1 includes a positive terminal 2, a negative terminal 3, and an intermediate terminal 4, and each terminal is drawn out from the module to the outside of the module. A capacitor is formed between the adjustment electrode 6 electrically connected to the heat sink 5 and the plate-like negative electrode side terminal 3.

図３は本発明の実施の形態１による電力用半導体装置の要部の内部構成を示す上面図である。図３では、後述する封止樹脂２５および中間側導体２０を取り除いた状態で下アームの半導体素子１３の部分のみを示している。図３以降では、上アームの半導体素子を正極側半導体素子１２、下アームの半導体素子を負極側半導体素子１３と表記する。図４は図１のＡ−Ａ線を含む面における断面を示す側面断面図である。図５は本発明の電力用半導体装置におけるセミブリッジ回路の構成における等価回路図である。図４に示すように正極側半導体素子１２は正側の主極が正極側表面電極８の上に接合され、負極側半導体素子１３は正側の主極が中間側表面電極９の上に接合されている。正極側端子２（図４には現れていない）は正極側表面電極８に接続され、負極側端子３は負極側半導体素子１３の負側の主極に接続され、中間側導体２０は中間側表面電極９と正極側半導体素子１２の負側の主極との間を接続する。中間側端子４は中間側導体２０と電気的に接続されている。正極側表面電極８および中間側表面電極９は絶縁基板１０の片面に形成されており、絶縁基板１０を介してヒートシンク５と接触している。このように電力用半導体の場合、冷却経路を確保するため薄い絶縁基板を介して表面電極をヒートシンクと接触させることが一般的である。また、半導体素子の製造プロセス上、ＭＯＳＦＥＴの場合はドレイン側（ＩＧＢＴの場合はコレクタ側、ダイオードの場合はカソード側）のように正側の主極が表面電極と接合されることが一般的なため、通常絶縁基板１０の表面には負極側の表面電極は形成されていない。半導体モジュール１は、表面電極に接合された半導体素子、絶縁基板、中間側導体などを封止樹脂２５で封止してモジュールが構成されている。   FIG. 3 is a top view showing an internal configuration of a main part of the power semiconductor device according to the first embodiment of the present invention. FIG. 3 shows only the semiconductor element 13 portion of the lower arm in a state in which the sealing resin 25 and the intermediate conductor 20 described later are removed. In FIG. 3 and subsequent figures, the upper arm semiconductor element is referred to as a positive electrode side semiconductor element 12, and the lower arm semiconductor element is referred to as a negative electrode side semiconductor element 13. 4 is a side cross-sectional view showing a cross section in a plane including the AA line of FIG. FIG. 5 is an equivalent circuit diagram in the configuration of the semi-bridge circuit in the power semiconductor device of the present invention. As shown in FIG. 4, the positive-side semiconductor element 12 has a positive main pole bonded to the positive-side surface electrode 8, and the negative-side semiconductor element 13 has a positive-side main electrode bonded to the intermediate-side surface electrode 9. Has been. The positive terminal 2 (not shown in FIG. 4) is connected to the positive surface electrode 8, the negative terminal 3 is connected to the negative main electrode of the negative semiconductor element 13, and the intermediate conductor 20 is on the intermediate side The surface electrode 9 is connected to the negative main electrode of the positive-side semiconductor element 12. The intermediate side terminal 4 is electrically connected to the intermediate side conductor 20. The positive surface electrode 8 and the intermediate surface electrode 9 are formed on one side of the insulating substrate 10 and are in contact with the heat sink 5 through the insulating substrate 10. As described above, in the case of a power semiconductor, in order to secure a cooling path, a surface electrode is generally brought into contact with a heat sink through a thin insulating substrate. In addition, in the process of manufacturing a semiconductor device, it is common that the main electrode on the positive side is joined to the surface electrode as in the drain side in the case of MOSFET (the collector side in the case of IGBT, the cathode side in the case of diode). Therefore, the surface electrode on the negative electrode side is usually not formed on the surface of the insulating substrate 10. The semiconductor module 1 is configured by sealing a semiconductor element, an insulating substrate, an intermediate conductor, and the like bonded to a surface electrode with a sealing resin 25.

この構成では、負極側端子３と、ヒートシンク５に電気的に接続した調整用電極６との間で浮遊容量が形成される。調整用電極６とヒートシンク５の接続方法として、はんだを用いて接続してもよいが、ねじによる締結や圧着等によりはんだを用いずに接続してもよい。図５の等価回路図に示すコンデンサ３２は、調整用電極６と負極側端子３により形成される浮遊容量３２（調整用浮遊容量と称する）を示している。またコンデンサ３０は正極側表面電極８とヒートシンク５間に生じる浮遊容量３０（正極側浮遊容量）を示している。さらに、コンデンサ３１は、主に負極側半導体素子１３の正側の主極が接続されている中間側表面電極９とヒートシンク５とで形成される浮遊容量３１（中間側浮遊容量）を示している。ここで、コンデンサ３２の容量、すなわち調整用電極６と負極側端子３とにより形成される調整用浮遊容量３２と、コンデンサ３０の容量、すなわち正極側表面電極８とヒートシンク５間に生じる浮遊容量３０との差異が、例えば一般的なコンデンサの静電容量の誤差である±１０％以内となるように調整用電極６が設けられる。   In this configuration, a stray capacitance is formed between the negative electrode side terminal 3 and the adjustment electrode 6 electrically connected to the heat sink 5. As a method of connecting the adjustment electrode 6 and the heat sink 5, the connection may be made using solder, but the connection may be made without using solder by fastening with screws or pressure bonding. A capacitor 32 shown in the equivalent circuit diagram of FIG. 5 represents a stray capacitance 32 (referred to as a stray capacitance for adjustment) formed by the adjustment electrode 6 and the negative electrode side terminal 3. A capacitor 30 indicates a stray capacitance 30 (positive side stray capacitance) generated between the positive electrode surface electrode 8 and the heat sink 5. Further, the capacitor 31 indicates a stray capacitance 31 (intermediate stray capacitance) formed by the intermediate surface electrode 9 and the heat sink 5 to which the positive main electrode of the negative electrode side semiconductor element 13 is connected. . Here, the capacitance of the capacitor 32, that is, the adjustment stray capacitance 32 formed by the adjustment electrode 6 and the negative terminal 3, and the capacitance of the capacitor 30, that is, the stray capacitance 30 generated between the positive surface electrode 8 and the heat sink 5. The adjustment electrode 6 is provided so that the difference is within ± 10%, which is an error in capacitance of a general capacitor, for example.

図１および図４に示す構成では、調整用電極６は、負極側端子３との間で浮遊容量を形成するように板状の負極側端子３と対向する面を有し、半導体モジュール１の負極側端子３が伸びる方向と平行な側面で、負極側端子３に近い側の側面に沿ってヒートシンク５と接続されるように設けている。調整用電極６は、これに限らず図６に示すように、負極側端子３が設けられた側面とは反対側の側面から伸ばして、負極側端子３と対向する面を有するように設けても良い。さらに、調整用電極６は負極側端子３が設けられた側面から、負極側端子３と対向する面を有するように設けても良い。ヒートシンク５に電気的に接続され、負極側端子３と対向する面を有するように調整用電極６を設けることにより、調整用電極６と負極側端子３との間で浮遊容量が形成されるため、その幅や厚みに関わらず本発明の効果を得ることができる。ただし、調整用電極６の幅を負極側端子３の幅と同じかそれ以上にすることが好ましい。調整用電極６の幅をこのようにすることで、負極側端子３とヒートシンク５の間を低インダクタンスで接続することができ、本発明の効果を向上させることができる。   In the configuration shown in FIGS. 1 and 4, the adjustment electrode 6 has a surface facing the plate-like negative electrode side terminal 3 so as to form a stray capacitance with the negative electrode side terminal 3. It is provided so as to be connected to the heat sink 5 along the side surface close to the negative electrode side terminal 3 on the side surface parallel to the direction in which the negative electrode side terminal 3 extends. As shown in FIG. 6, the adjustment electrode 6 is provided so as to extend from the side surface opposite to the side surface on which the negative electrode side terminal 3 is provided and to have a surface facing the negative electrode side terminal 3. Also good. Further, the adjustment electrode 6 may be provided so as to have a surface facing the negative electrode side terminal 3 from the side surface where the negative electrode side terminal 3 is provided. A stray capacitance is formed between the adjustment electrode 6 and the negative terminal 3 by providing the adjustment electrode 6 so as to have a surface that is electrically connected to the heat sink 5 and faces the negative terminal 3. The effects of the present invention can be obtained regardless of the width and thickness. However, it is preferable that the width of the adjustment electrode 6 is equal to or larger than the width of the negative electrode side terminal 3. By making the width of the adjustment electrode 6 in this way, the negative electrode side terminal 3 and the heat sink 5 can be connected with low inductance, and the effect of the present invention can be improved.

本実施の形態１では、図２に示すような電力変換装置１１において、セミブリッジ回路は図１に示すような半導体モジュール１で構成され、図３、図４、図６に示すような調整用電極６を設けて負極側端子３とヒートシンク５との間で調整用浮遊容量３２としてのコンデンサを形成する。正極側表面電極８とヒートシンク５の間の正極側浮遊容量３０と調整用浮遊容量３２の容量の差が、好ましくは±１０％以内となるように調整用電極６を設ける。これにより、片面冷却のヒートシンクによる構成でも、浮遊容量を正極側と負極側で平衡化させ、浮遊容量がノイズ除去用の静電容量成分として作用することで放射ノイズ低減効果を発揮することができる。また、負極側端子から伸ばした配線板を用いていないため、特許文献２に記載されているような電力用半導体装置と比較して、寄生インダクタンスが低減された構造となっている。このように、調整用電極以外の追加部品を用いずに、浮遊容量を正極側と負極側で平衡化させて、浮遊容量をノイズ除去用の静電容量成分として作用させることで放射ノイズ低減効果を発揮することができる。   In the first embodiment, in the power converter 11 as shown in FIG. 2, the semi-bridge circuit is composed of the semiconductor module 1 as shown in FIG. 1, and for adjustment as shown in FIG. 3, FIG. 4, and FIG. An electrode 6 is provided to form a capacitor as the adjustment stray capacitance 32 between the negative electrode side terminal 3 and the heat sink 5. The adjustment electrode 6 is provided so that the difference in capacitance between the positive-side stray capacitance 30 and the adjustment stray capacitance 32 between the positive-surface electrode 8 and the heat sink 5 is preferably within ± 10%. As a result, even in a configuration using a single-sided cooling heat sink, the stray capacitance can be balanced between the positive electrode side and the negative electrode side, and the effect of reducing radiation noise can be exhibited by the stray capacitance acting as a capacitance component for noise removal. . Further, since a wiring board extended from the negative electrode side terminal is not used, the parasitic inductance is reduced as compared with the power semiconductor device described in Patent Document 2. In this way, without using additional components other than the adjustment electrode, the stray capacitance is balanced on the positive electrode side and negative electrode side, and the stray capacitance acts as a capacitance component for noise removal, thereby reducing radiation noise. Can be demonstrated.

実施の形態２．
図７は、本発明の実施の形態２による電力用半導体装置の構成を示す側面断面図である。調整用電極６は図７に示すように封止樹脂２５の中に設けてもよい。この構成は、負極側端子３の上まで封止樹脂２５を充填した後、負極側のみに調整用電極６を設置し、再度、封止樹脂２５を半導体モジュール１の中に充填することで、製造が可能である。図７では、調整用電極６は、半導体モジュール１の負極側端子３が伸びる方向と平行な側面で、かつ、負極側端子３に近い側の側面に沿わせてヒートシンク５と接続されているが、調整用電極６は負極側端子が設けられた側面に沿わせて、あるいは中間側端子４が設けられた側面に沿わせてヒートシンク５と接続するように設けても良い。調整用電極６は、ヒートシンク５と接続し、負極側端子３と対向する面を有するように設ければ良い。調整用電極６とヒートシンク５の接続方法として、はんだを用いて接続してもよいが、ねじによる締結や圧着等によりはんだを用いずに接続してもよい。調整用電極６と負極側端子３で形成されるコンデンサの浮遊容量３２は正極側表面電極８とヒートシンク５間に生じる正極側浮遊容量３０との差異が±１０％以内（一般的なコンデンサの静電容量の誤差）となるように設ける。Embodiment 2. FIG.
FIG. 7 is a side sectional view showing the configuration of the power semiconductor device according to the second embodiment of the present invention. The adjustment electrode 6 may be provided in the sealing resin 25 as shown in FIG. In this configuration, after the sealing resin 25 is filled up to the negative electrode side terminal 3, the adjustment electrode 6 is installed only on the negative electrode side, and the sealing resin 25 is filled in the semiconductor module 1 again. Manufacturing is possible. In FIG. 7, the adjustment electrode 6 is connected to the heat sink 5 along a side surface parallel to the direction in which the negative electrode side terminal 3 of the semiconductor module 1 extends and close to the negative electrode side terminal 3. The adjustment electrode 6 may be provided so as to be connected to the heat sink 5 along the side surface on which the negative terminal is provided or along the side surface on which the intermediate terminal 4 is provided. The adjustment electrode 6 may be provided so as to have a surface that is connected to the heat sink 5 and faces the negative terminal 3. As a method of connecting the adjustment electrode 6 and the heat sink 5, the connection may be made using solder, but the connection may be made without using solder by fastening with screws or pressure bonding. The stray capacitance 32 of the capacitor formed by the adjustment electrode 6 and the negative electrode side terminal 3 is within ± 10% of the difference between the positive electrode side stray capacitance 30 generated between the positive electrode surface electrode 8 and the heat sink 5 (the capacitance of a general capacitor) (Electric capacity error).

図８は、本発明の実施の形態２による電力用半導体装置の別の構成を示す側面断面図である。図８に示すように、調整用電極６全体が封止樹脂２５で覆われるようにしてもよい。本実施の形態２による電力用半導体装置の構成によれば、実施の形態１のような調整用電極６を半導体モジュール１の外に設けた場合に比べて、調整用電極６と負極側端子３の距離を近づけることができるため、より小さな面積の調整用電極６を用いて、浮遊容量を正極側と負極側で平衡化させることができ、浮遊容量をノイズ除去用の静電容量成分として作用させることで放射ノイズ低減効果を発揮することができる。   FIG. 8 is a side sectional view showing another configuration of the power semiconductor device according to the second embodiment of the present invention. As shown in FIG. 8, the entire adjustment electrode 6 may be covered with a sealing resin 25. According to the configuration of the power semiconductor device according to the second embodiment, the adjustment electrode 6 and the negative electrode side terminal 3 are compared with the case where the adjustment electrode 6 as in the first embodiment is provided outside the semiconductor module 1. Therefore, the stray capacitance can be balanced between the positive electrode side and the negative electrode side using the adjustment electrode 6 having a smaller area, and the stray capacitance acts as a capacitance component for noise removal. By doing so, a radiation noise reduction effect can be exhibited.

実施の形態３．
図９は、本発明の実施の形態３による電力用半導体装置の構成を示す側面断面図である。図９に示すように調整用電極６と負極側端子３の間に、封止樹脂２５と異なる誘電率を持つ誘電体２２を充填してもよい。例えば誘電体２２として高誘電率系のチタン酸バリウムや低誘電率系のアルミナ、酸化チタンやジルコン酸カルシウムなどの材料を用いてもよい。この構成は、負極側端子３の上まで封止樹脂２５を充填した後、別途形成した誘電体２２を負極側のみに設置し、再度、封止樹脂２５を半導体モジュール１の中に充填することで、製造が可能である。調整用電極６をヒートシンク５に接続する方向は、実施の形態１や実施の形態２で説明したいずれの方向でもよい。本実施の形態３においても、調整用電極６とヒートシンク５の接続方法として、はんだを用いて接続してもよいが、ねじによる締結や圧着等によりはんだを用いずに接続してもよい。調整用電極６と負極側端子３で形成されるコンデンサの浮遊容量３２は正極側表面電極８とヒートシンク５間に生じる正極側浮遊容量３０との差異が±１０％以内（一般的なコンデンサの静電容量の誤差）となるように設ける。Embodiment 3 FIG.
FIG. 9 is a side sectional view showing the configuration of the power semiconductor device according to the third embodiment of the present invention. As shown in FIG. 9, a dielectric 22 having a dielectric constant different from that of the sealing resin 25 may be filled between the adjustment electrode 6 and the negative electrode side terminal 3. For example, a material such as high dielectric constant type barium titanate, low dielectric constant type alumina, titanium oxide or calcium zirconate may be used as the dielectric 22. In this configuration, after the sealing resin 25 is filled up to the negative electrode side terminal 3, a separately formed dielectric 22 is placed only on the negative electrode side, and the sealing resin 25 is filled again into the semiconductor module 1. And can be manufactured. The direction in which the adjustment electrode 6 is connected to the heat sink 5 may be any direction described in the first embodiment or the second embodiment. Also in the third embodiment, the adjustment electrode 6 and the heat sink 5 may be connected using solder, but may be connected without using solder by fastening with screws or pressure bonding. The stray capacitance 32 of the capacitor formed by the adjustment electrode 6 and the negative electrode side terminal 3 is within ± 10% of the difference between the positive electrode side stray capacitance 30 generated between the positive electrode surface electrode 8 and the heat sink 5 (the capacitance of a general capacitor) (Electric capacity error).

この構成によれば、誘電体２２の誘電率を高くすることで、調整用電極６と負極側端子３の間が封止樹脂２５のみの場合に比べて、浮遊容量を正極側と負極側で平衡化させるのに必要な調整用電極６の面積が小さくてよく、より小さな調整用電極６によって、放射ノイズ低減効果を発揮することができる。   According to this configuration, by increasing the dielectric constant of the dielectric 22, the stray capacitance can be reduced between the positive electrode side and the negative electrode side as compared with the case where only the sealing resin 25 is provided between the adjustment electrode 6 and the negative electrode side terminal 3. The area of the adjustment electrode 6 required for balancing may be small, and the radiation noise reduction effect can be exhibited by the smaller adjustment electrode 6.

実施の形態４．
図１０は、本発明の実施の形態４による電力用半導体装置の構成を示す側面断面図である。図１０のように調整用電極６と負極側端子３の間に、いわゆる積層コンデンサのような積層構造２３を形成して、調整用電極６および積層構造２３、負極側端子３によって浮遊容量を形成してもよい。この構成は、負極側端子３の上まで封止樹脂２５を充填した後、別途形成した積層構造２３を負極側のみに設置し、再度、封止樹脂２５を半導体モジュール１の中に充填することで、製造が可能である。調整用電極６をヒートシンク５に接続する方向は、実施の形態１や実施の形態２で説明したいずれの方向でもよい。また、調整用電極６とヒートシンク５の接続方法として、はんだを用いて接続してもよいが、ねじによる締結や圧着等によりはんだを用いずに接続してもよい。調整用電極６と負極側端子３で形成されるコンデンサの浮遊容量３２は正極側表面電極８とヒートシンク５間に生じる正極側浮遊容量３０との差異が±１０％以内（一般的なコンデンサの静電容量の誤差）となるように設ける。Embodiment 4 FIG.
FIG. 10 is a side sectional view showing the configuration of the power semiconductor device according to the fourth embodiment of the present invention. As shown in FIG. 10, a multilayer structure 23 such as a so-called multilayer capacitor is formed between the adjustment electrode 6 and the negative electrode side terminal 3, and a stray capacitance is formed by the adjustment electrode 6, the multilayer structure 23, and the negative electrode side terminal 3. May be. In this configuration, after the sealing resin 25 is filled up to the negative electrode side terminal 3, a separately formed laminated structure 23 is installed only on the negative electrode side, and the sealing resin 25 is filled into the semiconductor module 1 again. And can be manufactured. The direction in which the adjustment electrode 6 is connected to the heat sink 5 may be any direction described in the first embodiment or the second embodiment. Further, as a method of connecting the adjustment electrode 6 and the heat sink 5, the connection may be made using solder, but the connection may be made without using solder by fastening with screws or pressure bonding. The stray capacitance 32 of the capacitor formed by the adjustment electrode 6 and the negative electrode side terminal 3 is within ± 10% of the difference between the positive electrode side stray capacitance 30 generated between the positive electrode surface electrode 8 and the heat sink 5 (the capacitance of a general capacitor) (Electric capacity error).

この構成によれば、積層構造２３を設けることで、調整用電極６と負極側端子３の間が封止樹脂２５のみの場合に比べて、浮遊容量を正極側と負極側で平衡化させるのに必要な調整用電極６の面積が小さくてよく、より小さな調整用電極６によって、放射ノイズ低減効果を発揮することができる。   According to this configuration, by providing the laminated structure 23, the stray capacitance can be balanced between the positive electrode side and the negative electrode side as compared with the case where only the sealing resin 25 is provided between the adjustment electrode 6 and the negative electrode side terminal 3. The area of the adjustment electrode 6 necessary for the adjustment may be small, and the radiation noise reduction effect can be exhibited by the smaller adjustment electrode 6.

実施の形態５．
以上の実施の形態１〜４では、符号１２の半導体素子が上アームの半導体素子、符号１３の半導体素子が下アームの半導体素子として説明した。本発明は、逆の構成にも適用可能である。すなわち図１１の等価回路図に示すように、符号１２の半導体素子が下アームの半導体素子、符号１３が上アームの半導体素子であってもよい。この場合、実施の形態１〜４で説明した正、負が全て逆になる。実施の形態１〜４の説明において、正を第一、負を第二と置き換え、第一が負、第二が正と読み替えれば、符号１２の半導体素子が下アームの半導体素子、符号１３が上アームの半導体素子の場合の説明となる。Embodiment 5. FIG.
In the first to fourth embodiments described above, the semiconductor element denoted by reference numeral 12 is an upper arm semiconductor element, and the semiconductor element denoted by reference numeral 13 is a lower arm semiconductor element. The present invention is also applicable to the reverse configuration. That is, as shown in the equivalent circuit diagram of FIG. 11, the semiconductor element denoted by reference numeral 12 may be a semiconductor element of the lower arm, and the semiconductor element denoted by reference numeral 13 may be the semiconductor element of the upper arm. In this case, all the positive and negative described in the first to fourth embodiments are reversed. In the description of the first to fourth embodiments, if the positive is replaced with the first, the negative is replaced with the second, the first is negative, and the second is positive, the semiconductor element of reference numeral 12 is the semiconductor element of the lower arm, reference numeral 13 Is an explanation for the semiconductor device of the upper arm.

すなわち、図１、図３、図４、および図６〜１０のいずれの図においても、それぞれの部材を、第一極側端子２、第二極側端子３、第一極側表面電極８、第一極側半導体素子１２、第二極側半導体素子１３と表現する。第一極が正、第二極が負、の場合は実施の形態１〜４の説明となる。これとは逆に、第一極が負、第二極が正の場合は、負極側半導体素子１２、正極側半導体素子１３、正極側端子３となる。この場合の電力用半導体装置の等価回路は図１１のようになり、図５の等価回路とは直列に接続される半導体素子１２と半導体素子１３の符号が逆になる。この構成においては、調整用電極６と正極側端子３の間に形成される調整用浮遊容量、すなわち図１１におけるコンデンサ３２の容量と、負極側表面電極８とヒートシンク５の間の浮遊容量（負極側浮遊容量。第一極側浮遊容量）、すなわち図１１におけるコンデンサ３０の容量とを平衡化することになる。このように、本発明は、半導体モジュール１の正、負がいずれの場合にも適用可能である。   That is, also in any figure of FIG.1, FIG.3, FIG.4 and FIGS. 6-10, each member is made into the 1st pole side terminal 2, the 2nd pole side terminal 3, the 1st pole side surface electrode 8, The first pole side semiconductor element 12 and the second pole side semiconductor element 13 are expressed. In the case where the first pole is positive and the second pole is negative, the description of Embodiments 1 to 4 is given. On the contrary, when the first pole is negative and the second pole is positive, the negative electrode side semiconductor element 12, the positive electrode side semiconductor element 13, and the positive electrode side terminal 3 are obtained. The equivalent circuit of the power semiconductor device in this case is as shown in FIG. 11, and the signs of the semiconductor element 12 and the semiconductor element 13 connected in series are opposite to those of the equivalent circuit of FIG. In this configuration, the adjustment stray capacitance formed between the adjustment electrode 6 and the positive electrode side terminal 3, that is, the capacitance of the capacitor 32 in FIG. 11, and the stray capacitance (negative electrode between the negative electrode surface electrode 8 and the heat sink 5). (Side stray capacitance. First pole side stray capacitance), that is, the capacitance of the capacitor 30 in FIG. Thus, the present invention can be applied to any case where the semiconductor module 1 is positive or negative.

なお、本発明は、その発明の範囲内において、各実施の形態を自由に組み合わせたり、各実施の形態を適宜、変形、あるいはその構成要件を省略したりすることが可能である。   In the present invention, it is possible to freely combine the respective embodiments within the scope of the invention, to appropriately modify the respective embodiments, or to omit the constituent elements thereof.

１ 半導体モジュール、２ 正極側端子（第一極側端子）、３ 負極側端子（第二極側端子）、４ 中間側端子、５ ヒートシンク、６ 調整用電極、８ 正極側表面電極（第一極側表面電極）、９ 中間側表面電極、１０ 絶縁基板、１１ 電力変換装置、１２、１２ａ〜１２ｃ 上アームの半導体素子（正極側半導体素子、第一極側半導体素子）、１３、１３ａ〜１３ｃ 下アームの半導体素子（負極側半導体素子、第二極側半導体素子）、１４ 直流電源、１５ 平滑用コンデンサ、１７、１７ａ〜１７ｃ 上アームのダイオード、１８、１８ａ〜１８ｃ 下アームのダイオード、２０ 中間側導体、２２ 誘電体、２３ 積層構造、２５ 封止樹脂、３０ 正極側浮遊容量（第一極側浮遊容量）、３１ 中間側浮遊容量、３２ 調整用浮遊容量。
DESCRIPTION OF SYMBOLS 1 Semiconductor module, 2 Positive electrode side terminal (1st pole side terminal), 3 Negative electrode side terminal (2nd pole side terminal), 4 Intermediate side terminal, 5 Heat sink, 6 Adjustment electrode, 8 Positive electrode side surface electrode (1st pole) Side surface electrode), 9 Middle surface electrode, 10 Insulating substrate , 11 Power conversion device, 12, 12a to 12c Upper arm semiconductor element (positive electrode side semiconductor element, first pole side semiconductor element), 13, 13a to 13c Arm semiconductor device (negative-side semiconductor device, second-pole semiconductor device), 14 DC power supply, 15 smoothing capacitor, 17, 17a to 17c upper arm diode, 18, 18a to 18c lower arm diode, 20 intermediate side Conductor, 22 dielectric, 23 laminated structure, 25 sealing resin, 30 positive side floating capacitance (first pole side floating capacitance), 31 intermediate side floating capacitance, 32 adjustment floating capacitance.

Claims (3)

片面に第一極側表面電極と中間側表面電極が形成された絶縁基板と、
前記第一極側表面電極に第一極側の主極が接合された第一極側半導体素子と中間側表面電極に第一極側の主極が接合された第二極側半導体素子と、
前記中間側表面電極と前記第一極側半導体素子の第二極側の主極を接続する中間側導体と、
前記絶縁基板の前記第一極側表面電極が形成された面とは反対側の面に接合されたヒートシンクと、
前記第一極側半導体素子、前記第二極側半導体素子、前記絶縁基板、および前記中間側導体を封止する封止樹脂と、
前記第二極側半導体素子の第二極側の主極に接続され前記封止樹脂の外側に延在する板状の第二極側端子を備えた電力用半導体装置において、
前記ヒートシンクに接続され、前記封止樹脂、または積層コンデンサを介して前記第二極側端子と対向配置された調整用電極を設けたことを特徴とする電力用半導体装置。 An insulating substrate having a first surface electrode and an intermediate surface electrode formed on one side;
A first pole-side semiconductor element in which a first pole-side main electrode is joined to the first pole-side surface electrode, and a second pole-side semiconductor element in which a first pole-side main pole is joined to the intermediate-side surface electrode;
An intermediate conductor connecting the intermediate surface electrode and the main pole on the second pole side of the first pole-side semiconductor element;
A heat sink bonded to the surface of the insulating substrate opposite to the surface on which the first electrode surface electrode is formed;
A sealing resin for sealing the first pole side semiconductor element, the second pole side semiconductor element, the insulating substrate, and the intermediate conductor;
In the power semiconductor device comprising a plate-like second pole side terminal connected to the main pole on the second pole side of the second pole side semiconductor element and extending outside the sealing resin,
A power semiconductor device comprising an adjustment electrode connected to the heat sink and disposed opposite to the second pole side terminal via the sealing resin or a multilayer capacitor . 前記第一極側表面電極と前記ヒートシンクとの間の浮遊容量の値と、前記調整用電極と前記第二極側端子との間の浮遊容量の値との差が１０％以内となるように前記調整用電極を設けたことを特徴とする請求項１に記載の電力用半導体装置。 The difference between the value of the stray capacitance between the first pole side surface electrode and the heat sink and the value of the stray capacitance between the adjustment electrode and the second pole side terminal is within 10%. The power semiconductor device according to claim 1 , wherein the adjustment electrode is provided. 前記調整用電極の少なくとも一部が前記封止樹脂で覆われたことを特徴とする請求項１または２に記載の電力用半導体装置。 The power semiconductor device according to claim 1 or 2, characterized in that at least a portion of the adjustment electrodes are covered with the sealing resin.
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Families Citing this family (11)

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Publication number Priority date Publication date Assignee Title
JP2017092177A (en) * 2015-11-06 2017-05-25 株式会社村田製作所 Shield structure of semiconductor device and method of manufacturing shield cover device
JP6488996B2 (en) * 2015-11-27 2019-03-27 株式会社デンソー Power converter
DE112017003455B4 (en) * 2016-07-08 2024-06-06 Mitsubishi Electric Corporation Semiconductor device and power conversion device
FR3062518B1 (en) * 2017-01-31 2019-04-19 Supergrid Institute ELECTRONIC POWER MODULE HAVING A DIELECTRIC SUPPORT
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US11588009B2 (en) * 2018-12-12 2023-02-21 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor device having a lid configured as an enclosure and a capacitive structure and method of manufacturing a semiconductor device
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DE102020207401A1 (en) * 2020-06-16 2021-12-16 Zf Friedrichshafen Ag Power module for operating an electric vehicle drive with improved heat conduction for control electronics
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WO2022050042A1 (en) * 2020-09-03 2022-03-10 株式会社村田製作所 Module

Family Cites Families (13)

* Cited by examiner, † Cited by third party
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JP3879150B2 (en) 1996-08-12 2007-02-07 株式会社デンソー Semiconductor device
JP4009901B2 (en) * 2002-05-31 2007-11-21 富士電機デバイステクノロジー株式会社 Power conversion circuit
JP2007305962A (en) * 2006-05-12 2007-11-22 Honda Motor Co Ltd Power semiconductor module
JP5352113B2 (en) * 2008-04-22 2013-11-27 トヨタ自動車株式会社 Inverter module
JP2010016941A (en) * 2008-07-02 2010-01-21 Nippon Soken Inc Power converter
TWI380550B (en) * 2008-07-30 2012-12-21 Inventec Corp Electronic apparatus having an electrostatic discharge guide
US7633143B1 (en) * 2008-09-22 2009-12-15 Powertech Technology Inc. Semiconductor package having plural chips side by side arranged on a leadframe
JP5002568B2 (en) * 2008-10-29 2012-08-15 日立オートモティブシステムズ株式会社 Power converter
DE102009017621B3 (en) * 2009-04-16 2010-08-19 Semikron Elektronik Gmbh & Co. Kg Device for reducing the noise emission in a power electronic system
JP5846929B2 (en) * 2012-01-23 2016-01-20 カルソニックカンセイ株式会社 Power semiconductor module
JP2013182964A (en) * 2012-03-01 2013-09-12 Honda Motor Co Ltd Semiconductor device
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