JP2013182964A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can perform at least one of improving a degree of freedom of layout and reducing noise.SOLUTION: A semiconductor device 16 comprises an insulation member 70 which is disposed between either one of a positive electrode terminal 60 or a negative electrode terminal 62 to which a first switching element 34 is connected, and a heat sink 80. The insulation member 70 comprises: a first region 90 which is made by adding a first additive to a base material 120; and a second region 92 which is made by adding a second additive to the base material 120. The first region 90 has an overlap with the first switching element 34 in a lamination direction of the insulation member 70 and the first switching element 34. A thermal conductivity of the first additive is more than that of the second additive. A dielectric constant of the second additive is more than that of the first additive.

Description

  The present invention relates to a semiconductor device. More particularly, the present invention relates to a semiconductor device including one or more series circuits in which a plurality of switching elements are connected in series.

  A semiconductor device having a series circuit in which a plurality of switching elements are connected in series has been developed. Examples of such a semiconductor device include an inverter, a converter, and a NAND flash memory (for example, Patent Document 1).

  Patent Document 1 aims to provide an inverter module of a power conversion device that can reduce conduction noise and radiation noise by suppressing common mode current (summary, [0010]). In order to achieve this object, Patent Document 1 discloses a switching arm series circuit for one phase (or multiple phases) in which a switching element and an antiparallel diode are used as one arm and two arms 5 and 6 are connected in series up and down. In the inverter module 25a of the power conversion device that is included in one package and the cooling copper base 1 is disposed outside the package, the area of the copper pattern 4 on which the lower arm 6 of the switching arm series circuit is mounted is The area is smaller than the area of the copper pattern 3 on which the upper arm 5 is mounted (summary).

JP 2007-181351 A

  As described above, in Patent Document 1, conduction is achieved by suppressing the common mode current by making the area of the copper pattern 4 on which the lower arm 6 is mounted smaller than the area of the copper pattern 3 on which the upper arm 5 is mounted. It is intended to reduce noise and radiated noise. However, in the configuration of Patent Document 1, there is a possibility that the degree of freedom in area (that is, layout) may be reduced, and there is room for further improvement in the method for reducing noise.

  The present invention has been made in consideration of such problems, and an object thereof is to provide a semiconductor device capable of at least one of improving the degree of freedom of layout and reducing noise.

  The semiconductor device according to the present invention includes one or a plurality of series circuits in which a first switching element and a second switching element are connected in series between a positive electrode terminal and a negative electrode terminal, and the first switching element is The semiconductor device is joined to the positive terminal or the negative terminal, and the semiconductor device includes an insulating member disposed between a terminal of the positive terminal or the negative terminal to which the first switching element is joined and a heat sink, The insulating member includes a first region in which a first additive is added to a predetermined base material, and a second region in which a second additive is added to the base material, and the first region includes the insulating member. And the first switching element in the stacking direction of the first switching element, the thermal conductivity of the first additive is greater than the thermal conductivity of the second additive, the second addition The dielectric constant of, and greater than the dielectric constant of the first additive.

  According to the present invention, it is possible to improve the flexibility of layout or suppress radiation noise and improve the heat dissipation of the first switching element.

  That is, according to the present invention, the dielectric constant of the second region is made larger than that of the first region overlapping the first switching element in the stacking direction. For this reason, for example, it is possible to increase the stray capacitance at the positive electrode terminal or the negative electrode terminal as compared with a configuration in which the insulating member is formed only by adding the first additive to a predetermined base material.

  Therefore, for example, when the first switching element is joined to the positive terminal, the stray capacitance at the positive terminal can be increased without making the area of the output terminal smaller than the area of the positive terminal. Alternatively, instead of making the area of the output terminal smaller than the area of the positive terminal, the stray capacitance at the positive terminal can be increased without setting a certain distance or more between the positive terminal and the ground. Therefore, the degree of freedom in layout can be improved.

  Further, by increasing the stray capacitance at the positive electrode terminal or the negative electrode terminal as described above, when the stray capacitance at the midpoint between the first switching element and the second switching element is charged, the stray capacitance at the positive electrode terminal or the negative electrode terminal is charged. The charge of the capacity is charged. For this reason, the path through which the common mode current due to the stray capacitance at the midpoint flows is shortened, and radiation noise can be suppressed.

  Furthermore, according to the present invention, the thermal conductivity of the first region overlapping the first switching element in the stacking direction is made larger than the thermal conductivity of the second region. For this reason, for example, it is possible to easily release the heat generated in the first switching element, as compared with a configuration in which the insulating member is formed only by adding a second additive to a predetermined base material. Therefore, the heat dissipation of the first switching element can be improved.

  A semiconductor device according to the present invention includes one or more series circuits in which a first switching element and a second switching element are connected in series, and an output terminal between the first switching element and the second switching element. The second switching element is joined to the output terminal, and the semiconductor device includes a second insulating member disposed between the output terminal and a heat sink, and the second insulating member is a predetermined member. A third region in which a third additive is added to the base material, and a fourth region in which a fourth additive is added to the base material, wherein the third region includes the second insulating member and the second region. The second switching element overlaps the second switching element in the stacking direction of the two switching elements, the thermal conductivity of the third additive is larger than the thermal conductivity of the fourth additive, and the dielectric constant of the fourth additive is Third addition Wherein the smaller than the dielectric constant.

  According to the present invention, it is possible to improve the degree of freedom of layout and suppress conduction noise and radiation noise, and improve the heat dissipation of the second switching element.

  That is, according to the present invention, the dielectric constant of the fourth region is made smaller than that of the third region overlapping the second switching element in the stacking direction. For this reason, for example, the stray capacitance at the midpoint between the first switching element and the second switching element is reduced as compared with a configuration in which the second insulating member is formed only by adding a third additive to a predetermined base material. It becomes possible.

  Therefore, for example, it is possible to reduce the stray capacitance at the midpoint without making the area of the output terminal smaller than the area of the positive terminal. Alternatively, instead of making the area of the output terminal smaller than the area of the positive terminal, the stray capacitance at the midpoint can be reduced without setting the distance between the output terminal and the ground to be a certain distance or longer. Thereby, the common mode current flowing from the output terminal to the ground can be suppressed. Therefore, the degree of freedom in layout can be improved and conduction noise and radiation noise can be suppressed.

  According to the present invention, the thermal conductivity of the third region overlapping the second switching element in the stacking direction is made larger than the thermal conductivity of the fourth region. For this reason, for example, compared with the structure which consists only of what added the 4th additive to the predetermined | prescribed base material for the 2nd insulating member, it becomes possible to discharge | release the heat | fever which generate | occur | produced with the 2nd switching element easily. Therefore, the heat dissipation of the second switching element can be improved.

  The first switching element is disposed inside the first region in the stacking direction with the insulating member, and the first region is in the stacking direction of the terminal to which the first switching element is bonded and the insulating member. The second region may be disposed inside the terminal and outside the first region.

  As a result, heat can be radiated from the entire joint surface where the first switching element is joined to the terminal to the first region having a relatively high thermal conductivity. For this reason, it becomes possible to improve the heat dissipation of a 1st switching element more effectively.

  Furthermore, since the first region is arranged inside the terminal to which the first switching element is bonded, the terminal and the heat sink are arranged between the terminal to which the first switching element is bonded and the insulating member in the stacking direction. The second area is arranged in the area. For this reason, the stray capacitance at the terminal can be increased. Therefore, when the stray capacitance at the midpoint between the first switching element and the second switching element is charged, the charge of the stray capacitance at the terminal is charged. For this reason, the path through which the common mode current due to the stray capacitance at the midpoint flows is shortened, and radiation noise can be suppressed.

  The second switching element is disposed inside the third region in the stacking direction with the second insulating member, and the third region is connected to the output terminal in the stacking direction of the second insulating member and the output terminal. The fourth region may be disposed inside and the fourth region may be disposed outside the third region.

  As a result, heat can be radiated from the entire joint surface where the second switching element is joined to the output terminal to the third region having a relatively high thermal conductivity. For this reason, it is possible to further effectively improve the heat dissipation of the second switching element.

  Furthermore, since the third region is disposed inside the output terminal to which the second switching element is joined, the fourth region is provided between the output terminal and the heat sink in the stacking direction of the second insulating member and the output terminal. Is placed. For this reason, it is possible to reduce the stray capacitance at the output terminal. Therefore, the common mode current flowing from the output terminal to the ground can be suppressed.

  According to the present invention, it is possible to improve the degree of freedom of layout or suppress radiation noise and improve the heat dissipation of the first switching element or the second switching element.

It is a circuit diagram of the drive system carrying the inverter as a semiconductor device concerning one embodiment of this invention. It is a simple external appearance block diagram of a part of one arm series circuit included in the inverter and its periphery. It is sectional drawing in the III-III line of FIG. FIG. 4A is an external configuration diagram schematically illustrating a first surface of the switching element, and FIG. 4B is an external configuration diagram schematically illustrating a second surface of the switching element. It is a circuit diagram which shows the stray capacitance in several points paying attention to one said arm series circuit. It is a figure which shows a part of the mode at the time of manufacturing a 1st-3rd insulated substrate simply. It is a figure which shows a mode that the heat dissipation of an upper switching element is actively performed through the 1st area | region of a said 1st insulating substrate. The positional relationship in the stacking direction of the upper switching element, the positive electrode and the first insulating substrate (first region and second region), the lower switching element, the output terminal, and the third insulating substrate (third region and fourth region) It is a figure which shows the positional relationship in the lamination direction. It is a circuit diagram of the circuit carrying the inverter as a semiconductor device concerning the 1st modification. It is a simple external appearance block diagram of a part of one arm series circuit included in an inverter as a semiconductor device according to a second modification and its periphery.

I. Embodiment A. 1. Description of configuration Configuration of drive system 10 (1-1. Overall configuration)
FIG. 1 is a circuit configuration diagram of a drive system 10 equipped with an inverter 16 as a semiconductor device according to an embodiment of the present invention.

  As shown in FIG. 1, in addition to the inverter 16, the drive system 10 includes a motor 12, a DC power supply 14 (hereinafter also referred to as “power supply 14”), a capacitor 18, and an electronic control device 20 (hereinafter referred to as “ECU 20”). .)

(1-2. Motor 12)
The motor 12 is a three-phase AC brushless type, and power is supplied from a power source 14 via an inverter 16 controlled by the ECU 20. And the driving force according to the said electric power is produced | generated. The motor 12 can be used, for example, as a driving motor for a vehicle or an assist power generation motor for an electric power steering apparatus. Alternatively, it can be used for other purposes as described later.

(1-3. DC power supply 14)
The DC power source 14 is appropriately selected according to the application of the drive system 10 and can be either a primary battery or a secondary battery. For example, when the motor 12 is used in an application that requires a relatively high output (for example, when used as a vehicle driving motor), the power source 14 is a power storage such as a lithium ion secondary battery, a nickel hydride secondary battery, or a capacitor. It can be a device (energy storage). Further, when the motor 12 is used in an application requiring a relatively low output (for example, when used as an electric power steering device for a vehicle), the power source 14 can be a power storage device such as a lead storage battery.

(1-4. Inverter 16)
The inverter 16 has a three-phase bridge type configuration, performs DC / AC conversion, converts DC from the power supply 14 into three-phase AC, and supplies the AC to the motor 12.

  As shown in FIG. 1, the inverter 16 includes three-phase arm series circuits 30u, 30v, and 30w. The U-phase arm series circuit 30u includes an upper arm 32u having a switching element 34u (hereinafter referred to as "upper SW element 34u") and an anti-parallel diode 36u (hereinafter referred to as "upper diode 36u"), and a switching element 40u (hereinafter referred to as "lower"). SW arm 40u ") and a lower arm 38u having an anti-parallel diode 42u (hereinafter referred to as" lower diode 42u ").

  Similarly, the V-phase arm series circuit 30v includes an upper switching element 34v (hereinafter referred to as “upper SW element 34v”) and an anti-parallel diode 36v (hereinafter referred to as “upper diode 36v”), and a lower arm 32v. The lower arm 38v includes a switching element 40v (hereinafter referred to as “lower SW element 40v”) and an antiparallel diode 42v (hereinafter referred to as “lower diode 42v”). The W-phase arm series circuit 30w includes an upper arm 32w having an upper switching element 34w (hereinafter referred to as “upper SW element 34w”) and an anti-parallel diode 36w (hereinafter referred to as “upper diode 36w”), and a lower switching element 40w. (Hereinafter referred to as “lower SW element 40w”) and a lower arm 38w having an anti-parallel diode 42w (hereinafter referred to as “lower diode 42w”).

  The upper SW elements 34u, 34v, 34w and the lower SW elements 40u, 40v, 40w are, for example, switching elements such as one or a plurality of MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) or insulated gate bipolar transistors (IGBTs). It can consist of Similarly, the upper diodes 36u, 36v, 36w and the lower diodes 42u, 42v, 42w can each be composed of one or more diodes.

  In the following, each arm series circuit 30u, 30v, 30w is generically referred to as an arm series circuit 30, each upper arm 32u, 32v, 32w is generically referred to as an upper arm 32, and each lower arm 38u, 38v, 38w is designated as a lower arm. 38, the upper SW elements 34u, 34v, 34w are collectively referred to as the upper SW element 34, the lower SW elements 40u, 40v, 40w are collectively referred to as the lower SW element 40, and the upper diodes 36u, 36v, 36w The lower diodes 42u, 42v, and 42w are collectively referred to as the lower diode 42.

  In each arm series circuit 30, midpoints 44 u, 44 v, 44 w of the upper arms 32 u, 32 v, 32 w and the lower arms 38 u, 38 v, 38 w are connected to the windings 46 u, 46 v, 46 w of the motor 12. Hereinafter, the middle points 44u, 44v, and 44w are collectively referred to as the middle point 44, and the windings 46u, 46v, and 46w are collectively referred to as the winding 46.

  Each upper SW element 34 and each lower SW element 40 are driven by drive signals UH, VH, WH, UL, VL, WL from the ECU 20.

(1-5.ECU 20)
The ECU 20 controls the output of the motor 12 based on output values from various sensors (not shown). The ECU 20 has an input / output unit, a calculation unit, and a storage unit (all not shown) as a hardware configuration.

2. Details of inverter 16 (2-1. Overall configuration)
FIG. 2 is a simplified external perspective view of a part of one arm series circuit 30 and its periphery. FIG. 3 is a cross-sectional view taken along line III-III in FIG. In the present embodiment, the inverter 16 is configured by arranging three sets of arm series circuits 30 shown in FIGS. 2 and 3 in parallel (see FIG. 1). 2 and 3, “P” indicates the positive electrode side, “N” indicates the negative electrode side, and “OUT” indicates the output side.

  2 and 3 show the upper SW element 34 and the lower SW element 40 of the arm series circuit 30, while the upper diode 36 and the lower diode 42 are not shown.

  In the present embodiment, switching elements (for example, MOSFETs or IGBTs) having the same specifications are used for the upper SW element 34 and the lower SW element 40. 4A and 4B, the upper SW element 34 and the lower SW element 40 of this embodiment have a positive electrode 52 formed on the first surface 50 (drain surface), and the first surface 50 A negative electrode 56 and a gate electrode 58 (control electrode) are formed on the second surface 54 (source surface) on the opposite side. In FIG. 4A, “P” indicates the positive electrode side, and “N” in FIG. 4B indicates the negative electrode side.

  Hereinafter, in order to distinguish the constituent elements of the upper SW element 34 and the lower SW element 40, the positive electrode 52, the negative electrode 56, and the gate electrode 58 of the upper SW element 34 are replaced with the upper positive electrode 52 up, the upper negative electrode 56 up, and the upper gate. The positive electrode 52, the negative electrode 56, and the gate electrode 58 of the lower SW element 40 are referred to as a lower positive electrode 52low, a lower negative electrode 56low, and a lower gate electrode 58low. 2 and 3, illustration of the positive electrode 52, the negative electrode 56, and the gate electrode 58 is omitted.

  As shown in FIGS. 2 and 3, the positive terminal 60, the negative terminal 62, and the output terminal 64 of the inverter 16 are disposed around the upper SW element 34 and the lower SW element 40. The positive terminal 60 is formed on the first insulating substrate 70. The negative terminal 62 is formed on the second insulating substrate 72. The output terminal 64 is formed on the third insulating substrate 74.

  The first insulating substrate 70 insulates the positive electrode terminal 60 from the heat sink 80, and has a first region 90 and a second region 92 (FIG. 3) made of different materials. The second insulating substrate 72 insulates the negative electrode terminal 62 from the heat sink 80 and has the same composition as a whole. The third insulating substrate 74 insulates the output terminal 64 from the heat sink 80 and has a third region 94 and a fourth region 96 made of different materials. Details of the first to fourth regions 90, 92, 94, 96 will be described later. The first insulating substrate 70, the second insulating substrate 72, and the third insulating substrate 74 are formed on the heat sink 80. The heat sink 80 cools the inverter 16 and is connected to the ground GND (reference potential).

  The positive terminal 60, the negative terminal 62, and the output terminal 64 are plate-shaped conductive members (for example, copper plates). The positive terminal 60 is connected to the positive side of the arm series circuit 30, the negative terminal 62 is connected to the negative side of the arm series circuit 30, and the output terminal 64 is connected to the output side of the arm series circuit 30 (see FIG. 1).

  The positive terminal 60 is directly formed on the first insulating substrate 70 as DBC (Direct Bonding Copper). The negative terminal 62 is directly formed on the second insulating substrate 72 as DBC. The output terminal 64 is directly formed on the third insulating substrate 74 as DBC. Further, on the surface of the first insulating substrate 70, the second insulating substrate 72, and the third insulating substrate 74 on the heat sink 80 side, solid copper patterns 100, 102, 104 (FIG. 3) are formed as DBC.

  Furthermore, solder, a copper plate, and thermal grease (all not shown) are disposed between the solid patterns 100, 102, 104 and the heat sink 80. That is, the solid patterns 100, 102, and 104 are joined to the copper plate via the solder, and the copper plate is supported by the heat sink 80 via the thermal grease.

(2-2. Upper arm 32)
The positive electrode 52 (upper positive electrode 52up) of each upper SW element 34 is joined to the positive terminal 60 of the inverter 16 via solder (not shown) (see FIGS. 2 and 3). These joining may be a joining method such as brazing. In the present embodiment, wiring (distribution member) such as wire bonding or a bus bar is not used for joining the upper positive electrode 52up and the positive terminal 60 and joining the positive side of the upper diode 36 and the positive terminal 60.

  The negative electrode 56 of each upper SW element 34 is connected to the output terminal 64 of the inverter 16 through wire bonding 110.

(2-3. Lower arm 38)
The positive electrode 52 (lower positive electrode 52low) of each lower SW element 40 is joined to the output terminal 64 of the inverter 16 via solder (not shown) (see FIGS. 2 and 3). These joining may be a joining method such as brazing. In the present embodiment, wiring (wiring member) such as wire bonding or a bus bar is not used for joining the lower positive electrode 52 low and the output terminal 64.

  The negative electrode 56 (lower negative electrode 56 low) of each lower SW element 40 is connected to the negative terminal 62 of the inverter 16 through the wire bonding 112.

B. Floating Capacitance FIG. 5 is a circuit diagram showing stray capacitances C1 to C3 at a plurality of points P1 to P3 by focusing on one arm series circuit 30. Hereinafter, the stray capacitances C1 to C3 at the points P1 to P3 will be described.

  When the arm series circuit 30 is operated, stray capacitances C1 to C3 may be generated between the points P1 to P3 and the ground GND (heat sink 80). Since these stray capacitances C1 to C3 exist, noise is transmitted to the common (power supply 14 side or other equipment side) via the ground GND (heat sink 80) when the upper SW element 34 and the lower SW element 40 are switched, and is conducted. Noise and radiation noise may occur. In particular, with regard to the stray capacitance C2, there is a high possibility that conduction noise and radiation noise are generated (see paragraphs [0008] and [0009] of Patent Document 1, for example, regarding the mechanism of generation of conduction noise and radiation noise).

In general, the impedance Xc of the capacitor is obtained by the following equation (1).
Xc = 1 / (jωC) (1)

  In the above, j is an imaginary unit, ω is an angular frequency [Hz], and C is a capacitance [F].

  According to the above equation (1), in the case of the arm series circuit 30, the higher the switching frequency [Hz] of the upper SW element 34 and the lower SW element 40, the easier the current flows to the stray capacitances C1 to C3. By reducing C, it is possible to make it difficult for current to flow through the stray capacitances C1 to C3. In particular, since the influence of the common mode current Icom flowing from the stray capacitance C2 between the point P2 (the output terminal 64 constituting the middle point 44) where the potential fluctuation occurs due to switching and the ground GND (heat sink 80) to the common side is large, It is important to increase the impedance of the stray capacitance C2.

  On the other hand, if the values of the stray capacitances C1 and C3 are increased, the charges of the stray capacitances C1 and C3 are charged when the stray capacitance C2 is charged. For this reason, the path through which the common mode current Icom caused by the stray capacitance C2 flows is shortened, and radiation noise can be suppressed.

In general, the capacitance C [F] between parallel flat plates (electrode plates) is expressed by the following equation (2).
C = ε0 · ε _s · (S / d) (2)

In the above formula (2), ε0 is the dielectric constant [F / m] of vacuum, ε _s is the relative dielectric constant, S is the area [m ² ] of the electrode plate, and d is between the parallel plates (electrode plates). The gap [m] is shown. According to the above equation (2), the capacitance C increases as the relative dielectric constant ε _s increases.

C. Materials of the first insulating substrate 70, the second insulating substrate 72, and the third insulating substrate 74 Background As described above, while it is preferable to reduce the stray capacitance C2, it may be preferable to increase the stray capacitances C1 and C3. The upper SW element 34 and the lower SW element 40 are heat radiating elements and need to be sufficiently cooled.

  Therefore, in the present embodiment, the first insulating substrate 70, the second insulating substrate 72, and the third insulating substrate 74 adjust at least one of thermal conductivity and dielectric constant to the base material 120 made of an insulating resin material. A filler 122 (additive) is added and kneaded by a mixer 124 or the like, and then a sheet 126 is formed and used (see FIG. 6). As such a resin material, for example, an epoxy resin, an imide resin, polyphenylene ether (PPE), bismaleimide triazine (BT resin), a fluororesin, a silicone resin, a phenol resin, or the like can be used (for example, Japanese Patent Laid-Open No. Hei 10). -107448, JP, 2011-10077, A).

2. First insulating substrate 70
As shown in FIGS. 2 and 3, the first insulating substrate 70 is stacked with the upper SW element 34. For this reason, it is preferable that the first insulating substrate 70 facilitates heat dissipation of the upper SW element 34. In addition, the stray capacitance C3 (FIG. 5) is generated at the positive electrode terminal 60 laminated together with the first insulating substrate 70. For this reason, it is preferable that the first insulating substrate 70 has a large dielectric constant in order to increase the stray capacitance C3.

  Therefore, the first region 90 of the first insulating substrate 70 is made of a material having a higher thermal conductivity than the second region 92. Thereby, the heat generated in the upper SW element 34 can be actively dissipated through the first region 90 having a high thermal conductivity (see FIG. 7). The second region 92 is made of a material having a dielectric constant larger than that of the first region 90. As a result, the stray capacitance C3 can be increased and the radiation noise can be reduced.

The first region 90 is made of, for example, a high thermal conductive composite material including a filler made of a single substance or a composite such as aluminum nitride (AlN), silicon nitride (Si ₃ N ₄ ), and alumina (Al ₂ O ₃ ). As such a high thermal conductive composite material, for example, JP 2011-10077A, Kenji Miyata et al., “Development of an organic / inorganic composite material having the world's highest thermal conductivity”, Polyfile, February 2010, 47 and 552 can be used. The thermal conductivity of the high thermal conductive composite material is preferably 10 [W / mK] or more, and the relative dielectric constant ε _s is preferably 7 to 8, for example.

In the case where the first region 90 is formed of the material as described above, the second region 92 is a strong material including a filler made of a simple substance or a mixture such as barium titanate (BaTiO ₃ ) and strontium titanate (SrTiO ₃ ). It is composed of a dielectric composite material. As such a ferroelectric composite material, for example, those described in JP 2001-068803 A and JP 06-172618 A can be used. The thermal conductivity of the ferroelectric composite material is preferably less than 5 [W / mK], for example, and the relative dielectric constant ε _s is preferably 20 or more, for example.

3. Second insulating substrate 72
In the present embodiment, the second insulating substrate 72 is not laminated with either the upper SW element 34 or the lower SW element 40. In addition, the stray capacitance C1 (FIG. 5) is generated in the negative electrode terminal 62 laminated together with the second insulating substrate 72. For this reason, it is preferable that the second insulating substrate 72 has a large dielectric constant in order to increase the stray capacitance C1.

  Therefore, the second insulating substrate 72 is made of the same ferroelectric composite material as the second region 92 of the first insulating substrate 70. As a result, the stray capacitance C1 can be increased and radiation noise can be reduced.

4). Third insulating substrate 74
The third insulating substrate 74 is stacked with the lower SW element 40. For this reason, it is preferable to facilitate heat dissipation of the lower SW element 40. Further, the stray capacitance C2 (FIG. 5) is generated at the output terminal 64 laminated together with the third insulating substrate 74. For this reason, it is preferable to reduce the dielectric constant in order to reduce the stray capacitance C2.

  Therefore, the third region 94 of the third insulating substrate 74 is made of a material having a higher thermal conductivity than the fourth region 96. As a result, similarly to the upper SW element 34 (FIG. 7), the heat generated by the lower SW element 40 can be actively dissipated through the third region 94 having a high thermal conductivity. The fourth region 96 is made of a material having a smaller dielectric constant than that of the third region 94. As a result, the stray capacitance C2 can be reduced and the common mode current Icom can be reduced.

The third region 94 is made of, for example, a high thermal conductive composite material similar to the first region 90. In the case where the third region 94 is formed of the material as described above, the fourth region 96 includes, for example, a low dielectric constant composite material including a filler made of a single substance or a mixture of silica (SiO ₃ ), boron nitride (BN), or the like. Consists of. As such a low dielectric constant composite material, for example, those described in JP-A-10-107448 and JP-A-2005-159039 can be used. In this case, for example, the thermal conductivity of the low dielectric constant composite material is preferably less than 3 [W / mK], for example, and the relative dielectric constant ε _s is preferably less than 5.

D. FIG. 8 shows the positional relationship between the first insulating substrate 70 and the upper SW element 34 and the positional relationship between the third insulating substrate 74 and the lower SW element 40. FIG. The region 90 and the second region 92) in the stacking direction, and the positional relationship in the stacking direction of the lower SW element 40, the output terminal 64 and the third insulating substrate 74 (third region 94 and fourth region 96). is there. In FIG. 8, the outer edges of the positive electrode terminal 60 and the second region 92 overlap, and the outer edges of the output terminal 64 and the fourth region 96 overlap.

  As shown in FIGS. 3 and 8, the first region 90 of the first insulating substrate 70 overlaps the upper SW element 34 in the stacking direction (Z direction in FIG. 3). More specifically, the first region 90 includes the entire upper SW element 34 in the stacking direction and occupies a larger range than the upper SW element 34. In other words, the upper SW element 34 is located inside the first region 90. Further, the first region 90 is located inside the positive electrode terminal 60 in the stacking direction, and the second region 92 is located so as to surround four sides of the first region 90.

  Similarly, the third region 94 of the third insulating substrate 74 overlaps the lower SW element 40 in the stacking direction (Z direction in FIG. 3). More specifically, the third region 94 includes the entire lower SW element 40 in the stacking direction and occupies a larger range than the lower SW element 40. In other words, the lower SW element 40 is located inside the third region 94. The third region 94 is located inside the output terminal 64 in the stacking direction, and the fourth region 96 is located so as to surround the third region 94.

E. Effects of the Embodiment As described above, according to the present embodiment, the configuration of the first insulating substrate 70 realizes an improvement in the degree of freedom of layout or suppression of radiation noise, and the heat dissipation of the upper SW element 34. It becomes possible to improve.

  That is, according to the present embodiment, the dielectric constant of the second region 92 is made larger than that of the first region 90 overlapping the upper SW element 34 in the stacking direction (Z direction in FIG. 3). Therefore, for example, the stray capacitance C3 (FIG. 5) at the positive electrode terminal 60 can be increased as compared with the case where the first insulating substrate 70 is composed only of the composition of the first region 90.

  Therefore, for example, even if the area of the output terminal 64 is not made smaller than the area of the positive electrode terminal 60, the stray capacitance C3 in the positive electrode terminal 60 can be increased. Alternatively, instead of making the area of the output terminal 64 smaller than the area of the positive electrode terminal 60, the stray capacitance C3 can be increased without setting a certain distance or more between the positive electrode terminal 60 and the ground. Therefore, the degree of freedom in layout can be improved.

  Further, by increasing the stray capacitance C3 as described above, when the stray capacitance C2 at the midpoint 44 (point P2) between the upper SW element 34 and the lower SW element 40 is charged, the stray capacitance at the positive terminal 60 is increased. The charge of C3 is charged. For this reason, the path through which the common mode current Icom caused by the stray capacitance C2 at the midpoint 44 flows is shortened, and radiation noise can be suppressed.

  Furthermore, according to the present embodiment, the thermal conductivity of the first region 90 that overlaps the upper SW element 34 in the stacking direction (Z direction in FIG. 3) is made larger than the thermal conductivity of the second region 92. For this reason, for example, it is possible to easily release the heat generated in the upper SW element 34 as compared with the case where the first insulating substrate 70 is configured only from the composition of the second region 92. Therefore, the heat dissipation of the upper SW element 34 can be improved.

  In addition, according to the present embodiment, the configuration of the third insulating substrate 74 can improve the degree of freedom in layout, suppress conduction noise and radiation noise, and improve the heat dissipation of the lower SW element 40. It becomes.

  That is, according to the present embodiment, the dielectric constant of the fourth region 96 is made smaller than that of the third region 94 overlapping the lower SW element 40 in the stacking direction (Z direction in FIG. 3). Therefore, for example, the stray capacitance C2 at the midpoint 44 (point P2) between the upper SW element 34 and the lower SW element 40 is smaller than that in the case where the third insulating substrate 74 is composed only of the composition of the third region 94. It can be made smaller.

  Therefore, for example, even if the area of the output terminal 64 is not made smaller than the area of the positive electrode terminal 60, the stray capacitance C2 can be reduced. Alternatively, instead of making the area of the output terminal 64 smaller than the area of the positive electrode terminal 60, the stray capacitance C2 can be reduced without making the distance between the output terminal 64 and the ground more than a certain distance. Thereby, the common mode current Icom flowing from the output terminal 64 to the ground can be suppressed. Therefore, the degree of freedom in layout can be improved and conduction noise and radiation noise can be suppressed.

  Further, according to the present embodiment, the thermal conductivity of the third region 94 that overlaps the lower SW element 40 in the stacking direction (Z direction in FIG. 3) is made larger than the thermal conductivity of the fourth region 96. For this reason, for example, it is possible to easily release the heat generated in the lower SW element 40 as compared with the case where the third insulating substrate 74 is configured only from the composition of the fourth region 96. Therefore, the heat dissipation of the lower SW element 40 can be improved.

  In the present embodiment, when viewed in the stacking direction (the Z direction in FIG. 3), the upper SW element 34 is disposed inside the first region 90, and the first region 90 is disposed inside the positive electrode terminal 60. Yes. As a result, heat can be radiated from the entire bonding surface where the upper SW element 34 is bonded to the positive electrode terminal 60 to the first region 90 having a relatively high thermal conductivity. For this reason, it becomes possible to improve the heat dissipation of the upper SW element 34 more effectively.

  Further, since the first region 90 is disposed inside the positive electrode terminal 60, the second region 92 is disposed between the positive electrode terminal 60 and the heat sink 80 in the stacking direction (Z direction in FIG. 3). (See FIG. 3). For this reason, the stray capacitance C3 at the positive electrode terminal 60 can be increased. Therefore, when the stray capacitance C2 at the midpoint 44 (point P2) between the upper SW element 34 and the lower SW element 40 is charged, the charge of the stray capacitance C3 at the positive electrode terminal 60 is charged. For this reason, the path through which the common mode current Icom caused by the stray capacitance C2 at the midpoint 44 flows is shortened, and radiation noise can be suppressed.

  In the present embodiment, when viewed in the stacking direction (Z direction in FIG. 3), the lower SW element 40 is disposed inside the third region 94, and the third region 94 is disposed inside the output terminal 64. (See FIG. 8).

  As a result, heat can be radiated from the entire joint surface where the lower SW element 40 is joined to the output terminal 64 to the third region 94 having a relatively high thermal conductivity. For this reason, it becomes possible to improve the heat dissipation of the lower SW element 40 more effectively.

  Further, since the third region 94 is disposed inside the output terminal 64, the fourth region 96 is disposed between the output terminal 64 and the heat sink 80 in the stacking direction (see FIG. 3). ). For this reason, the stray capacitance C2 at the output terminal 64 can be reduced. Therefore, the common mode current Icom flowing from the output terminal 64 to the ground can be suppressed.

II. Modifications It should be noted that the present invention is not limited to the above-described embodiment, and it is needless to say that various configurations can be adopted based on the contents described in this specification. For example, the following configuration can be adopted.

A. Inverter 16 and drive system 10
In the above embodiment, the three-phase bridge type inverter 16 is used. However, an inverter having a single-phase or multi-phase arm series circuit in which an upper arm and a lower arm having a switching element and an antiparallel diode are connected in series may be used. For example, it is not limited to this. For example, as shown in FIG. 9, it can be applied to a single-phase bridge inverter 16a. The inverter 16 a in FIG. 9 converts the direct current from the direct current power source 14 into alternating current and supplies the alternating current to the winding 46 a (load) and the resistor 130.

  The inverter 16a has two arm series circuits 30a and 30b. The arm series circuit 30a includes an upper arm 32a having a switching element 34a (hereinafter referred to as “upper SW element 34a”) and an anti-parallel diode 36a (hereinafter referred to as “upper diode 36a”), and a switching element 40a (hereinafter referred to as “lower SW element”). Element 40a ") and a lower arm 38a having an antiparallel diode 42a (hereinafter referred to as" lower diode 42a "). Similarly, the arm series circuit 30b includes an upper arm 32b having a switching element 34b (hereinafter referred to as “upper SW element 34b”) and an anti-parallel diode 36b (hereinafter referred to as “upper diode 36b”), and a switching element 40b (hereinafter referred to as “upper SW element 34b”). And a lower arm 38b having an anti-parallel diode 42b (hereinafter referred to as "lower diode 42b").

  Also in the inverter 16a, the first insulating substrate 70 having the first region 90 and the second region 92 is provided corresponding to the upper SW elements 34a and 34b, and the third insulating substrate 74 having the third region 94 and the fourth region 96 is provided. Can be provided corresponding to the lower SW elements 40a and 40b. Thereby, it is possible to improve the degree of freedom of layout or suppress conduction noise and radiation noise, and improve the heat dissipation of the upper SW element 34 and the lower SW element 40.

  In the above embodiment and the modification of FIG. 9, the example in which the present invention is applied to the inverters 16 and 16a has been described. However, an upper arm and a lower arm each having a switching element and an antiparallel diode are connected in series. If it is a semiconductor device provided with a phase arm series circuit, it will not be restricted to this. For example, the present invention can be applied to a step-up / step-down and chopper type DC / DC converter (see, for example, FIG. 1 and FIG. 9 of JP 2009-153343 A).

  In the above embodiment, the positive terminal 60, the output terminal 64, and the negative terminal 62 are arranged in this order from the left side in FIGS. 2 and 3, but the arrangement in the inverter 16 is not limited to this. For example, the present invention can be applied to the inverter 16b arranged as shown in FIG. In the arm series circuit 30c of the inverter 16b in FIG. 10, the output terminal 64, the positive terminal 60, and the negative terminal 62 are arranged in this order from the left in FIG. Even in such a configuration, the first region 90 and the second region 92 are provided on the first insulating substrate 70, and the third region 94 and the fourth region 96 are provided on the third insulating substrate 74. It becomes possible to obtain the effect.

  Alternatively, in the above embodiment and the modification of FIG. 10, each of the positive electrode terminal 60, the negative electrode terminal 62, and the output terminal 64 is disposed on the common heat sink 80, but for example, the heat sink 80 on the upper side and the lower side in FIG. The positive terminal 60 and the negative terminal 62 may be disposed corresponding to the upper heat sink 80, and the output terminal 64 may be disposed corresponding to the lower heat sink 80.

  Alternatively, as long as the semiconductor device includes a series circuit in which a plurality of switching elements are connected in series, an antiparallel diode may not be provided. For example, the present invention can be applied to a NAND flash memory.

  In the above embodiment, the motor 12 of the drive system 10 is, for example, for driving a vehicle or for electric power steering. However, if the stray capacitance C2 is generated at the midpoint between the two switching elements, Not limited to. For example, you may use for the motor in a washing machine, a vacuum cleaner, an air conditioner, a refrigerator, an electromagnetic cooker, an alternating current (AC) servo, a railway vehicle, and an elevator.

  In the above embodiment, the drive system 10 drives the motor 12, but the present invention is not limited to this as long as the stray capacitance C2 is generated at the midpoint of the plurality of switching elements. For example, the drive system 10 can also be used for an inverter in a power conditioner for an uninterruptible power supply, solar power generation or wind power generation (see, for example, FIG. 4 of JP 2011-103497 A).

B. Gate electrode 58
In the above embodiment, in the upper SW element 34 and the lower SW element 40, the gate electrode 58 is formed on the same surface (second surface 54) as the negative electrode 56 (FIG. 4B). Not exclusively.

  For example, a configuration in which the gate electrode 58 is formed on the same surface (first surface 50) as the positive electrode 52 and the gate electrode 58 is not formed on the same surface (second surface 54) as the negative electrode 56 is possible. In this case, it is preferable that the negative electrode 56 of the upper SW element 34 is bonded to the output terminal 64 and the negative electrode 56 of the lower SW element 40 is bonded to the negative terminal 62. In this case, the third region 94 (high thermal conductivity composite material) and the fourth region 96 (low dielectric constant composite material) are formed on the first insulating substrate 70 disposed between the upper SW element 34 and the heat sink 80. The first region 90 (high thermal conductivity composite material) and the second region 92 (ferroelectric composite material) are formed on the second insulating substrate 72 disposed between the lower SW element 40 and the heat sink 80, and the second region 92 (ferroelectric composite material) is formed. The one insulating substrate 70 can be configured with the same composition as the second region 92.

  Even if it is such a structure, there can exist an effect | action and effect similar to the said embodiment. That is, it is possible to improve the degree of freedom of layout or suppress conduction noise and radiation noise, and improve the heat dissipation of the upper SW element 34 and the lower SW element 40.

  Alternatively, one of the upper SW element 34 and the lower SW element 40 has a configuration as shown in FIGS. 4A and 4B (a configuration in which the gate electrode 58 is formed on the same surface as the negative electrode 56), and the other has a different configuration (a gate electrode). 58 may be formed on the same surface as the positive electrode 52). In this case, a configuration in which the upper SW element 34 is bonded to the positive terminal 60 and the lower SW element 40 is bonded to the negative terminal 62, or a configuration in which the upper SW element 34 and the lower SW element 40 are bonded to the output terminal 64 is possible. Become. Also in these configurations, the first to fourth regions 90, 92, 94, and 96 can be used.

C. First insulating substrate 70, second insulating substrate 72, and third insulating substrate 74
1. First region 90 and second region 92
In the above-described embodiment, the first region 90 includes the entire upper SW element 34 in the stacking direction (Z direction in FIG. 3), occupies a larger range than the upper SW element 34, and the second region around the first region 90. 92 was arranged (see FIG. 8). However, the first region 90 is not limited to this as long as the heat dissipation of the upper SW element 34 is improved and the stray capacitance C3 in the positive electrode terminal 60 is increased by the second region 92.

  For example, the first region 90 is included in the entire upper SW element 34 in the stacking direction (Z direction in FIG. 3) (the first region 90 is smaller than the upper SW element 34), and the second region is formed around the first region 90. Region 92 may be disposed.

  Alternatively, in the stacking direction (Z direction in FIG. 3), the composition constituting the first region 90 and the composition constituting the second region 92 can be alternately arranged from the center of the upper SW element 34. .

2. Third region 94 and fourth region 96
In the above embodiment, the third region 94 includes the entire lower SW element 40 in the stacking direction (Z direction in FIG. 3), occupies a larger range than the lower SW element 40, and the fourth region around the third region 94. 96 was arranged (see FIG. 8). However, the third region 94 is not limited to this as long as the heat dissipation of the lower SW element 40 is improved and the stray capacitance C2 at the output terminal 64 is reduced by the fourth region 96.

  For example, the third region 94 is included in the entire lower SW element 40 in the stacking direction (Z direction in FIG. 3) (the third region 94 is smaller than the lower SW element 40), and the fourth region is formed around the third region 94. Region 96 may be disposed.

  Alternatively, in the stacking direction (Z direction in FIG. 3), it is possible to alternately arrange the composition constituting the third region 94 and the composition constituting the fourth region 96 from the center of the lower SW element 40. .

3. Others In the above embodiment, the first region 90 and the second region 92 are provided on the first insulating substrate 70, and the third region 94 and the fourth region 96 are provided on the third insulating substrate 74. It is also possible to provide only one of the combination of the second region 92 or the combination of the third region 94 and the fourth region 96.

  In the above embodiment, the first to fourth regions 90, 92, 94, and 96 have been described with the base material 120 made of a common material in mind, but the first to fourth regions 90, 92, 94, It is also possible to change the material of the base material 120 every 96.

16, 16a, 16b ... Inverter (semiconductor device)
30, 30a, 30b, 30c, 30u, 30v, 30w ... arm series circuit (series circuit)
34: Upper switching element (first switching element)
40. Lower switching element (second switching element)
60 ... Positive terminal 62 ... Negative terminal 64 ... Output terminal 70 ... First insulating substrate (insulating member)
74: third insulating substrate (second insulating member) 80 ... heat sink 90 ... first region 92 ... second region 94 ... third region 96 ... fourth region 120 ... base material 122 ... filler (first to fourth additives) )

Claims (5)

A semiconductor device comprising one or more series circuits in which a first switching element and a second switching element are connected in series between a positive terminal and a negative terminal,
The first switching element is bonded to the positive terminal or the negative terminal,
The semiconductor device includes an insulating member disposed between a heat sink and a terminal of the positive electrode terminal or the negative electrode terminal to which the first switching element is bonded,
The insulating member is
A first region in which a first additive is added to a predetermined base material;
A second region in which a second additive is added to the base material,
The first region overlaps the first switching element in the stacking direction of the insulating member and the first switching element,
The thermal conductivity of the first additive is greater than the thermal conductivity of the second additive,
The semiconductor device, wherein a dielectric constant of the second additive is larger than a dielectric constant of the first additive. The semiconductor device according to claim 1,
An output terminal is provided between the first switching element and the second switching element,
The second switching element is bonded to the output terminal;
The semiconductor device includes a second insulating member disposed between the output terminal and the heat sink,
The second insulating member is
A third region in which a third additive is added to a predetermined base material;
A fourth region in which a fourth additive is added to the base material,
The third region overlaps the second switching element in the stacking direction of the second insulating member and the second switching element,
The thermal conductivity of the third additive is greater than the thermal conductivity of the fourth additive,
The semiconductor device, wherein the dielectric constant of the fourth additive is smaller than the dielectric constant of the third additive. The semiconductor device according to claim 1 or 2,
The first switching element is disposed inside the first region in the stacking direction with the insulating member,
The first region is disposed inside the terminal in the stacking direction of the terminal to which the first switching element is bonded and the insulating member,
The semiconductor device, wherein the second region is arranged outside the first region. A semiconductor device comprising one or more series circuits in which a first switching element and a second switching element are connected in series, and an output terminal between the first switching element and the second switching element,
The second switching element is bonded to the output terminal;
The semiconductor device includes a second insulating member disposed between the output terminal and a heat sink,
The second insulating member is
A third region in which a third additive is added to a predetermined base material;
A fourth region in which a fourth additive is added to the base material,
The third region overlaps the second switching element in the stacking direction of the second insulating member and the second switching element,
The thermal conductivity of the third additive is greater than the thermal conductivity of the fourth additive,
The semiconductor device, wherein the dielectric constant of the fourth additive is smaller than the dielectric constant of the third additive. The semiconductor device according to claim 2 or 4 or claim 3 dependent on claim 2.
The second switching element is disposed inside the third region in the stacking direction with the second insulating member,
The third region is disposed inside the output terminal in the stacking direction of the second insulating member and the output terminal,
The semiconductor device, wherein the fourth region is disposed outside the third region.

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