JP2015023231A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can achieve at least one of improvement in degree of layout freedom and noise reduction.SOLUTION: A semiconductor device comprises an adhesion layer 90 for bonding a first electrode plate 60 or a second electrode plate 100 with an insulating member 70. The insulating member 70 includes a first resin material 130 added with a dielectric filler 132. The adhesion layer 90 includes a second resin material 140 added with a conductive filler 142 having an average particle diameter smaller than that of the dielectric filler 132. A capacitor 110a comprises the first electrode 60, the second electrode plate 100, the insulating member 70 and the adhesion layer 90.

Description

  The present invention relates to a semiconductor device including one or more series circuits in which a plurality of switching elements are connected in series.

  A semiconductor device having a series circuit in which a plurality of switching elements are connected in series has been developed. Examples of such a semiconductor device include an inverter, a converter, and a NAND flash memory (for example, Patent Document 1).

  Patent Document 1 aims to provide an inverter module of a power conversion device that can reduce conduction noise and radiation noise by suppressing common mode current (summary, [0010]). In order to achieve this object, Patent Document 1 discloses a switching arm series circuit for one phase (or multiple phases) in which a switching element and an antiparallel diode are used as one arm and two arms 5 and 6 are connected in series up and down. In the inverter module 25a of the power conversion device that is included in one package and the cooling copper base 1 is disposed outside the package, the area of the copper pattern 4 on which the lower arm 6 of the switching arm series circuit is mounted is The area is smaller than the area of the copper pattern 3 on which the upper arm 5 is mounted (summary).

JP 2007-181351 A

  As described above, in Patent Document 1, conduction is achieved by suppressing the common mode current by making the area of the copper pattern 4 on which the lower arm 6 is mounted smaller than the area of the copper pattern 3 on which the upper arm 5 is mounted. It is intended to reduce noise and radiated noise. However, in the configuration of Patent Document 1, there is a possibility that the degree of freedom in area (that is, layout) may be reduced, and there is room for further improvement in the method for reducing noise.

  The present invention has been made in view of such problems, and an object of the present invention is to provide a semiconductor device capable of at least one of improving the degree of freedom of layout and reducing noise.

  A semiconductor device according to the present invention includes one or a plurality of series circuits in which a first switching element and a second switching element are connected in series between a positive electrode terminal and a negative electrode terminal, and the semiconductor device includes: An insulating member sandwiched between a positive electrode terminal itself or the negative electrode terminal itself or a first electrode plate made of an electrode plate electrically connected to the positive electrode terminal or the negative electrode terminal and a second electrode plate on the ground side; 1 electrode plate or an adhesive layer for adhering the second electrode plate and the insulating member, wherein the insulating member includes a first resin material to which a dielectric filler is added, and the adhesive layer includes the dielectric A second resin material to which a conductive filler having an average particle size smaller than that of the filler is added; and a capacitor is formed by the first electrode plate, the second electrode plate, the insulating member, and the adhesive layer. Is the fact characterized.

  According to the present invention, it is possible to improve the degree of freedom of layout or suppress radiation noise.

  That is, according to the present invention, the adhesive layer for bonding the first electrode plate or the second electrode plate and the insulating member is made of the second resin material to which the conductive filler having an average particle size smaller than that of the dielectric filler is added. Including. Therefore, the conductive filler or the second resin material enters the gap between the first electrode plate or the second electrode plate and the insulating member. Therefore, even when a dielectric filler having a relatively large average particle size is added to the insulating member (first resin material) in order to give the capacitor desired capacitance characteristics, the first electrode plate or the second electrode plate and the insulating member It is possible to suppress the occurrence of a gap between the two. Therefore, even when the addition amount of the dielectric filler to the insulating member (first resin material) is increased, it is possible to prevent the capacity characteristics from being deteriorated due to the generation of the gap as described above. As a result, the stray capacitance at the positive terminal or the negative terminal can be relatively increased.

  Therefore, for example, when an insulating member and an adhesive layer are provided between the positive electrode terminal and the ground, the stray capacitance at the positive electrode terminal can be increased without making the area of the output terminal smaller than the area of the positive electrode terminal. It becomes possible. Alternatively, instead of making the area of the output terminal smaller than the area of the positive terminal, the stray capacitance at the positive terminal can be increased without making the distance between the positive terminal and the ground less than a certain distance. Therefore, the degree of freedom in layout can be improved.

  Further, by increasing the stray capacitance at the positive electrode terminal or the negative electrode terminal as described above, when the stray capacitance at the midpoint between the first switching element and the second switching element is charged, the stray capacitance at the positive electrode terminal or the negative electrode terminal is charged. The charge of the capacity is charged. For this reason, the path through which the common mode current due to the stray capacitance at the midpoint flows is shortened, and radiation noise can be suppressed.

  The insulating member includes a first dielectric filler and a second dielectric filler having different average particle sizes as the dielectric filler, and the average particle size of the second dielectric filler is the average particle size of the first dielectric filler. The average particle size of the conductive filler may be smaller than the average particle size of the second dielectric filler.

  Thus, even when the insulating member includes the first dielectric filler and the second dielectric filler having different average particle diameters as the dielectric filler, the first electrode plate or the second electrode plate and the insulating member (first It becomes easy to spread the conductive filler between the resin material, the first dielectric filler or the second dielectric filler). For this reason, while being able to connect the 1st electrode plate or the 2nd electrode plate, and an insulating member favorably, it becomes possible to control that the capacity ingredient of a capacitor falls.

  The first resin material and the second resin material may be composed of the same resin material. This makes it possible to achieve better adhesiveness.

  The viscosity of the second resin material may be smaller than the viscosity of the first resin material. As a result, the conductive filler and the second resin material constituting the adhesive layer can be obtained by connecting the first electrode plate or the second electrode plate and the insulating member (first resin material, first dielectric filler or second dielectric filler). It becomes easy to get around. For this reason, it becomes possible to suppress more effectively the generation of a gap between the first electrode plate or the second electrode plate and the insulating member.

  According to the present invention, it is possible to improve the degree of freedom of layout or suppress radiation noise.

It is a circuit diagram of the drive system carrying the inverter as a semiconductor device concerning one embodiment of the present invention. FIG. 3 is a simplified external perspective view of a part of one arm series circuit included in the inverter and its periphery. It is sectional drawing in the III-III line of FIG. FIG. 4A is an external configuration diagram schematically illustrating a first surface of the switching element, and FIG. 4B is an external configuration diagram schematically illustrating a second surface of the switching element. It is a circuit diagram which shows the stray capacitance in several points paying attention to one said arm series circuit. It is a figure which shows a part of the mode at the time of manufacturing a 1st and 2nd insulated substrate simply. FIG. 4 is a diagram schematically showing a part of FIG. 3 enlarged in two stages. FIG. 8A is a diagram illustrating a first comparative example, and FIG. 8B is a diagram illustrating a second comparative example. It is a flowchart at the time of laminating | stacking a solid pattern, a 1st insulating substrate, and a positive electrode terminal. It is a circuit diagram of the circuit carrying the inverter as a semiconductor device concerning the 1st modification. It is a simple external appearance block diagram of a part of one arm series circuit included in an inverter as a semiconductor device according to a second modification and its periphery.

I. Embodiment A. 1. Description of configuration Configuration of drive system 10 (1-1. Overall configuration)
FIG. 1 is a circuit configuration diagram of a drive system 10 equipped with an inverter 16 as a semiconductor device according to an embodiment of the present invention. As shown in FIG. 1, the drive system 10 includes an inverter 16, a motor 12, a DC power supply 14 (hereinafter also referred to as “power supply 14”), a capacitor 18, and an electronic control device 20 (hereinafter referred to as “ECU 20”). .)

(1-2. Motor 12)
The motor 12 is a three-phase AC brushless type, and power is supplied from a power source 14 via an inverter 16 controlled by the ECU 20. And the driving force according to the said electric power is produced | generated. The motor 12 can be used, for example, as a driving motor for a vehicle or an assist power generation motor for an electric power steering apparatus. Alternatively, it can be used for other purposes as described later.

(1-3. DC power supply 14)
The DC power source 14 is appropriately selected according to the application of the drive system 10 and can be either a primary battery or a secondary battery. For example, when the motor 12 is used in an application that requires a relatively high output (for example, when used as a vehicle driving motor), the power source 14 is a power storage such as a lithium ion secondary battery, a nickel hydride secondary battery, or a capacitor. It can be a device (energy storage). Further, when the motor 12 is used in an application requiring a relatively low output (for example, when used as an electric power steering device for a vehicle), the power source 14 can be a power storage device such as a lead storage battery.

(1-4. Inverter 16)
The inverter 16 has a three-phase bridge type configuration, performs DC / AC conversion, converts DC from the power supply 14 into three-phase AC, and supplies the AC to the motor 12.

  As shown in FIG. 1, the inverter 16 includes three-phase arm series circuits 30u, 30v, and 30w. The U-phase arm series circuit 30u includes an upper arm 32u having a switching element 34u (hereinafter referred to as "upper SW element 34u") and an anti-parallel diode 36u (hereinafter referred to as "upper diode 36u"), and a switching element 40u (hereinafter referred to as "lower"). SW arm 40u ") and a lower arm 38u having an anti-parallel diode 42u (hereinafter referred to as" lower diode 42u ").

  Similarly, the V-phase arm series circuit 30v includes an upper switching element 34v (hereinafter referred to as “upper SW element 34v”) and an anti-parallel diode 36v (hereinafter referred to as “upper diode 36v”), and a lower arm 32v. The lower arm 38v includes a switching element 40v (hereinafter referred to as “lower SW element 40v”) and an antiparallel diode 42v (hereinafter referred to as “lower diode 42v”). The W-phase arm series circuit 30w includes an upper arm 32w having an upper switching element 34w (hereinafter referred to as “upper SW element 34w”) and an anti-parallel diode 36w (hereinafter referred to as “upper diode 36w”), and a lower switching element 40w. (Hereinafter referred to as “lower SW element 40w”) and a lower arm 38w having an anti-parallel diode 42w (hereinafter referred to as “lower diode 42w”).

  The upper SW elements 34u, 34v, 34w and the lower SW elements 40u, 40v, 40w are, for example, switching elements such as one or a plurality of MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) or insulated gate bipolar transistors (IGBTs). It can consist of Similarly, the upper diodes 36u, 36v, 36w and the lower diodes 42u, 42v, 42w can each be composed of one or more diodes.

  In the following, each arm series circuit 30u, 30v, 30w is generically referred to as an arm series circuit 30, each upper arm 32u, 32v, 32w is generically referred to as an upper arm 32, and each lower arm 38u, 38v, 38w is designated as a lower arm. 38, the upper SW elements 34u, 34v, 34w are collectively referred to as the upper SW element 34, the lower SW elements 40u, 40v, 40w are collectively referred to as the lower SW element 40, and the upper diodes 36u, 36v, 36w The lower diodes 42u, 42v, and 42w are collectively referred to as the lower diode 42.

  In each arm series circuit 30, midpoints 44 u, 44 v, 44 w of the upper arms 32 u, 32 v, 32 w and the lower arms 38 u, 38 v, 38 w are connected to the windings 46 u, 46 v, 46 w of the motor 12. Hereinafter, the middle points 44u, 44v, and 44w are collectively referred to as the middle point 44, and the windings 46u, 46v, and 46w are collectively referred to as the winding 46.

  Each upper SW element 34 and each lower SW element 40 are driven by drive signals UH, VH, WH, UL, VL, WL from the ECU 20.

(1-5.ECU 20)
The ECU 20 controls the output of the motor 12 based on output values from various sensors (not shown). The ECU 20 has an input / output unit, a calculation unit, and a storage unit (all not shown) as a hardware configuration.

2. Details of inverter 16 (2-1. Overall configuration)
FIG. 2 is a simplified external perspective view of a part of one arm series circuit 30 and its periphery. FIG. 3 is a cross-sectional view taken along line III-III in FIG. In the present embodiment, the inverter 16 is configured by arranging three sets of arm series circuits 30 shown in FIGS. 2 and 3 in parallel (see FIG. 1). 2 and 3, “P” indicates the positive electrode side, “N” indicates the negative electrode side, and “OUT” indicates the output side.

  2 and 3 show the upper SW element 34 and the lower SW element 40 of the arm series circuit 30, while the upper diode 36 and the lower diode 42 are not shown.

  In the present embodiment, switching elements (for example, MOSFETs or IGBTs) having the same specifications are used for the upper SW element 34 and the lower SW element 40. 4A and 4B, the upper SW element 34 and the lower SW element 40 of this embodiment have a positive electrode 52 formed on the first surface 50 (drain surface), and the first surface 50 A negative electrode 56 and a gate electrode 58 (control electrode) are formed on the second surface 54 (source surface) on the opposite side. In FIG. 4A, “P” indicates the positive electrode side, and “N” in FIG. 4B indicates the negative electrode side.

  Hereinafter, in order to distinguish the constituent elements of the upper SW element 34 and the lower SW element 40, the positive electrode 52, the negative electrode 56, and the gate electrode 58 of the upper SW element 34 are replaced with the upper positive electrode 52 up, the upper negative electrode 56 up, and the upper gate. The positive electrode 52, the negative electrode 56, and the gate electrode 58 of the lower SW element 40 are referred to as a lower positive electrode 52low, a lower negative electrode 56low, and a lower gate electrode 58low. 2 and 3, illustration of the positive electrode 52, the negative electrode 56, and the gate electrode 58 is omitted.

  As shown in FIGS. 2 and 3, the positive terminal 60, the negative terminal 62, and the output terminal 64 of the inverter 16 are disposed around the upper SW element 34 and the lower SW element 40. The positive terminal 60 is formed on the first insulating substrate 70. The negative terminal 62 is formed on the second insulating substrate 72. The output terminal 64 is formed on the third insulating substrate 74.

  The first insulating substrate 70 insulates the positive electrode terminal 60 from the heat sink 80. The second insulating substrate 72 insulates the negative electrode terminal 62 from the heat sink 80 and has the same composition as the first insulating substrate 70 as a whole. The third insulating substrate 74 insulates the output terminal 64 from the heat sink 80 and is different in composition from the first insulating substrate 70 and the second insulating substrate 72. The first insulating substrate 70, the second insulating substrate 72, and the third insulating substrate 74 are formed on the heat sink 80. The heat sink 80 cools the inverter 16 and is connected to the ground GND (reference potential).

  The positive terminal 60, the negative terminal 62, and the output terminal 64 are plate-shaped conductive members (for example, copper plates). The positive terminal 60 is connected to the positive side of the arm series circuit 30, the negative terminal 62 is connected to the negative side of the arm series circuit 30, and the output terminal 64 is connected to the output side of the arm series circuit 30 (see FIG. 1).

  The positive terminal 60 is fixed to the first insulating substrate 70 via the adhesive layer 90. The negative terminal 62 is fixed to the second insulating substrate 72 through the adhesive layer 90. The output terminal 64 is directly formed on the third insulating substrate 74 as DBC (Direct Bonding Copper).

  The surface of the first insulating substrate 70 and the second insulating substrate 72 on the heat sink 80 side is fixed to the copper solid patterns 100 and 102 via the adhesive layer 90. A copper solid pattern 104 (FIG. 3) is formed as DBC on the surface of the third insulating substrate 74 on the heat sink 80 side. As will be described later, another adhesive layer may be used for joining the third insulating substrate 74 and the output terminal 64 or the solid pattern 104.

  Furthermore, solder, a copper plate, and thermal grease (all not shown) are disposed between the solid patterns 100, 102, 104 and the heat sink 80. That is, the solid patterns 100, 102, and 104 are joined to the copper plate via the solder, and the copper plate is supported by the heat sink 80 via the thermal grease.

  With the configuration as described above, the positive electrode terminal 60 (first electrode plate), the first insulating substrate 70 (insulating member), the adhesive layer 90, and the solid pattern 100 (second electrode plate) constitute the capacitor 110a. Similarly, the negative electrode terminal 62 (first electrode plate), the second insulating substrate 72 (insulating member), the adhesive layer 90, and the solid pattern 102 (second electrode plate) constitute a capacitor 110b.

(2-2. Upper arm 32)
The positive electrode 52 (upper positive electrode 52up) of each upper SW element 34 is joined to the positive terminal 60 of the inverter 16 via solder (not shown) (see FIGS. 2 and 3). These joining may be a joining method such as brazing. In the present embodiment, wiring (distribution member) such as wire bonding or a bus bar is not used for joining the upper positive electrode 52up and the positive terminal 60 and joining the positive side of the upper diode 36 and the positive terminal 60.

  The negative electrode 56 of each upper SW element 34 is connected to the output terminal 64 of the inverter 16 through the wire bonding 120.

(2-3. Lower arm 38)
The positive electrode 52 (lower positive electrode 52low) of each lower SW element 40 is joined to the output terminal 64 of the inverter 16 via solder (not shown) (see FIGS. 2 and 3). These joining may be a joining method such as brazing. In the present embodiment, wiring (wiring member) such as wire bonding or a bus bar is not used for joining the lower positive electrode 52 low and the output terminal 64.

  The negative electrode 56 (lower negative electrode 56 low) of each lower SW element 40 is connected to the negative terminal 62 of the inverter 16 through the wire bonding 122.

B. Floating Capacitance FIG. 5 is a circuit diagram showing stray capacitances C1 to C3 at a plurality of points P1 to P3 by focusing on one arm series circuit 30. Hereinafter, the stray capacitances C1 to C3 at the points P1 to P3 will be described.

  When the arm series circuit 30 is operated, stray capacitances C1 to C3 may be generated between the points P1 to P3 and the ground GND (heat sink 80). Since these stray capacitances C1 to C3 exist, noise is transmitted to the common (power supply 14 side or other equipment side) via the ground GND (heat sink 80) when the upper SW element 34 and the lower SW element 40 are switched, and is conducted. There is a possibility that noise and radiation noise may be generated (see paragraphs [0008] and [0009] of Patent Document 1 for the mechanism of generation of conduction noise and radiation noise, for example).

In general, the impedance Xc of the capacitor is obtained by the following equation (1).
Xc = 1 / (jωC) (1)

  In the above, j is an imaginary unit, ω is an angular frequency [Hz], and C is a capacitance [F].

  According to the above equation (1), in the case of the arm series circuit 30, the higher the switching frequency [Hz] of the upper SW element 34 and the lower SW element 40, the easier the current flows to the stray capacitances C1 to C3. By reducing C, it is possible to make it difficult for current to flow through the stray capacitances C1 to C3. In particular, since the influence of the common mode current Icom flowing from the stray capacitance C2 between the point P2 (the output terminal 64 constituting the middle point 44) where the potential fluctuation occurs due to switching and the ground GND (heat sink 80) to the common side is large, It is important to increase the impedance of the stray capacitance C2.

  On the other hand, if the values of the stray capacitances C1 and C3 are increased, the charges of the stray capacitances C1 and C3 are charged when the stray capacitance C2 is charged. For this reason, the path through which the common mode current Icom caused by the stray capacitance C2 flows is shortened, and radiation noise can be suppressed.

In general, the capacitance C [F] between parallel flat plates (electrode plates) is expressed by the following equation (2).
C = ε0 · ε _s · (S / d) (2)

In the above formula (2), ε0 is the dielectric constant [F / m] of vacuum, ε _s is the relative dielectric constant, S is the area [m ² ] of the electrode plate, and d is between the parallel plates (electrode plates). The gap [m] is shown. According to the above equation (2), the capacitance C increases as the relative dielectric constant ε _s increases.

C. Materials of the first insulating substrate 70, the second insulating substrate 72, the third insulating substrate 74, and the adhesive layer 90 Background As described above, while it is preferable to reduce the stray capacitance C2, it may be preferable to increase the stray capacitances C1 and C3. Therefore, in this embodiment, the first insulating substrate 70 and the second insulating substrate 72 adjust the dielectric constant of the base material 130 (hereinafter also referred to as “first resin material 130”) made of an insulating resin material. After adding the first dielectric filler 132 and the second dielectric filler 134 (additive) for kneading and kneading with the mixer 136 or the like, a sheet 138 (first sheet) is formed and used (see FIG. 6). As such a resin material, for example, an epoxy resin, an imide resin, polyphenylene ether (PPE), bismaleimide triazine (BT resin), a fluororesin, a silicone resin, a phenol resin, or the like can be used (for example, Japanese Patent Laid-Open No. Hei 10). -107448, JP, 2011-10077, A).

  The third insulating substrate 74 is formed by adding a third dielectric filler (additive) (not shown) for adjusting the dielectric constant to the base material 130 made of an insulating resin material, kneading with the mixer 136 or the like, and A sheet not to be used (second sheet) is formed and used.

2. First insulating substrate 70
In the positive electrode terminal 60 laminated together with the first insulating substrate 70, the stray capacitance C3 (FIG. 5) is generated. For this reason, it is preferable that the first insulating substrate 70 has a large dielectric constant in order to increase the stray capacitance C3.

  Therefore, the first dielectric filler 132 and the second dielectric filler 134 (hereinafter also referred to as “first filler 132” and “second filler 134”, respectively) included in the first insulating substrate 70 have a relative dielectric constant. Consists of large materials. As a result, the stray capacitance C3 can be increased and the radiation noise can be reduced.

The first filler 132 and the second filler 134 is, for example, barium titanate (BaTiO _3), constituting a ferroelectric composite material containing a filler made from a single piece or a mixture of strontium titanate (SrTiO ₃₎ or the like. As such a ferroelectric composite material, for example, those described in JP 2001-068803 A and JP 06-172618 A can be used. The relative dielectric constant ε _s of the ferroelectric composite material is preferably 20 or more, for example. In addition, it is also possible to improve thermal conductivity by using the ferroelectric composite material here as a high heat conductive material.

  In the present embodiment, the first filler 132 has a larger average particle diameter than the second filler 134. The average particle diameter of the first filler 132 is, for example, any one of 3 to 7 μm, and the average particle diameter of the second filler 134 is, for example, any one of 0.05 to 0.7 μm. The “average particle size” referred to here indicates, for example, the average value of the maximum particle size or the minimum particle size of each filler. Alternatively, the “average particle diameter” may mean the particle diameter at an integrated value of 50% in the particle size distribution obtained by the laser diffraction / scattering method.

  The ratio of the 1st filler 132 when the sum total of the 1st filler 132 and the 2nd filler 134 is 100 volume% can be 70-80 volume%, for example.

3. Second insulating substrate 72
In the present embodiment, the second insulating substrate 72 is not laminated with either the upper SW element 34 or the lower SW element 40. In addition, the stray capacitance C1 (FIG. 5) is generated in the negative electrode terminal 62 laminated together with the second insulating substrate 72. For this reason, it is preferable that the second insulating substrate 72 has a large dielectric constant in order to increase the stray capacitance C1.

  Therefore, the second insulating substrate 72 is composed of the first filler 132 and the second filler 134 which are ferroelectric composite materials as with the first insulating substrate 70. As a result, the stray capacitance C1 can be increased and radiation noise can be reduced.

4). Third insulating substrate 74
In the output terminal 64 laminated together with the third insulating substrate 74, the stray capacitance C2 (FIG. 5) is generated. For this reason, it is preferable to reduce the dielectric constant in order to reduce the stray capacitance C2.

  Therefore, the third dielectric filler (hereinafter also referred to as “third filler”) included in the third insulating substrate 74 is made of a material having a relatively low dielectric constant. As a result, the stray capacitance C2 can be reduced and the common mode current Icom can be reduced.

The third filler is made of, for example, a low dielectric constant composite material including a filler made of a single substance or a mixture such as silica (SiO ₃ ) and boron nitride (BN). As such a low dielectric constant composite material, for example, those described in JP-A-10-107448 and JP-A-2005-159039 can be used. In this case, for example, the relative dielectric constant ε _s of the low dielectric constant composite material is preferably less than 5.

5. Adhesive layer 90
FIG. 7 is a diagram schematically showing a part of FIG. 3 (adhesive layer 90 and its periphery) enlarged in two stages. FIG. 7 shows the adhesive layer 90 formed between the positive electrode terminal 60 and the solid pattern 100 and the first insulating substrate 70 and its periphery, but the other adhesive layers 90 have the same configuration.

  8A and 8B are diagrams showing first and second comparative examples, both of which correspond to FIG. In both the first comparative example and the second comparative example, the first filler 132 is used for the first insulating substrate 170 (corresponding to the first insulating substrate 70 of the present embodiment), but the second filler 134 is used. And the adhesive layer 90 is not used. In the first comparative example, the addition amount of the first filler 132 is relatively small, and in the second comparative example, the addition amount of the first filler 132 is relatively large.

  In the case of the first comparative example of FIG. 8A, since the amount of the first filler 132 added is small, the adhesion between the first insulating substrate 170 (insulating member) and the electrode plate (the positive electrode terminal 60 or the solid pattern 100) facing the first insulating substrate 170. However, there is a possibility that desired capacity characteristics cannot be obtained.

  On the other hand, in the case of the second comparative example in FIG. 8B, since the amount of the first filler 132 added is large, it is highly possible that desired capacity characteristics can be obtained from the viewpoint of the amount of the first filler 132 added. Become. However, since the density of the first filler 132 is high, a gap 200 is formed between the first insulating substrate 170 (insulating member) and the electrode plate (positive electrode terminal 60 or solid pattern 100) facing the first insulating substrate 170 (insulating member). As a result, the capacity characteristic is deteriorated due to the influence of the gap 200.

  In addition, the viscosity of the base material 130 is high before the base material 130 constituting the first insulating substrate 170 is cured, and the gap 200 is easily generated even when the base material 130 is applied in a sheet form.

  Furthermore, when the addition amount of the first filler 132 is increased, a region where the base material 130 functions as an adhesive is insufficient, and sufficient adhesion with the electrode plate (the positive electrode terminal 60 or the solid pattern 100) facing the first insulating substrate 170 is achieved. May not be obtained.

  Furthermore, even when the surface roughness of the electrode plate (the positive electrode terminal 60 or the solid pattern 100) facing the first insulating substrate 170 is large, the gap 200 is likely to occur after the bonding with the first insulating substrate 170.

  Therefore, in the present embodiment, the above-described problem is solved by providing the adhesive layer 90.

  As shown in FIG. 7, the adhesive layer 90 includes a resin material (second resin material 140) as a base material and a conductive filler 142 added to the second resin material 140. The second resin material 140 is, for example, the same resin material as the first resin material 130. However, the second resin material 140 may be a resin material different from the first resin material 130. In this case, a material different from the first resin material 130 among the materials that can be employed as the first resin material 130 described above can be used.

  Moreover, the 2nd resin material 140 makes a viscosity lower than the 1st resin material 130 by making density | concentration lower than the 1st resin material 130, for example. As a result, the second resin material 140 can easily enter between the first resin material 130 or the first dielectric filler 132 or the second dielectric filler 134.

  The conductive filler 142 can be, for example, metal particles such as silver and nickel. Alternatively, the conductive filler 142 may be carbon particles.

  The conductive filler 142 of this embodiment has an average particle size smaller than that of the first filler 132 and the second filler 134. As a result, the conductive filler 142 can easily enter between the first resin material 130 or the first filler 132 or the second filler 134. As a result, the generation of the gap 200 can be suppressed. As a result, the distribution of charges in the capacitors 110a and 110b becomes uniform, so that improvement in insulation reliability can be expected.

  In addition, when the average particle diameter of the conductive filler 142 is smaller than that of the first filler 132 and the second filler 134, the electrode plate (the positive electrode terminal 60, which faces the first insulating substrate 70 and the second insulating substrate 72 (insulating member)). The electrical contact area with the negative electrode terminal 62 and the solid patterns 100 and 102) increases. Thereby, an effective ferroelectric layer increases and the capacitance of the capacitors 110a and 110b can be increased.

  The average particle diameter of the conductive filler 142 can be any of 0.01 to 0.3 μm, for example. The maximum particle size of the conductive filler 142 is preferably at least smaller than the minimum particle size of the first filler 132, and more preferably smaller than the minimum particle size of the second filler 134.

D. Manufacturing Method FIG. 9 is a flowchart when the solid pattern 100, the first insulating substrate 70, and the positive electrode terminal 60 are stacked. The same applies when the solid pattern 102, the second insulating substrate 72, and the negative electrode terminal 62 are laminated.

  In step S <b> 1, the material of the adhesive layer 90 (second resin material 140 to which the conductive filler 142 is added) is applied to the solid pattern 100 to form the adhesive layer 90. In step S <b> 2, the semi-cured first insulating substrate 70 (the first resin material 130, the first filler 132, and the second filler 134) is applied to the solid pattern 100. In step S <b> 3, the material for the adhesive layer 90 (the second resin material 140 to which the conductive filler 142 is added) is applied to the first insulating substrate 70 to form the adhesive layer 90.

  In step S <b> 4, the positive electrode terminal 60 is disposed on the first insulating substrate 70. The positive electrode terminal 60 of the present embodiment is a plate-like member, but may be a sheet shape (foil shape). Alternatively, the positive electrode terminal 60 can be formed on the first insulating substrate 70 by sputtering or plating. However, when the positive electrode terminal 60 as the plate-like member is used, the size of the positive electrode terminal 60 is easily increased, so that it becomes easier to flow a larger current or improve the heat dissipation.

  In step S5, the first insulating substrate 70 (first resin material 130) and the adhesive layer 90 (second resin material 140) are thermally cured. In this embodiment, the temperature at which the first resin material 130 and the second resin material 140 are thermally cured is lower than the temperature when the positive electrode terminal 60 and the first insulating substrate 70 are joined using solder.

E. As described above, according to the present embodiment, the configuration of the capacitors 110a and 110b can improve the degree of freedom of layout or suppress radiation noise.

  That is, according to the present embodiment, the adhesive layer 90 that bonds the positive electrode terminal 60 (first electrode plate) or the solid pattern 100 (second electrode plate) and the first insulating substrate 70 (insulating member) is the first dielectric. The second resin material 140 to which the conductive filler 142 having an average particle size smaller than that of the body filler 132 and the second dielectric filler 134 is added is included. For this reason, the conductive filler 142 or the second resin material 140 enters the gap 200 between the positive electrode terminal 60 or the solid pattern 100 and the first insulating substrate 70. Therefore, even when a dielectric filler (first filler 132) having a relatively large average particle size is added to the first insulating substrate 70 (first resin material 130) in order to give the capacitor 110a desired capacitance characteristics, the positive electrode Generation of the gap 200 between the terminal 60 or the solid pattern 100 and the first insulating substrate 70 can be suppressed. Therefore, even when the amount of the first filler 132 added to the first insulating substrate 70 (the first resin material 130) is increased, it is possible to prevent the capacity characteristics from being deteriorated due to the generation of the gap 200. As a result, the stray capacitance C3 at the positive electrode terminal 60 can be relatively increased.

  The same applies to the capacitor 110b (the negative electrode terminal 62, the second insulating substrate 72, the adhesive layer 90, and the solid pattern 102), and the stray capacitance C1 in the negative electrode terminal 62 can be relatively increased.

  From the above, for example, when the first insulating substrate 70 and the adhesive layer 90 are provided between the positive electrode terminal 60 and the heat sink 80 (ground), the area of the output terminal 64 does not have to be smaller than the area of the positive electrode terminal 60. In addition, the stray capacitance C3 at the positive electrode terminal 60 can be increased. Alternatively, instead of making the area of the output terminal 64 smaller than the area of the positive electrode terminal 60, the stray capacitance C3 at the positive electrode terminal 60 is increased without making the distance between the positive electrode terminal 60 and the heat sink 80 (ground) less than a certain distance. It becomes possible to do. Therefore, the degree of freedom in layout can be improved.

  Further, by increasing the stray capacitances C3 and C1 at the positive terminal 60 or the negative terminal 62 as described above, the midpoint between the upper SW element 34 (first switching element) and the lower SW element 40 (second switching element). When the stray capacitance C2 at 44 is charged, the charges of the stray capacitances C3 and C1 at the positive terminal 60 or the negative terminal 62 are charged. For this reason, the path through which the common mode current due to the stray capacitance C2 at the midpoint 44 flows is shortened, and radiation noise can be suppressed.

  In the present embodiment, the temperature at which the first resin material 130 and the second resin material 140 are thermally cured is lower than the temperature at which the positive electrode terminal 60 and the first insulating substrate 70 are bonded using solder. When the positive electrode terminal 60 and the first insulating substrate 70 are joined using solder instead of the adhesive layer 90, the characteristics of the first resin material 130, the first filler 132, or the second filler 134 during heating to melt the solder May adversely affect However, in this embodiment, it is possible to reduce the risk of such adverse effects.

  In the present embodiment, the first insulating substrate 70 (insulating member) includes the first filler 132 and the second filler 134 having different average particle diameters as dielectric fillers, and the average particle diameter of the second filler 134 is the first filler. The average particle size of the conductive filler 142 is smaller than the average particle size of the second filler 134 (see FIG. 7).

  Thus, even when the first insulating substrate 70 includes the first filler 132 and the second filler 134 having different average particle diameters as dielectric fillers, the positive electrode terminal 60 (first electrode plate) or the solid pattern 100 ( It becomes easy to spread the conductive filler 142 between the second electrode plate) and the first insulating substrate 70 (the first resin material 130, the first filler 132, or the second filler 134). For this reason, it is possible to satisfactorily connect the positive electrode terminal 60 or the solid pattern 100 and the first insulating substrate 70, and it is possible to suppress a decrease in the capacitance component of the capacitor 110a. The same applies to the capacitor 110b.

  In the present embodiment, the first resin material 130 and the second resin material 140 are made of the same resin material. This makes it possible to achieve better adhesiveness.

  In the capacitor 110 a of this embodiment, the viscosity of the second resin material 140 is smaller than the viscosity of the first resin material 130. Thereby, the conductive filler 142 and the second resin material 140 constituting the adhesive layer 90 are replaced with the positive electrode terminal 60 or the solid pattern 100 and the first insulating substrate 70 (the first resin material 130, the first filler 132, or the second filler 134. ) And it becomes easy to spread between. For this reason, generation | occurrence | production of the clearance gap 200 between the positive electrode terminal 60 or the solid pattern 100, and the 1st insulated substrate 70 can be suppressed more effectively. The same applies to the capacitor 110b.

II. Modifications It should be noted that the present invention is not limited to the above-described embodiment, and it is needless to say that various configurations can be adopted based on the description of the present specification. For example, the following configuration can be adopted.

A. Inverter 16 and drive system 10
In the above embodiment, the three-phase bridge type inverter 16 is used. However, an inverter having a single-phase or multi-phase arm series circuit in which an upper arm and a lower arm having a switching element and an antiparallel diode are connected in series may be used. For example, it is not limited to this. For example, as shown in FIG. 10, it can be applied to a single-phase bridge type inverter 16a. The inverter 16 a in FIG. 10 converts the direct current from the direct current power source 14 into alternating current and supplies the alternating current to the winding 46 a (load) and the resistor 180.

  The inverter 16a has two arm series circuits 30a and 30b. The arm series circuit 30a includes an upper arm 32a having a switching element 34a (hereinafter referred to as “upper SW element 34a”) and an anti-parallel diode 36a (hereinafter referred to as “upper diode 36a”), and a switching element 40a (hereinafter referred to as “lower SW element”). Element 40a ") and a lower arm 38a having an antiparallel diode 42a (hereinafter referred to as" lower diode 42a "). Similarly, the arm series circuit 30b includes an upper arm 32b having a switching element 34b (hereinafter referred to as “upper SW element 34b”) and an anti-parallel diode 36b (hereinafter referred to as “upper diode 36b”), and a switching element 40b (hereinafter referred to as “upper SW element 34b”). And a lower arm 38b having an anti-parallel diode 42b (hereinafter referred to as "lower diode 42b").

  Also in the inverter 16a, the adhesive layer 90 is provided between the positive electrode terminal 60 or the solid pattern 100 and the first insulating substrate 70, and the adhesive layer 90 is provided between the negative electrode terminal 62 or the solid pattern 102 and the second insulating substrate 72. be able to. As a result, it is possible to improve the degree of freedom of layout or suppress conduction noise and radiation noise.

  In the above embodiment and the modification of FIG. 10, the example in which the present invention is applied to the inverters 16 and 16a has been described. However, an upper arm and a lower arm each having a switching element and an antiparallel diode are connected in series. If it is a semiconductor device provided with a phase arm series circuit, it will not be restricted to this. For example, the present invention can be applied to a step-up / step-down and chopper type DC / DC converter (see, for example, FIG. 1 and FIG. 9 of JP 2009-153343 A).

  In the above embodiment, the positive terminal 60, the output terminal 64, and the negative terminal 62 are arranged in this order from the left side in FIGS. 2 and 3, but the arrangement in the inverter 16 is not limited to this. For example, the present invention can be applied to the inverter 16b arranged as shown in FIG. In the arm series circuit 30c of the inverter 16b in FIG. 11, the output terminal 64, the positive terminal 60, and the negative terminal 62 are arranged in this order from the left in FIG. Even in such a configuration, the adhesive layer 90 is provided between the positive electrode terminal 60 or the solid pattern 100 and the first insulating substrate 70, and the adhesive layer 90 is provided between the negative electrode terminal 62 or the solid pattern 102 and the second insulating substrate 72. By providing the above, it is possible to obtain the same effect as in the above embodiment.

  Or in the said embodiment and the modification of FIG. 11, each of the positive electrode terminal 60, the negative electrode terminal 62, and the output terminal 64 was arrange | positioned on the common heat sink 80, For example, the heat sink 80 is shown on the upper side and lower side of FIG. The positive terminal 60 and the negative terminal 62 may be disposed corresponding to the upper heat sink 80, and the output terminal 64 may be disposed corresponding to the lower heat sink 80.

  Alternatively, as long as the semiconductor device includes a series circuit in which a plurality of switching elements are connected in series, an antiparallel diode may not be provided. For example, the present invention can be applied to a NAND flash memory.

  In the above embodiment, the motor 12 of the drive system 10 is, for example, for driving a vehicle or for electric power steering. However, for example, if attention is paid to an increase in the stray capacitances C1, C3, the motor 12 is not limited thereto. For example, you may use for the motor in a washing machine, a vacuum cleaner, an air conditioner, a refrigerator, an electromagnetic cooker, an alternating current (AC) servo, a railway vehicle, and an elevator.

  In the above embodiment, the drive system 10 drives the motor 12. However, for example, if attention is paid to an increase in the stray capacitances C1 and C3, the drive system 10 is not limited thereto. For example, the drive system 10 can also be used for an inverter in a power conditioner for an uninterruptible power supply, solar power generation or wind power generation (see, for example, FIG. 4 of JP 2011-103497 A).

B. Gate electrode 58
In the above embodiment, in the upper SW element 34 and the lower SW element 40, the gate electrode 58 is formed on the same surface (second surface 54) as the negative electrode 56 (FIG. 4B). Not exclusively.

  For example, a configuration in which the gate electrode 58 is formed on the same surface (first surface 50) as the positive electrode 52 and the gate electrode 58 is not formed on the same surface (second surface 54) as the negative electrode 56 is possible. In this case, it is preferable that the negative electrode 56 of the upper SW element 34 is bonded to the output terminal 64 and the negative electrode 56 of the lower SW element 40 is bonded to the negative terminal 62.

C. First insulating substrate 70, second insulating substrate 72, and base material 130 of adhesive layer 90
In the above embodiment, the base material 130 of the first insulating substrate 70, the second insulating substrate 72, and the adhesive layer 90 is made of a common material (resin material). However, the first insulating substrate 70, the second insulating substrate 72, and the adhesive are bonded. It is also possible to change the material of the base material 130 for each layer 90.

D. Adhesive layer 90
In the above embodiment, the adhesive layers 90 are provided at four locations. That is, between the positive electrode terminal 60 and the first insulating substrate 70, between the first insulating substrate 70 and the solid pattern 100 (heat sink 80), between the negative electrode terminal 62 and the second insulating substrate 72, and between the second insulating substrate 72 and An adhesive layer 90 was provided between the solid patterns 102 (heat sink 80). However, it is also possible to provide the adhesive layer 90 only at any one, two or three places.

  Further, from the viewpoint of increasing the stray capacitances C1 and C3, it is not always necessary that the adhesive layer 90 is in direct contact with the positive electrode terminal 60 or the negative electrode terminal 62 itself as a plate-like member. For example, the adhesive layer 90 may be provided between the electrode plate electrically connected to the positive electrode terminal 60 and the first insulating substrate 70. In other words, the electrode plate that forms the capacitor 110a together with the first insulating substrate 70 may not be the positive electrode terminal 60 itself. In this case, the adhesive layer 90 can also be provided at a place other than below the upper switching element 34. Similarly, an adhesive layer 90 can be provided between the electrode plate electrically connected to the negative electrode terminal 62 and the second insulating substrate 72.

  In the above embodiment, the average particle size of the conductive filler 142 is smaller than the average particle size of each of the first filler 132 and the second filler 134. However, for example, from the viewpoint of preventing the gap 200 formed due to the larger (or largest) first filler 132 having an average particle size, the average particle size of the conductive filler 142 is set to the first filler. It may be smaller than 132 and may be equal to or larger than the second filler 134.

  In the above embodiment, two types of fillers, the first filler 132 and the second filler 134, are used as the dielectric filler added to the first resin material 130. However, for example, from the viewpoint of the dielectric constant of the first insulating substrate 70 and the second insulating substrate 72, only one of the first filler 132 and the second filler 134 may be used. Alternatively, another dielectric filler having an average particle diameter different from that of the first filler 132 and the second filler 134 can be used together.

  In the above embodiment, the first filler 132 and the second filler 134 are made of the same material. However, for example, from the viewpoint of the dielectric constant of the first insulating substrate 70 and the second insulating substrate 72, the materials of the first filler 132 and the second filler 134 may be different.

  In the above embodiment, the viscosity of the second resin material 140 is made smaller than the viscosity of the first resin material 130. However, for example, when attention is paid to the presence of the conductive filler 142 entering the gap 200, the viscosity of the second resin material 140 can be equal to or greater than the viscosity of the first resin material 130.

  In the embodiment described above, the layer disposed between the positive electrode terminal 60 and the first insulating substrate 70 is the adhesive layer 90. However, from the viewpoint of a member that fills the gap 200, an intervening layer that does not exhibit adhesive performance is provided. May be. The same applies to the adhesive layer 90 disposed other than between the positive electrode terminal 60 and the first insulating substrate 70.

E. Others In the above embodiment, the solid pattern 100, the first insulating substrate 70, and the positive electrode terminal 60 are laminated by the method shown in FIG. 9, but for example, when focusing on the configuration of the capacitor 110a, these are laminated by other methods. You may let them. The same applies to the capacitor 110b.

  In the above embodiment, the adhesive layer 90 is provided corresponding to the first insulating substrate 70 and the second insulating substrate 72. For example, the adhesion between the electrode plate facing the insulating member and the insulating member is improved or the dielectric constant is adjusted. From this point of view, it is possible to provide another adhesive layer between the output terminal 64 or the solid pattern 104 and the third insulating substrate 74. In this case, in order to reduce the stray capacitance C2, a low dielectric constant filler can be added to the adhesive layer.

16, 16a, 16b ... Inverter (semiconductor device)
30, 30a, 30b, 30c, 30u, 30v, 30w ... arm series circuit (series circuit)
34: Upper switching element (first switching element)
40. Lower switching element (second switching element)
60 ... Positive terminal (first electrode plate) 62 ... Negative terminal (first electrode plate)
70: First insulating substrate (insulating member) 72 ... Second insulating substrate (insulating member)
80 ... Heat sink (ground) 90 ... Adhesive layer 100, 102 ... Solid pattern (second electrode plate)
110a, 110b ... capacitor 130 ... base material (first resin material)
132 ... 1st filler (1st dielectric filler)
134 ... second filler (second dielectric filler)
140: second resin material 142: conductive filler

Claims (4)

A semiconductor device comprising one or more series circuits in which a first switching element and a second switching element are connected in series between a positive terminal and a negative terminal,
The semiconductor device includes:
An insulating member sandwiched between a first electrode plate made of the positive electrode terminal itself or the negative electrode terminal itself or the positive electrode terminal or an electrode plate electrically connected to the negative electrode terminal and a second electrode plate on the ground side;
An adhesive layer for bonding the first electrode plate or the second electrode plate and the insulating member;
The insulating member includes a first resin material to which a dielectric filler is added,
The adhesive layer includes a second resin material to which a conductive filler having an average particle size smaller than that of the dielectric filler is added,
A capacitor is constituted by the first electrode plate, the second electrode plate, the insulating member, and the adhesive layer. The semiconductor device according to claim 1,
The insulating member includes a first dielectric filler and a second dielectric filler having different average particle diameters as the dielectric filler,
The average particle size of the second dielectric filler is smaller than the average particle size of the first dielectric filler,
The average particle diameter of the said conductive filler is smaller than the average particle diameter of the said 2nd dielectric filler. The semiconductor device characterized by the above-mentioned. The semiconductor device according to claim 1 or 2,
The first resin material and the second resin material are made of the same resin material. A semiconductor device, wherein: The semiconductor device according to any one of claims 1 to 3,
The viscosity of the second resin material is smaller than the viscosity of the first resin material. A semiconductor device, wherein:

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