JP6143590B2 - 記憶素子及びプログラマブルロジックデバイス - Google Patents

記憶素子及びプログラマブルロジックデバイス Download PDF

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Publication number
JP6143590B2
JP6143590B2 JP2013147153A JP2013147153A JP6143590B2 JP 6143590 B2 JP6143590 B2 JP 6143590B2 JP 2013147153 A JP2013147153 A JP 2013147153A JP 2013147153 A JP2013147153 A JP 2013147153A JP 6143590 B2 JP6143590 B2 JP 6143590B2
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transistor
film
wiring
oxide semiconductor
drain
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Japanese (ja)
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JP2014038684A (ja
JP2014038684A5 (https=
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池田　隆之
隆之 池田
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17764—Structural details of configuration resources for reliability
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17758—Structural details of configuration resources for speeding up configuration or reconfiguration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices

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  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)
  • Dram (AREA)
  • Non-Volatile Memory (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Logic Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electronic Switches (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2013147153A 2012-07-18 2013-07-15 記憶素子及びプログラマブルロジックデバイス Expired - Fee Related JP6143590B2 (ja)

Priority Applications (1)

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JP2012159449 2012-07-18
JP2012159449 2012-07-18
JP2013147153A JP6143590B2 (ja) 2012-07-18 2013-07-15 記憶素子及びプログラマブルロジックデバイス

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JP2014038684A JP2014038684A (ja) 2014-02-27
JP2014038684A5 JP2014038684A5 (https=) 2016-08-25
JP6143590B2 true JP6143590B2 (ja) 2017-06-07

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JP2013147153A Expired - Fee Related JP6143590B2 (ja) 2012-07-18 2013-07-15 記憶素子及びプログラマブルロジックデバイス
JP2017093215A Expired - Fee Related JP6325149B2 (ja) 2012-07-18 2017-05-09 記憶素子、及びプログラマブルロジックデバイス
JP2018076041A Active JP6516897B2 (ja) 2012-07-18 2018-04-11 半導体装置
JP2019077487A Withdrawn JP2019153796A (ja) 2012-07-18 2019-04-16 半導体装置
JP2021014819A Withdrawn JP2021073724A (ja) 2012-07-18 2021-02-02 半導体装置
JP2022125349A Withdrawn JP2022159399A (ja) 2012-07-18 2022-08-05 記憶素子

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JP2018076041A Active JP6516897B2 (ja) 2012-07-18 2018-04-11 半導体装置
JP2019077487A Withdrawn JP2019153796A (ja) 2012-07-18 2019-04-16 半導体装置
JP2021014819A Withdrawn JP2021073724A (ja) 2012-07-18 2021-02-02 半導体装置
JP2022125349A Withdrawn JP2022159399A (ja) 2012-07-18 2022-08-05 記憶素子

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US (2) US8934299B2 (https=)
JP (6) JP6143590B2 (https=)
KR (6) KR102107591B1 (https=)
TW (2) TWI638431B (https=)

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JP6333028B2 (ja) * 2013-04-19 2018-05-30 株式会社半導体エネルギー研究所 記憶装置及び半導体装置
JP6625328B2 (ja) * 2014-03-06 2019-12-25 株式会社半導体エネルギー研究所 半導体装置の駆動方法
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KR102107591B1 (ko) 2020-05-07
JP2022159399A (ja) 2022-10-17
US9985636B2 (en) 2018-05-29
KR20210012032A (ko) 2021-02-02
KR102368444B1 (ko) 2022-02-25
TWI638431B (zh) 2018-10-11
KR20200047485A (ko) 2020-05-07
KR102150574B1 (ko) 2020-09-01
TWI608569B (zh) 2017-12-11
US20150123705A1 (en) 2015-05-07
JP2021073724A (ja) 2021-05-13
JP2014038684A (ja) 2014-02-27
TW201413874A (zh) 2014-04-01
JP6516897B2 (ja) 2019-05-22
US20140021474A1 (en) 2014-01-23
KR20140011260A (ko) 2014-01-28
KR20200103597A (ko) 2020-09-02
JP6325149B2 (ja) 2018-05-16
KR20220027128A (ko) 2022-03-07
US8934299B2 (en) 2015-01-13
KR102436903B1 (ko) 2022-08-25
JP2019153796A (ja) 2019-09-12
KR102556197B1 (ko) 2023-07-14
JP2017182869A (ja) 2017-10-05
KR20220119590A (ko) 2022-08-30
JP2018139165A (ja) 2018-09-06
TW201810538A (zh) 2018-03-16
KR102210818B1 (ko) 2021-02-01

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