JP6124681B2 - ルックアップテーブル、及びルックアップテーブルを備えるプログラマブルロジックデバイス - Google Patents
ルックアップテーブル、及びルックアップテーブルを備えるプログラマブルロジックデバイス Download PDFInfo
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- JP6124681B2 JP6124681B2 JP2013105768A JP2013105768A JP6124681B2 JP 6124681 B2 JP6124681 B2 JP 6124681B2 JP 2013105768 A JP2013105768 A JP 2013105768A JP 2013105768 A JP2013105768 A JP 2013105768A JP 6124681 B2 JP6124681 B2 JP 6124681B2
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- oxide semiconductor
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- oxide
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- NAWDYIZEMPQZHO-UHFFFAOYSA-N ytterbium Chemical compound [Yb] NAWDYIZEMPQZHO-UHFFFAOYSA-N 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- H03—ELECTRONIC CIRCUITRY
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- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
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Description
本実施の形態では、本発明の一態様に係るプログラマブルロジックデバイスの一形態について、図1乃至図7を参照して説明する。
本実施の形態では、半導体装置の作製方法について説明する。具体的には、先の実施の形態に示すメモリ素子13の作製方法について、図8乃至図14を参照して説明する。なお、図8乃至図10は、メモリ素子の主要な配線、コンタクトプラグ等の構造物の位置と平面形状を表し、図11乃至図14は、メモリ素子の作製方法を示す断面図を表し、図8乃至図10の折れ線A−Bに沿った断面を模式的に示す。
13a メモリ素子
13m メモリ素子
13p メモリ素子
13q メモリ素子
100 プログラマブルロジックデバイス
101 トランジスタ
102 トランジスタ
103 トランジスタ
104 容量素子
110 論理ブロック
110A 論理ブロック
110B 論理ブロック
111 ルックアップテーブル
112 レジスタ
113 メモリ
120 スイッチブロック
301 nウェル領域
302 pウェル領域
303 素子分離絶縁層
304 ゲート絶縁層
305 ゲート電極層
306a n+領域
306b n+領域
306c n+領域
307a p+領域
307b p+領域
307c p+領域
308 サイドウォール絶縁層
309 絶縁膜
310a コンタクトプラグ
310g コンタクトプラグ
311a 配線層
311d 配線層
312 絶縁膜
313 コンタクトプラグ
314a 配線層
314b 配線層
315 埋め込み絶縁層
316 ゲート絶縁膜
317 開口
318 酸化物半導体層
319a 導電層
319b 導電層
319c 導電層
320 絶縁膜
321 導電層
322 絶縁膜
331 トランジスタ
332 トランジスタ
333 トランジスタ
334 容量素子
414a 配線層
414b 配線層
415 埋め込み絶縁層
416 ゲート絶縁層
418 酸化物半導体層
419a 導電層
419b 導電層
420 絶縁膜
421 導電層
433 トランジスタ
434 容量素子
Claims (4)
- 複数のメモリ素子と、
第1及び第2の入力端子を有する複数のマルチプレクサと、を有し、
前記複数のマルチプレクサは、バイナリツリー状に多段に電気的に接続され、
最下位の段のマルチプレクサ各々の第1及び第2の入力端子に、前記メモリ素子がそれぞれ電気的に接続され、
前記メモリ素子は、
チャネル幅1μmあたりのオフ電流が100zA以下の第1のトランジスタと、n型の第2のトランジスタと、p型の第3のトランジスタと、容量素子と、を有し、
前記第1のトランジスタのソース又はドレインの一方は、前記容量素子の一対の電極の一方と、前記第2のトランジスタのゲートと、前記第3のトランジスタのゲートと電気的に接続され、
前記第2のトランジスタのソース又はドレインの一方は、前記第3のトランジスタのソース又はドレインの一方と電気的に接続され、
前記容量素子の一対の電極の一方の電位を、前記容量素子の一対の電極の他方との容量結合により、前記第2のトランジスタがオン状態となる電位または第3のトランジスタがオン状態となる電位とする、ルックアップテーブル。 - 請求項1において、
前記第3のトランジスタのゲートの電位と前記第2のトランジスタのソース又はドレインの他方の電位との差との最大値を、前記第3のトランジスタのソース又はドレインの他方の電位と、前記第2のトランジスタのソース又はドレインの他方の電位との差よりも大きくする、ルックアップテーブル。 - 請求項1又は2において、
前記第2のトランジスタのチャネル長は、前記第3のトランジスタのチャネル長の2倍以上である、ルックアップテーブル。 - 請求項1乃至3のいずれかに記載されたルックアップテーブルを含むプログラマブルロジックデバイス。
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US9992067B1 (en) * | 2015-05-13 | 2018-06-05 | Level 3 Communications, Llc | Communication network multiplexer grooming optimization |
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US9007090B2 (en) | 2012-05-01 | 2015-04-14 | Semiconductor Energy Laboratory Co., Ltd. | Method of driving semiconductor device |
US8952723B2 (en) * | 2013-02-13 | 2015-02-10 | Semiconductor Energy Laboratory Co., Ltd. | Programmable logic device and semiconductor device |
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2013
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US10229913B2 (en) | 2019-03-12 |
US9571103B2 (en) | 2017-02-14 |
US20130314123A1 (en) | 2013-11-28 |
US20170133381A1 (en) | 2017-05-11 |
JP2017139797A (ja) | 2017-08-10 |
JP2014003597A (ja) | 2014-01-09 |
JP6676575B2 (ja) | 2020-04-08 |
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