JP6110686B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to the production how a semiconductor device, in particular, both the slow trap inhibition of P-type MOS transistor using a silicon nitride film, and a low 1 / f noise of the N-type MOS transistor and a P-type MOS transistor It relates to the production how a semiconductor device capable.

  In recent years, as the miniaturization of semiconductor integrated circuits has progressed, various problems have arisen in various elements, and one of them is a change in threshold voltage over time due to a slow trap. Si-H bonds exist at the Si-SiO2 interface immediately below the gate oxide insulating film. When a high electric field with a negative bias is applied to the gate electrode, the Si—H bond is broken and hydrogen is desorbed, and a dangling bond (dangling bond) is generated to increase the degree of carrier trapping. The threshold voltage (Vth) varies with time. This phenomenon is called Vth shift or slow trap. Slow traps are known to become prominent at high temperatures / high electric fields, and as the gate length is shorter, the amount of fluctuation in threshold voltage is larger. Therefore, in situations where higher product specifications or smaller devices are required. Is a major obstacle.

  Various solutions have already been found for the slow trap problem. Among them, the entire element is covered with a silicon nitride film to prevent outward diffusion of hydrogen desorbed from the Si-H bond. A method for suppressing fluctuations in threshold voltage is widely known (see Non-Patent Document 1). In Patent Document 1, nitrogen having a binding energy higher than that of hydrogen is terminated at a dangling bond to suppress desorption, and the entire element is covered with a silicon nitride film to prevent nitrogen from diffusing outwardly. A method for further suppressing the fluctuation amount is disclosed.

  The method of covering the entire element with a silicon nitride film is used in various other applications, and the channel portion of a MOS transistor (MOSFET) is distorted by the stress of the silicon nitride film to improve the mobility (DSL (Dual Stress Liner)). Technology has attracted attention in recent years. As disclosed in Patent Document 2, the mobility is improved by applying tensile strain to the N-type MOS transistor and compressive strain to the P-type MOS transistor. This is a method of selectively depositing silicon nitride films (liner films) with stresses in the direction of improving N-type and P-type MOS transistors, and improving MOS transistor characteristics without the need for new production methods during manufacturing. It is a technology that can.

  On the other hand, flicker noise (1 / f noise), which increases on the contrary as the area of the MOS transistor is reduced, cannot be ignored because it is often cited as a problem in recent semiconductor devices where the chip size is being reduced. Non-Patent Document 2 shows the relationship between the stress of the liner film and 1 / f noise, and it is assumed that there is liner film stress at which the 1 / f noise of the MOS transistor is optimal.

JP-A-10-209444 Special table 2010-530127

M.M. Noyori, and T.K. Ishihara “SECONDARY SLOW TRAPPING-A NEW MOISTURE INDUCED INSTABILITY PHENOMENON IN SCALED CMOS DEVICES” Matsushita Electric Industrial Co. , Ltd., Ltd. Semiconductor Research Research Laboratory Signenobu Maeda “Impact of Mechanical Stress Engineering on Flicker Noise Characteristics”

However, in Patent Documents 1 and 2 and Non-Patent Document 1 in which a silicon nitride film is deposited on a MOS transistor for the purpose of suppressing slow traps and improving mobility, 1 / of the MOS transistor that becomes a problem as the chip size is reduced. f No consideration is given to noise.
Therefore, the present invention has been made in view of such circumstances. Slow trap suppression of a P-type MOS transistor using a silicon nitride film and low 1 / f of an N-type MOS transistor and a P-type MOS transistor are achieved. and an object thereof is to provide a manufacturing how a semiconductor apparatus which can achieve both noise reduction.

  As a result of intensive studies, the present inventor has found that when the P-type MOS transistor is a buried channel type, the silicon nitride film deposited on the MOS transistor does not affect the 1 / f noise. Further, in a semiconductor device in which an N-type MOS transistor and a P-type MOS transistor are mixedly mounted, a silicon nitride film is selectively deposited only on the P-type MOS transistor, thereby suppressing a slow trap and an N-type MOS transistor and It has been found that both P-type MOS transistors can be kept at low 1 / f noise.

That is, in order to solve the above-described problem, according to a method for manufacturing a semiconductor device according to one embodiment of the present invention, a step of forming a surface channel N-type MOS transistor in a first region of a substrate, Forming a buried channel type P-type MOS transistor in a second region different from the first region; and depositing a silicon nitride film on the substrate to form the N-type MOS transistor and the P-type MOS transistor. Covering the silicon nitride film, partially etching the silicon nitride film to remove the silicon nitride film from the N-type MOS transistor, and leaving the silicon nitride film on the P-type MOS transistor; Yes and, after the silicon nitride film is partially etched, and wherein the performing hydrogen annealing on the substrate.

  Here, the buried channel type MOS transistor is a MOS transistor formed in the substrate whose channel is deeper than the interface between the gate insulating film and the substrate. According to the present invention, a MOS transistor in which a channel is formed in a range from 0.03 to 0.04 μm away from the interface in the direction from the interface toward the inside of the substrate (ie, in the depth direction of the substrate) is embedded channel type MOS. It is called a transistor.

Also, in the above-described method for manufacturing a semiconductor device, in the step of depositing said silicon nitride film may also be characterized by depositing the silicon nitride film by LPCVD (Low Pressre Chemical Vapor Deposition) method. Here, the LPCVD method is a CVD method in which film formation is performed in a low-pressure atmosphere of, for example, 15 to 25 [Pa].

  According to one embodiment of the present invention, the P-type MOS transistor is a buried channel type, and the channel is formed inside the substrate deeper than the interface between the gate insulating film and the substrate. As a result, in the P-type MOS transistor, it is possible to make it less susceptible to the influence of the interface state (for example, due to dangling bonds) between the gate insulating film and the substrate, and 1 / f noise can be kept low. .

  In addition, by covering the P-type MOS transistor with the silicon nitride film, it is possible to prevent hydrogen, water, etc. from diffusing into the P-type MOS transistor under the silicon nitride film, and a hole trap at the interface between the gate insulating film and the substrate. Can be prevented. Thereby, Vth shift (that is, slow trap) can be suppressed in the P-type MOS transistor. Also for the N-type MOS transistor, 1 / f noise can be kept low.

It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment in process order. FIG. 6 is a diagram comparing noise coefficients Kf with and without nitriding for a surface channel type N-type MOS transistor. FIG. 9 is a diagram comparing noise coefficients Kf with and without nitriding for buried channel type P-type MOS transistors. FIG. 6 is a diagram comparing Vth shifts of nitriding with and without a nitride film for a buried channel P-type MOS transistor.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. Note that, in each drawing described below, parts having the same configuration are denoted by the same reference numerals, and repeated description thereof may be omitted.

<First Embodiment>
FIG. 1A to FIG. 3C are cross-sectional views showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention in the order of steps. In the first embodiment, a case will be described in which a surface channel type N-type MOS transistor and a buried channel type P-type MOS transistor are formed on a substrate.
As shown in FIG. 1A, first, a LOCOS region 2 for element isolation is formed on a silicon substrate 1. Next, the P well region 3 is formed in the P-type MOS transistor formation portion of the silicon substrate 1 using photolithography technology and ion implantation technology. After the P well region 3 is formed, a resist pattern (not shown) is removed by ashing. Subsequently, an N well region 4 is formed in the N-type MOS transistor formation portion of the silicon substrate 1 by using a photolithography technique and an ion implantation technique. After the N well region 4 is formed, a resist pattern (not shown) is removed by ashing. The order of forming the P well region 3 and the N well region 4 may be reversed. That is, the P well region 3 may be formed after the N well region 4 is formed.

  Next, as shown in FIG. 1B, a silicon oxide film 5 is formed on the surface of the silicon substrate 1 by thermal oxidation. Then, using a photolithography technique, a resist pattern (not shown) is formed that opens above the N-type MOS transistor formation portion and covers other regions. While using this resist pattern as a mask, for example, boron ions (B +) are ion-implanted into the channel region 6 of the NMOS transistor forming portion with an acceleration energy of 60 keV using the silicon oxide film 5 as an implantation through film. Thereby, the surface channel of the N-type MOS transistor is formed. After the surface channel is formed, the resist pattern is removed by ashing.

  Subsequently, using a photolithography technique, a resist pattern (not shown) is formed that opens above the N-type MOS transistor formation portion and covers other regions. Using this resist pattern as a mask, for example, phosphorus ions (P +) are ion-implanted at an acceleration energy of 120 keV into the channel region 7 of the PMOS transistor forming portion using the silicon oxide film 5 as an implantation through film. Thereby, a buried channel of the P-type MOS transistor is formed. After forming the buried channel, the resist pattern is removed by ashing.

  As described above, since the depth of the channel region is determined by changing the strength of acceleration energy during ion implantation, the surface channel and the buried channel can be created separately. The formation order of the surface channel of the N-type MOS transistor and the buried channel of the P-type MOS transistor may be reversed. That is, after forming the buried channel of the P-type MOS transistor, the surface channel of the N-type MOS transistor may be formed.

  Next, the silicon oxide film 5 used as the implant-through film is removed by washing with, for example, a chemical solution containing hydrofluoric acid. Then, as shown in FIG. 1C, a gate oxide insulating film 8 is newly formed on the silicon substrate 1 by thermal oxidation. Next, a polysilicon film 9 ′ is formed on the gate oxide insulating film 8 by the CVD method. Then, impurities (for example, phosphorus, boron, etc.) are ion-implanted into the polysilicon film 9 ′ to make the polysilicon film 9 ′ conductive. The introduction of impurities into the polysilicon film 9 ′ may be performed in-situ, for example, instead of ion implantation.

Next, a resist pattern 10 is formed on the polysilicon film 9 ′ using a photolithography technique. Then, using this resist pattern 10 as a mask, the polysilicon film 9 'is etched. Thereby, as shown in FIG. 1D, the gate electrode 9 is formed from the polysilicon film 9 '.
After removing the resist pattern 10, as shown in FIG. 2A, a resist pattern 11 is formed by opening the upper portion of the N-type MOS transistor forming portion and covering the other region by using a photolithography technique. Then, using this resist pattern 11 as a mask, phosphorus ions (P +) ions are implanted into the N-type MOS transistor portion to form an N− diffusion layer 12. After the N− diffusion layer 12 is formed, the resist pattern 11 is removed by ashing.

  Subsequently, as shown in FIG. 2B, a resist pattern 13 is formed by opening the upper part of the P-type MOS transistor forming portion and covering the other region by using a photolithography technique. Then, using the resist pattern 13 as a mask, boron fluoride ions (BF2 +) are ion-implanted into the P-type MOS transistor portion to form a P− diffusion layer 14. After forming the P− diffusion layer 14, the resist pattern 13 is removed by ashing.

Next, a silicon nitride film is formed on the entire upper surface of the silicon substrate 1, and the silicon nitride film is etched by self-alignment. Thereby, as shown in FIG. 2C, the side spacer 15 is formed on the side wall of the gate electrode 9.
Next, as shown in FIG. 2D, a resist pattern 16 is formed by opening the upper portion of the N-type MOS transistor forming portion and covering the other region by using a photolithography technique. Then, using this resist pattern 16 as a mask, arsenic ions (As +) are ion-implanted into the N-type MOS transistor portion to form an N + diffusion layer 17. After the N + diffusion layer 17 is formed, the resist pattern 16 is removed by ashing.

  Subsequently, as shown in FIG. 3A, a resist pattern 18 is formed by opening the upper part of the P-type MOS transistor forming portion and covering the other region by using a photolithography technique. Then, using this resist pattern 18 as a mask, boron fluoride ions (BF2 +) are ion-implanted into the P-type MOS transistor portion to form a P + diffusion layer 19. After the P + diffusion layer 19 is formed, the resist pattern 18 is removed by ashing. The formation order of the N + diffusion layer 17 and the P + diffusion layer 19 may be reversed. That is, the N + diffusion layer 17 may be formed after the P + diffusion layer 19 is formed.

Through the above steps, the surface channel type N-type MOS transistor 30 is formed in the N-type MOS transistor formation portion of the silicon substrate 1, and the buried channel type P-type MOS transistor 40 is formed in the P-type MOS transistor formation portion of the silicon substrate 1. Form.
Next, as shown in FIG. 3B, a silicon nitride film 20 for slow trap suppression is deposited on the entire upper surface of the silicon substrate 1 to a thickness of 130 mm. The silicon nitride film 20 is deposited by, for example, the LPCVD method.

The present inventor has confirmed that even if the thickness of the silicon nitride film 20 deposited on the buried channel type P-type MOS transistor 40 is reduced to 70 mm, a sufficient slow trap suppression effect can be obtained. doing. Therefore, the thickness of the silicon nitride film 20 is preferably 70 mm or more.
Next, using a photolithography technique, a resist pattern 21 is formed that opens above the N-type MOS transistor formation portion and covers the P-type MOS transistor formation portion. Then, using the resist pattern 21 as a mask, only the silicon nitride film 20 deposited on the surface channel type N-type MOS transistor 30 is removed by etching. The etching of the silicon nitride film 20 may be dry etching or wet etching.

  After the silicon nitride film 20 is removed from the N-type MOS transistor 30, the resist pattern 21 is removed by ashing. Then, as shown in FIG. 3C, the silicon substrate 1 is subjected to hydrogen annealing. Thereby, in the surface channel type N-type MOS transistor 30, hydrogen can be diffused to the interface between the gate oxide insulating film 8 and the silicon substrate 1, and dangling bonds at the interface can be terminated with hydrogen. On the other hand, the buried channel type P-type MOS transistor 40 is covered with the silicon nitride film 20. Thereby, it is possible to prevent hydrogen and water from diffusing up to the P-type MOS transistor 40 under the silicon nitride film 20 during the hydrogen annealing.

The subsequent steps are the same as those in the normal CMOS process. For example, at least one interlayer insulating film (not shown) is formed on the silicon substrate 1 and at least one wiring layer is formed. Thereafter, a passivation film (not shown) is formed. Through these steps, the semiconductor device is completed.
In the first embodiment and the second embodiment described later, the silicon substrate 1 corresponds to the substrate of the present invention, the N-type MOS transistor formation portion corresponds to the first region of the present invention, and the P-type MOS transistor formation portion. Corresponds to the second region of the present invention.

(Effect of 1st Embodiment)
The first embodiment of the present invention has the following effects.
(1) The P-type MOS transistor 40 is a buried channel type, and the channel is formed inside the substrate deeper than the interface between the gate oxide insulating film 8 and the silicon substrate 1. As a result, the influence of the interface state between the gate oxide insulating film 8 and the silicon substrate 1 (for example, due to dangling bonds) can be reduced, and the 1 / f noise of the P-type MOS transistor 40 can be reduced. Can be suppressed.

(2) Further, by covering the P-type MOS transistor 40 with the silicon nitride film 20, hydrogen, water, etc. in the furnace are removed under the silicon nitride film 20 in the hydrogen annealing step shown in FIG. Diffusion to the MOS transistor 40 can be prevented. Thereby, in the P-type MOS transistor 40, hole traps can be prevented from being generated at the interface between the gate oxide insulating film 8 and the silicon substrate 1, and Vth shift (ie, slow trap) can be suppressed.

(3) The N-type MOS transistor 30 is a surface channel type and is exposed from below the silicon nitride film 20. Thereby, in the hydrogen annealing step shown in FIG. 3C, the hydrogen in the furnace can be diffused to the interface between the gate oxide insulating film 8 of the N-type MOS transistor 30 and the silicon substrate 1. Dangling bonds can be terminated with hydrogen. Thereby, the 1 / f noise of the N-type MOS transistor 30 can be suppressed low. Since carriers of the N-type MOS transistor 30 are electrons, even if hydrogen, water, or the like diffuses into the interface, there is no influence of hole traps.

(4) The silicon nitride film 20 is formed by a CVD method. As the CVD method, an APCVD (Atmospheric Pressure CVD) method or a PECVD (Plasma Enhanced CVD) method may be used, but an LPCVD method is more preferably used. Thereby, the silicon nitride film 20 which is dense and hardly permeates hydrogen, water, etc. (that is, a higher performance as a barrier film) can be formed.

Second Embodiment
In the first embodiment, the case where the surface channel type N-type MOS transistor 30 and the buried channel type P-type MOS transistor 40 are formed on the silicon substrate 1 has been described. However, in the present invention, the N-type MOS transistor may be a buried channel type instead of a surface channel type. In the second embodiment, such an aspect will be described.
4A to 4C are cross-sectional views showing a method of manufacturing a semiconductor device according to the second embodiment of the present invention in the order of steps.

As shown in FIG. 4A, first, the LOCOS region 2 is formed. Next, a P well region 3 is formed in the N-type MOS transistor formation portion of the silicon substrate 1. Subsequently, an N well region 4 is formed in the P-type MOS transistor formation portion. Each formation method of the LOCOS region 2, the P well region 3, and the N well region 4 is the same as that in the first embodiment.
Next, as shown in FIG. 4B, a silicon oxide film 5 is formed on the surface of the silicon substrate 1 by thermal oxidation.

  Then, using a photolithography technique, a resist pattern (not shown) is formed that opens above the N-type MOS transistor formation portion and covers other regions. While using this resist pattern as a mask, for example, boron ions (B +) are ion-implanted into the channel region 6 of the NMOS transistor formation portion at an acceleration energy of 120 keV using the silicon oxide film 5 as an implantation through film. Thereby, a buried channel of the N-type MOS transistor is formed.

  That is, when forming the channel region of the N-type MOS transistor, boron ions (B +) are ion-implanted deeply into the silicon substrate 1 by increasing the acceleration energy as compared with the first embodiment. It is a buried channel type. After forming the buried channel of the N-type MOS transistor, the resist pattern is removed by ashing. Further, before and after the step of forming the buried channel of the N-type MOS transistor, the buried channel of the P-type MOS transistor is formed by the same method as in the first embodiment.

  The subsequent steps up to the step of forming the silicon nitride film 20 are the same as those in the first embodiment, and are as described with reference to FIGS. 1C to 3A. As a result, as shown in FIG. 4C, a buried channel type N-type MOS transistor 50 is formed in the N-type MOS transistor formation portion of the silicon substrate 1 and a buried channel is formed in the P-type MOS transistor formation portion of the silicon substrate 1. A P-type MOS transistor 40 of the type is formed.

(Effect of 2nd Embodiment)
The second embodiment of the present invention has the same effects as the effects (1), (2), and (4) of the first embodiment. The second embodiment also has the following effects (1) and (2).
(1) Not only the P-type MOS transistor 40 but also the N-type MOS transistor 50 is a buried channel type. The channel of the N-type MOS transistor 50 is formed inside the substrate deeper than the interface between the gate oxide insulating film 8 and the silicon substrate 1. As a result, even in the N-type MOS transistor 50, it is possible to make it less susceptible to the influence of the interface level between the gate oxide insulating film 8 and the silicon substrate 1 (for example, due to dangling bonds), and 1 / f noise. Can be kept low.

(2) In the second embodiment, since the etching process (that is, partial removal) of the silicon nitride film 20 performed in FIG. 3B is not required, photolithography / etching related to the process is eliminated. / 3 steps of ashing can be deleted. Thereby, compared with 1st Embodiment, the further improvement of a through-put can be aimed at.

  Next, an experiment conducted by the inventor and the result thereof will be described as examples. When the silicon nitride film is deposited on the MOS transistor through the following experiments 1 and 2, the present inventor shows 1 / f noise degradation in the surface channel type, but 1 / f noise in the buried channel type. It was found that f noise was not deteriorated.

(Experiment 1)
FIG. 5 shows a surface channel type N-type MOS transistor covered with a silicon nitride film having a thickness of 130 mm (that is, with nitriding) and not covered with a silicon nitride film (that is, without a nitride film). FIG. 6 is a diagram comparing noise coefficients Kf. The horizontal axis in FIG. 5 indicates the cumulative distribution, and the vertical axis indicates the noise coefficient Kf.
The Kf value of “with nitride film” is measured after hydrogen annealing is performed in a state where the N-type MOS transistor is covered with the silicon nitride film. The Kf value of “no nitride film” is measured after hydrogen annealing is performed in a state where the N-type MOS transistor is not covered with the silicon nitride film.
As shown in FIG. 5, the Kf value was measured at 10 points for each of “with nitride film” and “without nitride film”. As a result, in the surface channel type N-type MOS transistor, it was confirmed that “with nitride film” deteriorates the noise coefficient Kf by about three times compared with “without nitride film”. For this reason, the surface channel type N-type MOS transistor suppresses 1 / f noise by performing hydrogen annealing without covering the top with a silicon nitride film (that is, exposed from under the silicon nitride film). I understood that I can do it.

(Experiment 2)
FIG. 6 shows a buried channel type P-type MOS transistor when it is covered with a silicon nitride film having a thickness of 130 mm (that is, with nitriding) and when it is not covered with a silicon nitride film (that is, without a nitride film). FIG. 6 is a diagram comparing noise coefficients Kf. The horizontal axis in FIG. 6 represents the cumulative distribution, and the vertical axis represents the noise coefficient Kf.
The Kf value of “with nitride film” was measured after hydrogen annealing was performed with the P-type MOS transistor covered with the silicon nitride film. The Kf value of “no nitride film” is measured after hydrogen annealing is performed in a state where the P-type MOS transistor is not covered with the silicon nitride film.
As shown in FIG. 6, the Kf value was measured at 10 points for each of “with nitride film” and “without nitride film”. As a result, in the buried channel type P-type MOS transistor, it was confirmed that the noise coefficient Kf was almost the same value for both “without nitride film” and “with nitride film”. From this, it was found that in the buried channel type P-type MOS transistor, 1 / f noise does not deteriorate even if hydrogen annealing is performed in a state where the upper portion is covered with a silicon nitride film.

(Experiment 3)
FIG. 7 shows a buried channel type P-type MOS transistor when it is covered with a silicon nitride film having a thickness of 130 mm (that is, with nitriding) and when it is not covered with a silicon nitride film (that is, without a nitride film). FIG. 6 is a diagram comparing Vth shifts. In FIG. 7, the horizontal axis indicates the stress application time, and the vertical axis indicates ΔVth (that is, the shift amount of Vth). In Experiment 3, as a stress application, a buried channel type P-type MOS transistor was placed in a high temperature environment of 125 ° C., and a gate voltage (Vg) = − 5.5 V was applied to the gate electrode in this state. As shown in FIG. 7, it was confirmed that “with nitride film” was able to suppress the Vth shift, that is, slow trap, compared with “without nitride film”.

<Others>
The present invention is not limited to the embodiments described above. Based on the knowledge of those skilled in the art, design changes and the like can be made to each embodiment, and an aspect in which such changes and the like are added is also included in the scope of the present invention.

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 LOCOS area | region 3 P well area | region 4 N well area | region 5 Silicon oxide film 6 Channel area | region 7 Channel area | region 8 Gate oxide insulating film 9 'Polysilicon film 9 Gate electrode 10, 11, 13, 16, 18, 21 Resist pattern 12 N- diffusion layer 14 P- diffusion layer 15 Side spacer 17 N + diffusion layer 19 P + diffusion layer 20 Silicon nitride film 30 (surface channel type) N-type MOS transistor 40 (buried channel type) P-type MOS transistor 50 (buried N-type MOS transistor (channel type)

Claims (2)

Forming a surface channel type N-type MOS transistor in a first region of the substrate;
Forming a buried channel P-type MOS transistor in a second region different from the first region of the substrate;
Depositing a silicon nitride film on the substrate to cover the N-type MOS transistor and the P-type MOS transistor;
Wherein the silicon nitride film is partially etched, thereby removing the silicon nitride layer from over the N-type MOS transistor, it is on the P-type MOS transistor have a, a step of leaving the silicon nitride film,
A method of manufacturing a semiconductor device , comprising subjecting the substrate to hydrogen annealing after partially etching the silicon nitride film . In the step of depositing the silicon nitride film, a manufacturing method of a semiconductor device according to claim 1, characterized by depositing the silicon nitride film by LPCVD.

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