JP6997501B2 - Semiconductor devices and methods for manufacturing semiconductor devices - Google Patents

Description

The present invention relates to a semiconductor device in which a digital circuit and an analog circuit are mixedly mounted, and a method for manufacturing the semiconductor device.

A semiconductor integrated circuit in which a digital circuit and an analog circuit are mixedly mounted on the same wafer is known. Digital circuits are required to have high speed, high density, and low power consumption. In order to realize these items, the miniaturization of MOS transistors is generally attempted. When the gate length of the MOS transistor is shortened for miniaturization, the threshold voltage is lowered due to the short channel effect, and the power consumption is sharply increased. In order to prevent this sudden increase in power consumption, the MOS transistor is formed so as to perform halo injection and increase the concentration of impurities in the vicinity of the source region end and the drain region end. As a result, in the halo-injected MOS transistor, the inverse short-channel effect that the threshold voltage increases as the gate length becomes shorter occurs.

On the other hand, in analog circuits, 1 / f noise of MOS transistors often greatly affects product performance. Halo injection, which is commonly performed in digital circuits, degrades 1 / f noise. Further, the 1 / f noise becomes smaller as the element area is larger. In a circuit where the influence of noise cannot be ignored, the channel length is intentionally increased. Therefore, in analog circuits, leakage current is less likely to be a problem than in digital circuits. Therefore, in the analog circuit, the dose amount of halo injection may be reduced, or the halo injection itself may not be performed.

Japanese Unexamined Patent Publication No. 2009-278031

J. W. Wu et al: IEEE TED 51 (2004) 1262. G. Applied Physics Letters 84 (2004) 1862. T. Tsunomura et al: 2009 Symposium on VLSI Technology Digest of Technical papers, p. 110.

Even when halo injection is not performed, the N-type MOS transistor may show an inverse short channel effect. This is a phenomenon related to interstitial silicon atoms generated by ion implantation during the formation of the source / drain region. This phenomenon is called Transient Enhanced Diffusion (TED) of impurities (particularly boron). Impurities segregate near the edges of the source / drain region due to TED. The greater the overlap of the distribution of interstitial silicon and boron caused by ion implantation during the formation of extensions or source / drain regions, the more TED of impurities occurs.

An object of the present invention is to provide a semiconductor device and a method for manufacturing a semiconductor device, which can reduce power consumption in a digital circuit and reduce the influence of noise in an analog circuit.

In order to achieve the above object, the method for manufacturing a semiconductor device according to one aspect of the present invention includes an element separation layer forming step of forming an element separation layer on a semiconductor substrate and a first conductivity in a digital circuit forming region of the semiconductor substrate. The first conductive type is applied to the first well layer forming step of injecting mold impurities to form the first well layer and the analog circuit forming region of the semiconductor substrate separated from the digital circuit forming region by the element separation layer. A second well layer forming step of injecting the impurities of the above to form a second well layer, a gate insulating film forming step of forming a gate insulating film on the surface of the semiconductor substrate, and the gate insulation of the digital circuit forming region. A gate electrode forming step of forming a first gate electrode on the surface of the film and forming a second gate electrode on the surface of the gate insulating film in the analog circuit forming region, and the first well using the first gate electrode as a mask. A step of forming a second conductive type impurity layer on the digital side by injecting a second conductive type impurity into the layer to form a second conductive type impurity layer on the digital side, and using the second gate electrode as a mask in the second well layer. The process of forming the analog side second conductive type impurity layer by injecting the second conductive type impurities to form the analog side second conductive type impurity layer, and the side surfaces of the first gate electrode and the second gate electrode. , A sidewall forming step of forming a sidewall with an insulating film, and a first source by injecting a second conductive type impurity into the digital side second conductive type impurity layer using the first gate electrode and the sidewall as a mask. Injecting into the analog-side second conductive impurity layer in the first source / drain forming step using the second gate electrode and the sidewall as a mask in the first source / drain forming step of forming the region and the first drain region. The second source / drain forming step of forming the second source region and the second drain region by injecting the second conductive type impurities shallower than the second conductive type impurities, and the first source region. It is characterized by comprising a silicide film forming step of forming a silicide film on the surfaces of the first drain region, the first gate electrode, the second source region, the second drain region, and the second gate electrode.

Further, in order to achieve the above object, the method for manufacturing a semiconductor device according to another aspect of the present invention includes an element separation layer forming step of forming an element separation layer on a semiconductor substrate and a digital circuit forming region of the semiconductor substrate. In the first well layer forming step of injecting the first conductive type impurities to form the first well layer, and in the analog circuit forming region of the semiconductor substrate separated from the digital circuit forming region by the element separation layer. A second well layer forming step of injecting a conductive type impurity to form a second well layer, and a non-doped film forming step of selectively growing a non-doped film on the surface of the semiconductor substrate in the analog circuit forming region. A gate insulating film forming step of forming a gate insulating film on the surface of the semiconductor substrate in the digital circuit forming region and the surface of the non-doped film in the analog circuit forming region, and the gate insulating film in the digital circuit forming region. A gate electrode forming step of forming a first gate electrode on the surface and forming a second gate electrode on the surface of the gate insulating film in the analog circuit forming region, and a non-doped film on the first well layer and the non-doped film. A second conductive type impurity layer forming step of injecting a second conductive type impurity with an average flight of a thickness or less to form a digital side second conductive type impurity layer and an analog side second conductive type impurity layer, and the above-mentioned A sidewall forming step of forming a sidewall with an insulating film on each side surface of the first gate electrode and the second gate electrode, and the digital using the first gate electrode, the second gate electrode and the sidewall as masks. A second conductive type impurity is injected into the side second conductive type impurity layer and the analog side second conductive type impurity layer to form a first source region and a first drain region in the digital side second conductive type impurity layer. A source / drain forming step of forming a second source region and a second drain region in the analog-side second conductive impurity layer, the first source region, the first drain region, the first gate electrode, and the above. The second source region, the second drain region, and a silicide film forming step of forming a silicide film on the surface of the second gate electrode are provided , and the source / drain forming step includes the first gate electrode and the sidewall. A first source / drain forming step of injecting the second conductive type impurity into the digital side second conductive type impurity layer as a mask to form the first source region and the first drain region, and the second gate. Electrodes and said side Using the wall as a mask, the second source is injected into the second conductive impurity layer on the analog side, which is shallower than the second conductive impurities injected in the first source / drain forming step. It is characterized by comprising a second source / drain forming step of forming a region and a second drain region .

Further, in order to achieve the above object, the semiconductor device according to one aspect of the present invention has an element separation layer formed on a semiconductor substrate and separating the semiconductor substrate into a digital circuit forming region and an analog circuit forming region, and the digital circuit forming. The first conductive type first well layer formed in the region, the first conductive type second well layer formed in the analog circuit forming region, and the first gate formed on the surface of the first well layer. An insulating film, a second gate insulating film formed on the surface of the second well layer, a first gate electrode formed on the surface of the first gate insulating film, and a surface of the second gate insulating film. The second gate electrode is formed, a sidewall formed of an insulating film on each side surface of the first gate electrode and the second gate electrode, and the first well layer sandwiching the first gate electrode. The semiconductor substrate is formed in the second well layer with the second gate electrode sandwiched between the first source region and the first drain region of the second conductive type, and is more than the first source region and the first drain region. The second source region and the second drain region of the second conductive type having a shallow depth from the surface of the above, the first source region, the first drain region, the first gate electrode, and the second source region, said. It is characterized by including a second drain region and a silicide film formed on the surface of the second gate electrode.

Further, in order to achieve the above object, the semiconductor device according to another aspect of the present invention includes an element separation layer formed on a semiconductor substrate and separating the semiconductor substrate into a digital circuit forming region and an analog circuit forming region, and the digital circuit. The first conductive type first well layer formed in the forming region, the first conductive type second well layer formed in the analog circuit forming region, and the non-doped epi formed on the surface of the second well layer. A silicon film, a first gate insulating film formed on the surface of the first well layer, a second gate insulating film formed on the surface of the non-doped episilicon film, and a surface of the first gate insulating film. A sidewall formed of an insulating film on each side surface of the first gate electrode, the second gate electrode formed on the surface of the second gate insulating film, and the first gate electrode and the second gate electrode. The first source region and the first drain region of the second conductive type formed in the first well layer across the first gate electrode, and the non-doped episilicon film and the first without the second gate electrode. The second conductive type second source region and second drain region formed in the two-well layer, the first source region, the first drain region, the first gate electrode, the second source region, and the second. It is characterized by including a drain region and a silicide film formed on the surface of the second gate electrode.

According to each aspect of the present invention, it is possible to reduce the power consumption in the digital circuit and reduce the influence of noise in the analog circuit.

It is sectional drawing which shows the schematic structure of the semiconductor device 1 by 1st Embodiment of this invention. It is a figure explaining the semiconductor device 1 by 1st Embodiment of this invention, and is the sectional view which shows the N-type MOS transistor 7 for a digital circuit and the N-type MOS transistor 9 for an analog circuit in an enlarged manner. It is a manufacturing process sectional view explaining the manufacturing process manufacturing method of the semiconductor apparatus by 1st Embodiment of this invention, and is the figure explaining the element separation layer forming process. It is a manufacturing process sectional view explaining the manufacturing process manufacturing method of the semiconductor device by 1st Embodiment of this invention, and is the figure explaining the 1st well layer formation process. It is a manufacturing process sectional view explaining the manufacturing process manufacturing method of the semiconductor device by 1st Embodiment of this invention, and is the figure explaining the 2nd well layer formation process. It is a manufacturing process sectional view explaining the manufacturing process manufacturing method of the semiconductor apparatus by 1st Embodiment of this invention, and is a figure explaining the gate insulating film forming process and the gate electrode forming process. It is a manufacturing process sectional view explaining the manufacturing process manufacturing method of the semiconductor device by 1st Embodiment of this invention, and is the figure explaining the digital side 2nd conductive type impurity layer forming process. It is a manufacturing process sectional view explaining the manufacturing process manufacturing method of the semiconductor device by 1st Embodiment of this invention, and is the figure explaining the analog side 2nd conductive type impurity layer forming process (the 1). It is a manufacturing process sectional view explaining the manufacturing process manufacturing method of the semiconductor device by 1st Embodiment of this invention, and is the figure explaining the analog side 2nd conductive type impurity layer forming process (the 2). It is a manufacturing process sectional view explaining the manufacturing process manufacturing method of the semiconductor device by 1st Embodiment of this invention, and is the figure explaining the analog side 2nd conductive type impurity layer forming process (3). It is a manufacturing process sectional view explaining the manufacturing process manufacturing method of the semiconductor device by 1st Embodiment of this invention, and is the figure explaining the sidewall forming process. It is a manufacturing process sectional view explaining the manufacturing process manufacturing method of the semiconductor device by 1st Embodiment of this invention, and is the figure explaining the 1st source drain formation process. It is a manufacturing process sectional view explaining the manufacturing process manufacturing method of the semiconductor device by 1st Embodiment of this invention, and is the figure explaining the 2nd source drain forming process (the 1). It is a manufacturing process sectional view explaining the manufacturing process manufacturing method of the semiconductor device by 1st Embodiment of this invention, and is the figure explaining the 2nd source drain forming process (the 2). It is a manufacturing process sectional view explaining the manufacturing process manufacturing method of the semiconductor device by 1st Embodiment of this invention, and is the figure explaining the 2nd source drain forming process (the 3). It is a figure explaining the semiconductor device and the manufacturing method of the semiconductor device by 1st Embodiment of this invention, and is a graph which shows the distribution in the depth direction of a channel impurity by a process simulation. It is a figure explaining the semiconductor device and the manufacturing method of the semiconductor device by 1st Embodiment of this invention, FIG. 17A is a figure which shows the arsenic distribution of a deep source drain region, and FIG. 17B is an extension. It is a figure which shows the distribution in the depth direction of the boron at the position inside 10 nm from the end to the gate side. It is a figure explaining the semiconductor device and the manufacturing method of the semiconductor device by 1st Embodiment of this invention, and is 1 / f when fluorine ion implantation is added to both a source region side and a drain region side in an extension injection process. It is a figure which shows an example of a noise coefficient ratio. It is a figure explaining the semiconductor device and the manufacturing method of the semiconductor device by 1st Embodiment of this invention, and is the figure which shows an example of the 1 / f noise coefficient ratio at the time of changing the ion implantation condition of a deep source drain. It is sectional drawing which shows the schematic structure of the semiconductor device 11 by 2nd Embodiment of this invention. It is a manufacturing process sectional view explaining the manufacturing process manufacturing method of the semiconductor apparatus by 2nd Embodiment of this invention, and is the figure explaining the element separation layer forming process. It is a manufacturing process sectional view explaining the manufacturing process manufacturing method of the semiconductor device by 2nd Embodiment of this invention, and is the figure explaining the 2nd well layer forming process. It is a manufacturing process sectional view explaining the manufacturing process manufacturing method of the semiconductor device by 2nd Embodiment of this invention, and is the figure explaining the 1st well layer formation process. It is a manufacturing process sectional view explaining the manufacturing process manufacturing method of the semiconductor device by 2nd Embodiment of this invention, and is a figure explaining the process of opening an analog circuit formation region. It is a manufacturing process sectional view explaining the manufacturing process manufacturing method of the semiconductor device by 2nd Embodiment of this invention, and is the figure explaining the non-doped film forming process. It is a manufacturing process sectional view explaining the manufacturing process manufacturing method by 2nd Embodiment of this invention, and is the figure explaining the gate insulating film forming process and the gate electrode forming process. It is a manufacturing process sectional view explaining the manufacturing process manufacturing method of the semiconductor device by 2nd Embodiment of this invention, and is the figure explaining the 2nd conductive type impurity layer forming process. It is a manufacturing process sectional view explaining the manufacturing process manufacturing method of the semiconductor device by 2nd Embodiment of this invention, and is the figure explaining the sidewall forming process. It is a manufacturing process sectional view explaining the manufacturing process manufacturing method of the semiconductor device by 2nd Embodiment of this invention, and is a figure explaining the deep source drain region forming process for forming a source drain region.

The inventor of the present application has conducted diligent experiments, and impurities (particularly boron) high concentration regions near the ends of the source region and drain region formed by TED of impurities (particularly boron) deteriorate 1 / f noise. It revealed that. However, if TED is suppressed in the same way for both the analog circuit part and the digital circuit part, the short channel effect is likely to occur in the digital circuit part, and the characteristics required for the digital circuit such as high speed, high density, and low power consumption are exhibited. It may deteriorate.

Therefore, the inventor of the present application suppresses TED of impurities (particularly boron) with respect to the MOS transistor of the analog circuit part by adding a process dedicated to the analog circuit part, and reduces the noise of the MOS transistor used in the analog circuit. Found that it is possible.

Hereinafter, the present invention will be described through embodiments, but the following embodiments do not limit the invention to which the claims are made. Also, not all combinations of features described in the embodiments are essential to the means of solving the invention.

[First Embodiment]
(Approximate configuration of semiconductor device)
First, the schematic configuration of the semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. 1 and 2. Hereinafter, in FIGS. 1 and 2 and FIGS. 3 to 15 showing the manufacturing process of the semiconductor device, the P-type MOS transistor is not shown, and only the N-type MOS transistor is shown.

As shown in FIG. 1, the semiconductor device 1 according to the present embodiment includes an N-type MOS transistor 7 for a digital circuit formed in a digital circuit forming region DA and an N-type MOS transistor for an analog circuit formed in an analog circuit forming region AA. It is equipped with a transistor 9. As described above, the semiconductor device 1 is a semiconductor device in which a digital circuit and an analog circuit are mixedly mounted.

The semiconductor device 1 includes an N-type (an example of a second conductive type) semiconductor substrate 3. The semiconductor substrate 3 is, for example, an N-type semiconductor substrate or a P-type semiconductor substrate having a deep N-well. The semiconductor device 1 includes an element separation layer 5 formed on the semiconductor substrate 3 and separating the semiconductor substrate 3 into a digital circuit forming region DA and an analog circuit forming region AA. The element separation layer 5 is formed of, for example, an STI (Shallow Tunnel Isoration) or LOCOS (Local Oxidation of Silicon) oxide film.

The semiconductor device 1 includes a P-type (an example of a first conductive type) well layer (an example of a first well layer) 71 formed in a digital circuit forming region DA and a P-type formed in an analog circuit forming region AA. A well layer (an example of a second well layer) 91 is provided. The well layers 71 and 91 are formed by, for example, ion-implanting boron (B) into the semiconductor substrate 3.

The semiconductor device 1 includes a gate insulating film (an example of a first gate insulating film) 72 formed on the surface of the well layer 71 and a gate insulating film (an example of a second gate insulating film) formed on the surface of the well layer 91. It is equipped with 92. The gate insulating films 72 and 92 are made of, for example, silicon dioxide (SiO ₂ ).

The semiconductor device 1 includes a gate electrode (an example of a first gate electrode) 73 formed on the surface of the gate insulating film 72, and a gate electrode (an example of a second gate electrode) 93 formed on the surface of the gate insulating film 92. It is equipped with. The gate electrodes 73 and 93 are made of, for example, polysilicon.

The semiconductor device 1 includes a sidewall 74 and a sidewall 94 formed of an insulating film on the side surfaces of the gate electrode 73 and the gate electrode 93, respectively. The sidewall 74 is formed on the side surface of the gate electrode 73, and the sidewall 94 is formed on the side surface of the gate electrode 93. The insulating film forming the sidewalls 74 and 94 is, for example, SiO ₂ .

The semiconductor device 1 includes an N-type source region (an example of a first source region) 75s and a drain region (an example of a first drain region) 75d formed in the well layer 71 with the gate electrode 73 interposed therebetween. The source region 75s includes an extension region 751 formed below the sidewall 74 and a deep source region 753 formed adjacent to the extension region 751. The deep source region 753 has a higher concentration of impurities (for example, arsenic (As)) than the extension region 751. The drain region 75d has an extension region 752 formed below the sidewall 74 and a deep drain region 754 formed adjacent to the extension region 752. The deep drain region 754 has a higher concentration of impurities (for example, arsenic (As)) than the extension region 752.

The semiconductor device 1 is formed in the well layer 91 with the gate electrode 93 interposed therebetween, has a depth shallower than the surface of the semiconductor substrate 3 than the source region 75s and the drain region 75d, and has an N-type source region (of the second source region). An example) 95s and a drain region (an example of a second drain region) 95d are provided. The source region 95s includes an extension region 951 formed below the sidewall 94 and a deep source region 953 formed adjacent to the extension region 951. The deep source region 953 has a higher concentration of impurities (for example, arsenic (As)) than the extension region 951. The drain region 95d has an extension region 952 formed below the sidewall 94 and a deep drain region 954 formed adjacent to the extension region 952. The deep drain region 954 has a higher concentration of impurities (for example, arsenic (As)) than the extension region 952. The relationship between the depths of the source region 95s and the drain region 95d and the depths of the source region 75s and the drain region 75d will be described later.

The semiconductor device 1 includes a silicide film 76 formed on the surfaces of the source region 75s, the drain region 75d, and the gate electrode 73, and a silicide film 96 formed on the surfaces of the source region 95s, the drain region 95d, and the gate electrode 93. ing. Although not shown, the semiconductor device 1 includes a protective layer formed on an N-type MOS transistor 7 for a digital circuit and an N-type MOS transistor 9 for an analog circuit, a source region 75s, a drain region 75d, a gate electrode 73, and a source. It includes an electrode plug embedded in a contact hole formed by removing a part of a protective layer on a region 95s, a drain region 95d, and a gate electrode 93, and a wiring connected to the electrode plug. The silicide films 76 and 96 are provided to reduce the contact resistance with the electrode plug.

To reiterate, the N-type MOS transistor 7 for a digital circuit provided in the semiconductor device 1 has a well layer 71 formed on the semiconductor substrate 3 and a gate insulating film 72 formed on a part of the well layer 71. The gate electrode 73 formed on the gate insulating film 72, the sidewall 74 formed on the side surface of the gate electrode 73, and the source region 75s and the drain region 75d formed in the well layer 71 sandwiching the gate electrode 73. It has a source region 75s, a drain region 75d, and a silicide film 76 formed on the gate electrode 73.

Further, the N-type MOS transistor 9 for an analog circuit provided in the semiconductor device 1 has a well layer 91 formed on the semiconductor substrate 3, a gate insulating film 92 formed on a part of the well layer 91, and gate insulation. The gate electrode 93 formed on the film 92, the sidewall 94 formed on the side surface of the gate electrode 93, the source region 95s and the drain region 95d formed in the well layer 91 sandwiching the gate electrode 93, and the source region. It has 95s, a drain region 95d, and a silicide film 96 formed on the gate electrode 93.

Next, FIG. 2 is used with reference to FIG. 2 regarding the relationship between the depth of the source region 95s and the drain region 95d of the N-type MOS transistor 9 for an analog circuit and the depth of the source region 75s and the drain region 75d of the N-type MOS transistor 7 for a digital circuit. I will explain.

As shown in FIG. 2, the depth of the extension region 752 of the drain region 75d provided in the N-type MOS transistor 7 for a digital circuit is D1, and the depth of the deep drain region 754 is D2. The extension region 751 of the source region 75s has the same depth as the extension region 752, and the deep source region 753 of the source region 75s has the same depth as the deep drain region 754. Further, the depth of the extension region 951 of the source region 95s provided in the N-type MOS transistor 9 for an analog circuit is D3, and the depth of the deep source region 953 is D4. The extension region 952 of the drain region 95d has the same depth as the extension region 951, and the deep source region 953 of the drain region 95d has the same depth as the deep drain region 954. Here, each depth is a distance toward the inside of the semiconductor substrate 3 with respect to the surface of the semiconductor substrate 3. Further, each depth is, for example, an average depth from the surface of the semiconductor substrate 3.

As shown in FIG. 2, the N-type MOS transistor 7 for a digital circuit and the N-type MOS transistor 9 for an analog circuit have a source region 75s and a drain region 75d so that the relationship of “D1> D3” and “D2> D4” is established. In addition, a source region 95s and a drain region 95d are formed. As described above, the semiconductor device 1 makes the depth of the source region 95s and the drain region 95d of the analog circuit N-type MOS transistor 9 shallower than the source region 75s and the drain region 75d of the N-type MOS transistor 7 for the digital circuit. Therefore, the boron concentration in the well layer 91 near the end of the source region 95s and the end of the drain region 95d is relatively low. As a result, the semiconductor device 1 can suppress TED in the N-type MOS transistor 9 for analog circuits.

(Manufacturing method of semiconductor device)
Next, a method of manufacturing a semiconductor device according to the present embodiment will be described with reference to FIGS. 1 and 2 with reference to FIGS. 3 to 15. In the present embodiment, a plurality of semiconductor devices are simultaneously formed on one semiconductor wafer. In FIGS. 3 to 15, a set of N-type MOS transistors for a digital circuit among the plurality of semiconductor devices is formed. The cross-sectional view of the manufacturing process of the N-type MOS transistor for an analog circuit is shown. Further, in FIGS. 3 to 15, in order to facilitate understanding, hatching is attached only to newly formed components (for example, a gate electrode, a resist pattern, etc.).

First, for example, a semiconductor wafer 3w made of silicon is prepared. Next, as shown in FIG. 3, after forming a plurality of element separation layers 5 on the semiconductor wafer 3w and separating the semiconductor wafers 3w into elements (an example of the element separation layer forming step), a through film for channel ion implantation is formed. (Through film forming step). Specifically, in the through film forming step, the semiconductor wafer 3w is thermally oxidized to form a silicon dioxide (SiO ₂ ) film to be a through film 31 on the entire surface of the semiconductor wafer 3w including the element separation layer 5.

Next, a channel ion implantation step (an example of the first well layer forming step) of ion-implanting into the region of the semiconductor wafer 3w, which is finally the channel region of the N-type MOS transistor 7 for a digital circuit, is carried out. Specifically, in the channel ion implantation step, a resist is applied to the entire surface of the through film 31 for patterning. As a result, as shown in FIG. 4, a resist mask RM71 that finally opens a predetermined region of the digital circuit forming region DA, which is the channel region of the N-type MOS transistor 7 for a digital circuit, is formed. Next, using the resist mask RM71 as a mask, for example, boron (B) is ion-implanted into the semiconductor wafer 3w as a first conductive type impurity. As a result, the first impurity layer 71a is formed.

Next, a channel ion implantation step (an example of a second well layer forming step) in which ions are finally implanted into the region of the semiconductor wafer 3w, which is the channel region of the N-type MOS transistor 9 for an analog circuit, and a step of co-implanting are carried out. do. Specifically, in the channel ion implantation step and the co-implantation step, a resist is applied to the entire surface of the through film 31 for patterning. As a result, as shown in FIG. 5, a resist mask RM91 that finally opens a predetermined region of the analog circuit forming region AA, which is the channel region of the N-type MOS transistor 9 for analog circuits, is formed. Next, using the resist mask RM91 as a mask, for example, boron (B) is ion-implanted into the semiconductor wafer 3w as a first conductive type impurity. In addition, fluorine (F) or carbon (C) is co-injected together with boron. As a result, the second impurity layer 91a is formed. Either the ion implantation step shown in FIG. 4 or the channel ion implantation step and the co-implantation step shown in FIG. 5 may be performed first.

Next, the first impurity layer 71a and the second impurity layer 91a are channel-activated. As a result, the well layer 71 is formed in the formation region of the first impurity layer 71a, and the well layer 91 is formed in the formation region of the second impurity layer 91a. In the present embodiment, it may be regarded as corresponding to an example of the first well layer forming step and the second well layer forming step including this channel activation step.

Next, after removing the through film 31, an insulating film 12 whose part is finally a gate insulating film is formed on the entire surface of the semiconductor wafer 3w (an example of the gate insulating film forming step).

Next, for example, a polysilicon film is formed on the entire surface of the insulating film 12. Next, a resist is applied to the entire surface of the polysilicon film and patterned to form a resist mask in which the resist remains in the formed regions of the gate electrodes 73 and 93. Next, the resist mask is removed after etching the polysilicon film using this resist mask as a mask. As a result, as shown in FIG. 6, the gate electrode 73 and the gate electrode 93 are formed on the insulating film 12 (an example of the gate electrode forming step). Then, the semiconductor wafer 3w is reoxidized.

Next, an extension implantation step (an example of a digital-side second conductive impurity layer forming step) of ion-implanting into the region of the semiconductor wafer 3w, which is finally the extension region 751 and 752 of the N-type MOS transistor 7 for a digital circuit, is carried out. do. Specifically, in the extension injection step, a resist is applied to the entire surface of the insulating film 12 including the gate electrodes 73 and 93 for patterning. As a result, as shown in FIG. 7, a resist mask RM750 that finally opens a predetermined region of the digital circuit forming region DA that becomes the source region 75s and the drain region 75d of the N-type MOS transistor 7 for a digital circuit is formed. Next, using the resist mask RM750 as a mask, for example, arsenic (As) as a second conductive type impurity is ion-implanted into the semiconductor wafer 3w to perform extension implantation. As a result, the second conductive impurity layer (an example of the digital side second conductive impurity layer) 751a and 752a are formed in the well layers 71 on both sides of the gate electrode 73.

Next, the extension injection step (an example of the analog side second conductive type impurity layer forming step) of ion-implanting into the region of the semiconductor wafer 3w which finally becomes the extension region 951,952 of the N-type MOS transistor 9 for an analog circuit and the same. Carry out the implantation process. Specifically, in the extension injection step and the co-injection step, a resist is applied to the entire surface of the insulating film 12 including the gate electrodes 73 and 93 for patterning. As a result, as shown in FIG. 8, a resist mask RM950a that finally opens a predetermined region of the analog circuit forming region AA, which is the source region 95s and the drain region 95d of the analog circuit N-type MOS transistor 9, is formed. Next, for example, phosphorus (P) as a second conductive type impurity is extended and injected into the semiconductor wafer 3w using the resist mask RM950a as a mask, and fluorine (F) or carbon (C) is co-injected together with phosphorus. As a result, the second conductive impurity layer (an example of the analog side second conductive impurity layer) 951a and 952a are formed in the well layers 91 on both sides of the gate electrode 93.

In the extension injection step and the co-injection step of forming the second conductive type impurity layers 951a and 952a, the injection amount of the second conductive type impurities is reduced as compared with the extension injection step of forming the second conductive type impurity layers 751a and 752a. .. As a result, as shown in FIG. 8, the depth from the surface of the semiconductor wafer 3w is shallower in the second conductive type impurity layers 951a and 952a than in the second conductive type impurity layers 751a and 752a.

Further, the second conductive impurity layers 951a and 952a may not be formed at the same time as described with reference to FIG. 8, but may be formed separately. That is, instead of the extension injection step described with reference to FIG. 8, both the source side extension injection step shown in FIG. 9 and the drain side extension injection step shown in FIG. 10 may be performed. In this case, for example, for the purpose of further suppressing TED only on the source side where the influence of noise is large, the injection amount and injection depth of the second conductive type impurities on each of the source region 95s side and the drain region 95d side, and both. The presence or absence of injection can be adjusted.

For example, the source side extension injection step (analog side second conductive side impurity layer forming step) in which ions are finally implanted into the region of the semiconductor wafer 3w which becomes the extension region 951 on the source region 95s side of the analog circuit N-type MOS transistor 9. Example) and the step of performing co-implantation. Specifically, in the source-side extension injection step and the co-injection step, resist is applied to the entire surface of the insulating film 12 including the gate electrodes 73 and 93 for patterning. As a result, as shown in FIG. 9, a resist mask RM951 that at least opens a predetermined region of the analog circuit forming region AA, which is finally the source region 95s of the analog circuit N-type MOS transistor 9, is formed. Next, for example, phosphorus (P) is ion-implanted and extended as a second conductive type impurity into the semiconductor wafer 3w using the resist mask RM951 as a mask, and fluorine (F) or carbon (C) is co-implanted together with phosphorus. At this time, in the source-side extension injection step, the amount of impurities injected is reduced or the impurity injection depth is made shallower as compared with the drain-side extension injection step. As a result, the second conductive impurity layer 951a is formed on one well layer 91 on both sides of the gate electrode 93.

Next, a drain side extension injection step (analog side second conductive side impurity layer forming step) in which ions are finally implanted into the region of the semiconductor wafer 3w which becomes the extension region 952 on the drain region 95d side of the analog circuit N-type MOS transistor 9. Example) and the step of performing co-implantation are carried out. In the drain-side extension injection step and the co-injection step, resist is applied to the entire surface of the insulating film 12 including the gate electrodes 73 and 93 for patterning. As a result, as shown in FIG. 10, a resist mask RM952 that finally opens a predetermined region of the analog circuit forming region AA, which is the drain region 95d of the analog circuit N-type MOS transistor 9, is formed. Next, for example, phosphorus (P) is ion-implanted and extended as a second conductive type impurity into the semiconductor wafer 3w using the resist mask RM952 as a mask, and fluorine (F) or carbon (C) is co-implanted together with phosphorus. As a result, the second conductive impurity layer 952a is formed on the other well layer 91 on both sides of the gate electrode 93. Either the source side extension injection step and the co-injection step shown in FIG. 9 and the drain side extension injection step and the co-injection step shown in FIG. 10 may be performed first. Further, the co-injection of fluorine (F) or carbon (C) may suppress the diffusion of impurities injected in the drain side extension injection step. Therefore, when the second conductive impurity layer 952a is formed, fluorine (F) or carbon (C) is not co-injected, and only when the second conductive impurity layer 951a is formed, the fluorine (F) or carbon (C) is co-injected. It is preferable to make an injection.

Next, activation annealing is performed on the semiconductor wafer 3w to activate the second conductive impurity layers 751a and 752a and the second conductive impurity layers 951a and 952a. As a result, extension regions 751 and 752 are formed in the formation regions of the second conductive impurity layers 751a and 752a, and extension regions 951 and 952 are formed in the formation regions of the second conductive impurity layers 951a and 952a. In the present embodiment, it may be regarded as corresponding to an example of the digital side second conductive type impurity layer forming step and the analog side second conductive type impurity layer forming step including this activation annealing step.

Next, as shown in FIG. 11, a step of forming sidewalls 74 and 94 with an insulating film on each side surface of the gate electrode 73 and the gate electrode 93 (sidewall forming step) is performed. The sidewalls 74 and 94 are formed by depositing an insulating film and performing anisotropic etching using a chemical vapor deposition (CVD) method.

Next, a step of injecting deep source / drain into a region including at least a region in which the deep source region 753 and the deep drain region 754 of the N-type MOS transistor 7 for a digital circuit are finally formed (the first source / drain forming step). One example) is carried out. Specifically, in the deep source / drain injection step, a resist is applied to the entire surface of the insulating film 12 including the gate electrodes 73 and 93 and the sidewalls 74 and 94 for patterning. As a result, as shown in FIG. 12, a resist mask RM75 that finally opens a predetermined region of the digital circuit forming region DA that becomes the source region 75s and the drain region 75d of the N-type MOS transistor 7 for a digital circuit is formed. Next, using the resist mask RM75 as a mask, for example, arsenic (As) is ion-implanted into the semiconductor wafer 3w as a second conductive type impurity to perform deep source-drain implantation. As a result, the second conductive deep impurity layer 753a and the second conductive deep impurity layer 754a are formed on the well layers 71 on both sides of the gate electrode 73.

Next, a deep source / drain injection step (an example of a second source / drain forming step) is performed in a region including at least a region in which the deep source region 953 and the deep drain region 954 are finally formed in the N-type MOS transistor 9 for an analog circuit. And carry out the step of performing co-injection. In the deep source / drain injection step and the co-injection step, a resist is applied to the entire surface of the insulating film 12 including the gate electrodes 73 and 93 and the sidewalls 74 and 94 for patterning. As a result, as shown in FIG. 13, a resist mask RM950b that finally opens a predetermined region of the analog circuit forming region AA, which is the source region 95s and the drain region 95d of the analog circuit N-type MOS transistor 9, is formed. Next, using the resist mask RM950b as a mask, for example, phosphorus (P) is deep source-drain injected into the semiconductor wafer 3w as a second conductive type impurity, and fluorine (F) or carbon (C) is co-injected together with phosphorus. As a result, the second conductive deep impurity layers 953a and 954a are formed in the well layers 91 on both sides of the gate electrode 93.

Further, the second conductive deep impurity layers 953a and 954a may not be formed at the same time as described with reference to FIG. 13, but may be formed separately. That is, instead of the deep source / drain injection step described with reference to FIG. 13, both the deep source injection step shown in FIG. 14 and the deep drain injection step shown in FIG. 15 may be performed. In this case, for example, for the purpose of further suppressing TED only on the source side where the influence of noise is large, the injection amount and injection depth of the second conductive type impurities on each of the source region 95s side and the drain region 95d side, and both. The presence or absence of injection can be adjusted.

For example, a deep source injection step (an example of a second source / drain forming step) and co-operation in a region including at least a region where a deep source region 953 on the source region 95s side of the N-type MOS transistor 9 for an analog circuit is finally formed. Carry out the step of injecting. In the deep source injection step and the co-injection step, a resist is applied to the entire surface of the insulating film 12 including the gate electrodes 73 and 93 and the sidewalls 74 and 94 for patterning. As a result, as shown in FIG. 14, a resist mask RM95a that at least opens a predetermined region of the analog circuit forming region AA, which is finally the deep source region 953 of the analog circuit N-type MOS transistor 9, is formed. Next, using the resist mask RM95a as a mask, for example, phosphorus (P) is injected deep source into the semiconductor wafer 3w as a second conductive type impurity, and fluorine (F) or carbon (C) is co-injected together with phosphorus. At this time, in the deep source injection step, the injection amount of impurities is reduced or the injection depth of impurities is made shallower as compared with the deep drain injection step. As a result, the second conductive deep impurity layer 953a is formed on one well layer 91 on both sides of the gate electrode 93.

Next, a deep drain injection step (an example of a second source / drain forming step) and a deep drain injection step (an example of a second source / drain forming step) are performed in a region including at least a region in which the deep drain region 954 on the drain region 95d side of the N-type MOS transistor 9 for an analog circuit is finally formed. Carry out the process of co-injection. In the deep drain injection step and the co-injection step, a resist is applied to the entire surface of the insulating film 12 including the gate electrodes 73 and 93 and the sidewalls 74 and 94 for patterning. As a result, as shown in FIG. 15, a resist mask RM95b that finally opens a predetermined region of the analog circuit forming region AA, which is the deep drain region 954 of the analog circuit N-type MOS transistor 9, is formed. Next, using the resist mask RM95b as a mask, for example, phosphorus (P) is deep-drained into the semiconductor wafer 3w as a second conductive type impurity, and fluorine (F) or carbon (C) is co-injected together with phosphorus. As a result, the second conductive deep impurity layer 954a is formed on the other well layer 91 on both sides of the gate electrode 93. Either the deep source injection step and the co-injection step shown in FIG. 14 and the deep drain injection step and the co-injection step shown in FIG. 15 may be performed first. Further, the co-injection of fluorine (F) or carbon (C) may suppress the diffusion of impurities injected in the deep drain injection step. Therefore, when the second conductive deep impurity layer 954a is formed, fluorine (F) or carbon (C) is not co-injected, and only when the second conductive deep impurity layer 953a is formed, the fluorine (F) or carbon (C) is formed. It is preferable to perform co-injection.

In the present embodiment, in the deep source drain injection step and co-injection step, deep source injection step and co-injection step, deep drain injection and co-injection step in the analog circuit forming region AA, the deep source drain in the digital circuit forming region DA The injection amount of the second conductive type impurities is smaller than that in the injection step and the co-injection step. As a result, as shown in FIG. 2, the source region 75s and the drain region 75d and the source region 95s and the drain region 95d are finally formed so that the relationship of “D1> D3” and “D2> D4” is established.

Either the deep source injection step and the co-injection step and the deep drain injection step and the co-injection step may be performed first. Further, the deep source / drain injection in the digital circuit formation region DA, the deep source / drain injection step and the co-injection step, the deep source injection step and the co-injection step, the deep drain injection step and the co-injection step in the analog circuit formation region AA. Whichever comes first.

Next, activation annealing is performed on the semiconductor wafer 3w to activate the second conductive deep impurity layers 753a and 754a and the second conductive deep impurity layers 953a and 954a. As a result, the deep source region 753 is formed in the formation region of the second conductive type deep impurity layer 753a, and the deep drain region 754 is formed in the formation region of the second conductive type deep impurity layer 754a. Further, a deep source region 953 is formed in the formation region of the second conductive type deep impurity layer 953a, and a deep drain region 954 is formed in the formation region of the second conductive type deep impurity layer 954a. As a result, as shown in FIG. 1, the well layers 71 on both sides of the gate electrode 73 have a source region 75s having an extension region 751 and a deep source region 753, and a drain region 75d having an extension region 752 and a deep drain region 754. Is formed. Further, a source region 95s having an extension region 951 and a deep source region 953 and a drain region 95d having an extension region 952 and a deep drain region 954 are formed in the well layers 91 on both sides of the gate electrode 93. In the present embodiment, it may be regarded as corresponding to an example of the first source / drain forming step and the second source / drain forming step including this activation annealing step.

Next, the insulating film 12 is etched using the gate electrode 73 and the sidewall 74 as a mask and the gate electrode 93 and the sidewall 94 as masks. As a result, as shown in FIG. 1, the gate insulating film 72 is formed below the gate electrode 73 and the sidewall 74, and the gate insulating film 92 is formed below the gate electrode 93 and the sidewall 94.

Next, a step of forming a silicide film on the surfaces of the source region 75s, the drain region 75d and the gate electrode 73, and the source region 95s, the drain region 95d and the gate electrode 93 (silicide film forming step) is carried out. In the silicide film forming step, a metal film is formed on the entire surface of the semiconductor wafer 3w including the source region 75s, the drain region 75d, the gate electrode 73, the source region 95s, the drain region 95d, and the gate electrode 93, and the metal film is annealed. I do. As a result, the surfaces of the source region 75s, the drain region 75d, the gate electrode 73, the source region 95s, the drain region 95d, and the gate electrode 93 react with the metal film to form silicide. Then, the unnecessary metal film is removed by the chemical treatment. As a result, as shown in FIG. 1, the silicide film 76 is formed on the source region 75s, the drain region 75d, and the gate electrode 73, and the silicide film 96 is formed on the source region 95s, the drain region 95d, and the gate electrode 93. ..

In this way, the N-type MOS transistor 7 for digital circuits is formed in the digital circuit formation region DA, and the N-type MOS transistor 9 for analog circuits is formed in the analog circuit formation region AA.

Although not shown, a protective layer is subsequently formed on the entire surface of the semiconductor wafer 3w including the N-type MOS transistor 7 for digital circuits and the N-type MOS transistor 9 for analog circuits. Next, a contact hole is formed in a predetermined region of the protective layer, and the contact hole is electrically connected to the source region 75s, the drain region 75d and the gate electrode 73, and the source region 95s, the drain region 95d and the gate electrode 93. Form an electrode plug. Next, the wiring connected to this electrode plug is formed. Next, the semiconductor wafer 3w is cut into pieces by cutting at a predetermined position. This completes the semiconductor device 1 including the N-type MOS transistor 7 for digital circuits and the N-type MOS transistor 9 for analog circuits.

(Effect of channel ion implantation dedicated to analog circuit formation area)
Next, the effect of channel ion implantation dedicated to the analog circuit forming region in the method for manufacturing a semiconductor device according to the present embodiment will be described with reference to FIG. The horizontal axis of the graph shown in FIG. 16 shows the depth (μm) of the semiconductor substrate 3 with respect to the interface (that is, the surface of the semiconductor substrate) between the semiconductor substrate and the gate oxide film as a reference (0 μm), and the vertical axis represents the channel. The impurity concentration (cm ^-3 ) is shown.

As described above, in the method for manufacturing a semiconductor device according to the present embodiment, in forming the well layer 91, a channel ion implantation step dedicated to the analog circuit forming region AA is provided (see FIG. 5). In the present embodiment, the analog circuit forming region AA has a smaller channel dose amount than the digital circuit forming region DA. In addition to this, in the step of forming the well layer 91 of the analog circuit forming region AA, the first conductive type impurities may be injected so that the concentration increases in the depth direction of the semiconductor substrate 3. That is, the profile of the impurity concentration of the second impurity layer 91a in the analog circuit forming region AA may have a retrograde distribution. In the second impurity layer 91a in the analog circuit forming region AA, the concentration of the first conductive type impurities on the surface of the semiconductor wafer 3w may be lower than the concentration of the first conductive type impurities inside the semiconductor wafer 3w. The smaller the amount of impurities in the channel, the less likely TED of the first conductive type impurities will occur. Further, in the present embodiment, in order to further suppress TED, fluorine and carbon are co-injected at the time of forming the second impurity layer 91a, but TED can be suppressed without this co-injection. ..

FIG. 16 shows a profile P1 connecting ◯, a profile P2 connecting □, and a profile P3 connecting Δ. Profiles P1 and P2 show the impurity concentration distribution when boron is used as the channel impurity, and profile P3 shows the impurity concentration distribution when indium is used as the channel impurity.

As shown in FIG. 16, the profile P2 has a lower impurity concentration than the profile P1. That is, the profile P2 can be seen as a profile of impurities due to channel ion implantation in the analog circuit formation region AA. Further, the profile P1 can be seen as a profile of impurities due to channel ion implantation in the digital circuit formation region DA. As described above, by lowering the impurity concentration of the second impurity layer 91a of the analog circuit forming region AA to be lower than the impurity concentration of the first impurity layer 71a of the digital circuit forming region DA, it is generated by extension ion implantation or deep source / drain ion implantation. The overlap between interstitial silicon and channel impurities can be reduced. As a result, TED in the N-type MOS transistor 9 for analog circuits can be suppressed.

Profile P3 shows a retrograde distribution. In profile P3, the impurity concentration near the interface between the gate oxide film and the semiconductor substrate (silicon substrate) is lower than that in profile P2. As a result, it is possible to reduce the overlap between the interstitial silicon generated by the extension ion implantation and the channel impurities, and it is possible to suppress TED in the analog circuit formation region AA.

(Effect of extension injection)
Next, the effect of the extension injection step in the method for manufacturing a semiconductor device according to the present embodiment will be described.
As described above, in the method for manufacturing a semiconductor device according to the present embodiment, an extension step dedicated to the analog circuit forming region AA is provided in forming the source region 95s and the drain region 95d (see FIG. 8). In this embodiment, arsenic is injected into the digital circuit forming region DA, and phosphorus is injected into the analog circuit forming region AA instead of arsenic. Further, not limited to this, the analog circuit forming region AA may have a smaller arsenic injection amount than the digital circuit forming region DA. As a result, the amount of interstitial silicon in the analog circuit forming region AA can be reduced, and the TED of boron can be suppressed. Further, in the present embodiment, in order to further suppress TED, fluorine and carbon are co-injected together with the extension injection, but TED can be suppressed even if this co-injection is not performed.

The influence of the channel boron concentration distribution on the source region side is larger than that on the drain region side on the 1 / f noise. Therefore, in the method for manufacturing a semiconductor device according to the present embodiment, as shown in FIGS. 9 and 10, extension injection conditions on the source region side and the drain region side are created separately. In particular, preventing TED on the source region side rather than the drain region side is effective in reducing 1 / f noise.

(Effect of deep source drain injection)
Next, the effect of the deep source / drain injection step in the method for manufacturing a semiconductor device according to the present embodiment will be described with reference to FIG. FIG. 17 shows an example of the impurity distribution obtained by the process simulation for a transistor having a gate length of 0.2 μm. The horizontal axis of the graphs shown in FIGS. 17 (a) and 17 (b) is the depth (μm) of the semiconductor substrate with the interface between the semiconductor substrate 3 and the gate oxide film (that is, the surface of the semiconductor substrate) as a reference (0 μm). ) Is shown. The vertical axis of the graph shown in FIG. 17A shows the concentration of arsenic, and the vertical axis of the graph shown in FIG. 17B shows the concentration of boron. The characteristic C1 connecting the ◇ marks in FIG. 17 (a) represents the distribution characteristic of arsenic when arsenic is injected shallowly, and the characteristic C2 connecting the □ marks in FIG. 17 (a) shows the case where arsenic is deeply injected. It shows the distribution characteristics of arsenic. Further, the characteristic C3 connecting the ◇ marks in FIG. 17 (b) represents the distribution characteristic of boron when arsenic is injected shallowly, and the characteristic C4 connecting the □ marks in FIG. 17 (b) indicates the deep injection of arsenic. It shows the distribution characteristics of boron when it is used.

As described above, in the method for manufacturing a semiconductor device according to the present embodiment, a deep source / drain step dedicated to the analog circuit forming region AA is provided (see FIG. 13). In this embodiment, arsenic is injected into the digital circuit forming region DA, and phosphorus is injected into the analog circuit forming region AA instead of arsenic. Further, not limited to this, the analog circuit forming region AA may have a smaller arsenic injection amount than the digital circuit forming region DA. As a result, the amount of interstitial silicon in the analog circuit forming region AA can be reduced, and the TED of boron can be suppressed. Further, in the present embodiment, in order to further suppress TED, fluorine and carbon are co-injected together with the extension injection, but TED can be suppressed even if this co-injection is not performed.

As shown in FIGS. 14 and 15, in the method for manufacturing a semiconductor device according to the present embodiment, extension injection conditions on the source region side and the drain region side are created separately as in the case of extension injection. In particular, TED on the source region side rather than the drain region side may be prevented.

FIG. 17A shows the distribution of arsenic in the deep source / drain region when the boron concentration distribution shown in FIG. 17B is obtained. FIG. 17B shows the distribution of boron in the depth direction at a position 10 nm inside from the extension end to the gate side. As shown in FIG. 17B, the gate insulating film (SiO ₂ ) is different from the case where the arsenic of the deep source drain is struck shallowly (see characteristic C3) and the arsenic of the deep source drain is struck deeply (see characteristic C4). The boron concentration near the interface between the semiconductor substrate (Si) and the semiconductor substrate (Si) is reduced. This makes it possible to reduce 1 / f noise.

(Example 1)
A semiconductor device and a method for manufacturing the semiconductor device according to the first embodiment of the present embodiment will be described with reference to FIG. FIG. 18 shows an example of the 1 / f noise coefficient ratio when fluorine ion implantation is added to both the source region side and the drain region side in the extension injection step. The “reference” in FIG. 18 shows the 1 / f noise coefficient when fluorine ion implantation is not added.

In FIG. 18, the 1 / f noise coefficient (Kf) is calculated using the following equation (1).
Kf = Svg × Cox × W × L × f ... (1)

Each symbol in the formula (1) is as follows.
Svg: Gate voltage conversion noise Cox: Gate oxide film capacity W: Gate width L: Gate length f: Frequency

In Example 1, phosphorus is used as an impurity in the extension region. The dose amount of phosphorus is 2 × 10 ¹³ cm ^-2 , and the dose amount of fluorine is 4 × 10 ¹⁴ cm ^-2 . As shown in FIG. 18, under this condition, by performing co-injection in the extension injection step, the inverse short channel effect is suppressed and the 1 / f noise coefficient ratio is reduced by about 40%.
In addition, the noise reduction rate due to TED suppression is 40% to 60% with the amount of fluorine dose in the range of 1 × 10 ¹⁴ cm ^-2 to 1 × 10 ¹⁵ cm ^-2 .

(Example 2)
A semiconductor device and a method for manufacturing the semiconductor device according to the second embodiment of the present embodiment will be described with reference to FIG. FIG. 19 shows an example of the 1 / f noise coefficient ratio when the ion implantation conditions (arsenic implantation amount and acceleration energy) of the deep source drain are changed. The “reference” in FIG. 19 shows the 1 / f noise coefficient when the ion implantation condition is “arsenic implantation amount: 5 × 10 ¹⁵ cm ^-2 , acceleration energy: 80 keV”. “Reverse short channel effect suppression” in FIG. 19 indicates the 1 / f noise coefficient when the ion implantation condition is “arsenic implantation amount: 3 × 10 ¹⁵ cm ^-2 , acceleration energy: 40 keV”.

As shown in FIG. 19, 1 / f noise is reduced by about 40% by changing the ion implantation conditions that suppress the reverse short channel effect.

As described above, according to the semiconductor device and the method for manufacturing the semiconductor device according to the present embodiment, the well concentration of the MOS transistor for an analog circuit is reduced as compared with the transistor for a digital circuit, and the source region and the drain region are reduced. The impurity concentration is reduced, or the impurity distribution in the source region and drain region is made shallow. As a result, even if the gate length of the MOS transistor for analog circuits is the same as the gate length that can reduce power consumption of MOS transistors for digital circuits, TED is suppressed and 1 / f noise is reduced. Can be done. As a result, according to the semiconductor device and the method for manufacturing the semiconductor device according to the present embodiment, it is possible to reduce the power consumption in the digital circuit and reduce the influence of noise in the analog circuit.

[Second Embodiment]
(Approximate configuration of semiconductor device)
First, the schematic configuration of the semiconductor device according to the second embodiment of the present invention will be described with reference to FIG. Hereinafter, in FIGS. 20 to 29 showing the manufacturing process of the semiconductor device, the P-type MOS transistor is not shown, and only the N-type MOS transistor is shown.

As shown in FIG. 20, the semiconductor device 11 according to the present embodiment includes an N-type MOS transistor 6 for a digital circuit formed in the digital circuit forming region DA and an N-type MOS transistor for an analog circuit formed in the analog circuit forming region AA. It includes a transistor 8. As described above, the semiconductor device 11 is a semiconductor device in which a digital circuit and an analog circuit are mixedly mounted, similarly to the semiconductor device 1 according to the first embodiment.

The semiconductor device 11 includes an N-type (an example of a second conductive type) semiconductor substrate 2. The semiconductor substrate 2 is, for example, an N-type semiconductor substrate or a P-type semiconductor substrate having a deep N-well. The semiconductor device 11 includes an element separation layer 4 formed on the semiconductor substrate 2 and separating the semiconductor substrate 2 into a digital circuit forming region DA and an analog circuit forming region AA. The device separation layer 4 is formed of, for example, an STI or LOCOS oxide film.

The semiconductor device 11 includes a P-type (an example of the first conductive type) well layer (an example of the first well layer) 61 formed in the digital circuit forming region DA and a P-type formed in the analog circuit forming region AA. A well layer (an example of a second well layer) 81 is provided. The well layers 61 and 81 are formed by, for example, ion-implanting boron (B) into the semiconductor substrate 2.

The semiconductor device 11 includes a non-doped episilicon film (an example of a non-doped film) 87 formed on the surface of the P-type well layer 81. Although the details will be described later, the non-doped episilicon film 87 is formed by epitaxially growing on the P-type well layer 81. As a result, the profile of the impurity concentration in the channel region (the region where the non-doped episilicon film 87 and the P-type well layer 81 are laminated) becomes a retrograde distribution.

The semiconductor device 11 includes a gate insulating film (an example of the first gate insulating film) 62 formed on the surface of the well layer 61 and a gate insulating film (of the second gate insulating film) formed on the surface of the non-doped episilicon film 87. One example) 82 is provided. The gate insulating films 62 and 82 are made of, for example, silicon dioxide (SiO ₂ ).

The semiconductor device 11 includes a gate electrode (an example of a first gate electrode) 63 formed on the surface of the gate insulating film 62 and a gate electrode (an example of a second gate electrode) 83 formed on the surface of the gate insulating film 82. It is equipped with. The gate electrodes 63 and 83 are made of, for example, polysilicon.

The semiconductor device 11 includes a sidewall 64 and a sidewall 84 formed of an insulating film on the respective side surfaces of the gate electrode 63 and the gate electrode 83. The sidewall 64 is formed on the side surface of the gate electrode 63, and the sidewall 84 is formed on the side surface of the gate electrode 83. The insulating film forming the sidewalls 64 and 84 is, for example, SiO ₂ .

The semiconductor device 11 includes an N-type source region (an example of a first source region) 65s and a drain region (an example of a first drain region) 65d formed in the well layer 61 with the gate electrode 63 interposed therebetween. The source region 65s includes an extension region 651 formed below the sidewall 64 and a deep source region 653 formed adjacent to the extension region 651. The deep source region 653 has a higher concentration of impurities (for example, arsenic (As)) than the extension region 651. The drain region 65d has an extension region 652 formed below the sidewall 64 and a deep drain region 654 formed adjacent to the extension region 652. The deep drain region 654 has a higher concentration of impurities (for example, arsenic (As)) than the extension region 652.

The semiconductor device 11 has an N-type source region (an example of a second source region) 85s and a drain region (an example of a second drain region) 85d formed on the non-doped episilicon film 87 and the well layer 81 with the gate electrode 83 interposed therebetween. It is equipped with. The source region 85s includes an extension region 851 formed below the sidewall 84 and a deep source region 853 formed adjacent to the extension region 851. The extension region 851 is formed on the non-doped episilicon film 87. The deep source region 853 is formed in the well layer 81. The extension region 851 is formed thinner than the non-doped episilicon film 87. The deep source region 853 has a higher concentration of impurities (for example, arsenic (As)) than the extension region 851. The drain region 85d has an extension region 852 formed below the sidewall 84 and a deep drain region 854 formed adjacent to the extension region 852. The extension region 852 is formed on the non-doped episilicon film 87. The deep drain region 854 is formed in the well layer 81. The extension region 852 is formed thinner than the non-doped episilicon film 87. The deep drain region 854 has a higher concentration of impurities (for example, arsenic (As)) than the extension region 852.

The semiconductor device 11 includes a silicide film 66 formed on the surfaces of the source region 65s, the drain region 65d, and the gate electrode 63, and a silicide film 86 formed on the surfaces of the source region 85s, the drain region 85d, and the gate electrode 83. ing. Although not shown, the semiconductor device 11 includes a protective layer formed on an N-type MOS transistor 6 for a digital circuit and an N-type MOS transistor 8 for an analog circuit, a source region 65s, a drain region 65d, a gate electrode 63, and a source. It includes an electrode plug embedded in a contact hole formed by removing a part of a protective layer on a region 85s, a drain region 85d, and a gate electrode 83, and a wiring connected to the electrode plug. The silicide films 66 and 86 are provided to reduce the contact resistance with the electrode plug.

To reiterate, the N-type MOS transistor 6 for a digital circuit provided in the semiconductor device 11 has a well layer 61 formed on the semiconductor substrate 2 and a gate insulating film 62 formed on a part of the well layer 61. The gate electrode 63 formed on the gate insulating film 62, the sidewall 64 formed on the side surface of the gate electrode 63, and the source region 65s and the drain region 65d formed in the well layer 61 sandwiching the gate electrode 63. It has a source region 65s, a drain region 65d, and a silicide film 66 formed on the gate electrode 63.

Further, the N-type MOS transistor 8 for an analog circuit provided in the semiconductor device 11 includes a well layer 81 formed on the semiconductor substrate 2, a non-doped episilicon film 87 formed on a part of the well layer 81, and non-doped. A gate insulating film 82 formed on the episilicon film 87, a gate electrode 83 formed on the gate insulating film 82, a sidewall 84 formed on the side surface of the gate electrode 83, and a non-doped across the gate electrode 83. It has a source region 85s and a drain region 85d formed over the episilicon film 87 and the well layer 91, and a silicide film 86 formed on the source region 85s, the drain region 85d, and the gate electrode 83.

By using the non-doped episilicon film 87, the impurity concentration profile of the N-type MOS transistor 8 for analog circuits can be made into a retrograde distribution. Therefore, the impurity concentration near the interface between the non-doped episilicon film 87 and the gate insulating film 82 is the vicinity of the interface between the well layer 81 and the gate insulating film 82 when the gate insulating film 82 is formed directly on the well layer 81. It is reduced below the impurity concentration. Therefore, the non-doped episilicon film 87 can reduce the overlap between the interstitial silicon and the channel impurities generated by ion implantation when forming the extension regions 851 and 852. As a result, the semiconductor device 11 can suppress TED in the analog circuit forming region AA.

(Manufacturing method of semiconductor device)
Next, a method of manufacturing a semiconductor device according to the present embodiment will be described with reference to FIGS. 20 and 29 with reference to FIGS. 20. In the present embodiment, a plurality of semiconductor devices are simultaneously formed on one semiconductor wafer. In FIGS. 21 to 29, a set of N-type MOS transistors for a digital circuit among the plurality of semiconductor devices is formed. The cross-sectional view of the manufacturing process of the N-type MOS transistor for an analog circuit is shown. Further, in FIGS. 21 to 29, in order to facilitate understanding, hatching is attached only to newly formed components (for example, a gate electrode, a resist pattern, etc.).

First, for example, a semiconductor wafer 2w made of silicon is prepared. Next, as shown in FIG. 21, after forming a plurality of element separation layers 4 on the semiconductor wafer 2w and separating the semiconductor wafer 2w into elements (an example of the element separation layer forming step), a through film for channel ion implantation is formed. (Through film forming step). Specifically, in the through film forming step, the semiconductor wafer 2w is thermally oxidized to form a silicon dioxide (SiO ₂ ) film to be the through film 21 on the entire surface of the semiconductor wafer 2w including the element separation layer 4.

Next, a channel ion implantation step (an example of a second well layer forming step) for implanting ions into the region of the semiconductor wafer 2w, which is finally the channel region of the N-type MOS transistor 8 for analog circuits, and a step of co-implanting are carried out. do. Specifically, in the channel ion implantation step and the co-implantation step, a resist is applied to the entire surface of the through film 21 for patterning. As a result, as shown in FIG. 22, a resist mask RM81 that finally opens a predetermined region of the analog circuit forming region AA, which is the channel region of the N-type MOS transistor 8 for analog circuits, is formed. Next, using the resist mask RM81 as a mask, for example, boron (B) is ion-implanted into the semiconductor wafer 2w as a first conductive type impurity. In addition, fluorine (F) or carbon (C) is co-injected together with boron. As a result, the second impurity layer 81a is formed.

Although the details will be described later, since the non-doped episilicon film 87 is grown in the analog circuit forming region AA, the impurity concentration on the silicon surface (that is, the surface of the second impurity layer 81a) of the semiconductor wafer 2w becomes low. Therefore, if the second impurity layer 81a is formed under the same conditions as the channel ion implantation conditions when the non-doped episilicon film 87 is not grown, the threshold voltage of the finally formed N-type MOS transistor 8 for analog circuits decreases. .. Therefore, in the present embodiment, in order to set the threshold voltage of the N-type MOS transistor 8 for analog circuits to a desired value, the channel ion implantation conditions when the non-doped episilicon film 87 is not grown (for example, the first embodiment in the first embodiment). (2) The channel dose amount is increased as compared with the channel ion implantation conditions in the impurity layer 91a).

Next, a channel ion implantation step (an example of the first well layer forming step) of ion-implanting into the region of the semiconductor wafer 2w, which is finally the channel region of the N-type MOS transistor 6 for a digital circuit, is carried out. Specifically, in the channel ion implantation step, a resist is applied to the entire surface of the through film 21 for patterning. As a result, as shown in FIG. 23, a resist mask RM61 that finally opens a predetermined region of the digital circuit forming region DA, which is the channel region of the N-type MOS transistor 6 for a digital circuit, is formed. Next, using the resist mask RM61 as a mask, for example, boron (B) is ion-implanted into the semiconductor wafer 2w as a first conductive type impurity. As a result, the first impurity layer 61a is formed. Either the ion implantation step shown in FIG. 23 and the channel ion implantation step and the co-implantation step shown in FIG. 22 may be performed first.

Next, after removing the resist mask RM61, the first impurity layer 61a and the second impurity layer 81a are channel-activated. As a result, the well layer 61 is formed in the formation region of the first impurity layer 71a, and the well layer 81 is formed in the formation region of the second impurity layer 81a. In the present embodiment, it may be regarded as corresponding to an example of the first well layer forming step and the second well layer forming step including this channel activation step.

Next, a resist is applied to the entire surface of the through film 21 for patterning. As a result, as shown in FIG. 24, the resist mask RM21 that opens the analog circuit forming region AA is formed. Next, the through film 21 formed in the analog circuit forming region AA using the resist mask RM21 as a mask is removed by lithography. As a result, as shown in FIG. 24, the analog circuit forming region AA is opened and the well layer 81 is exposed.

Next, a non-doped film forming step of selectively growing the non-doped episilicon film 87 on the surface of the semiconductor substrate (that is, the semiconductor wafer 2w) in the analog circuit forming region AA is performed. In the non-doped film forming step, the resist mask RM21 is first removed by dry ashing and washing with ammonium hydrogen peroxide (Ammonium hydrogen peroxide Mixture APM). High temperature APM cleaning increases the surface roughness of the silicon substrate. Therefore, in the present embodiment, APM cleaning is performed at a low temperature so as not to increase the surface roughness of the semiconductor wafer 2w. However, since the cleaning ability is lowered at a low temperature, it is preferable to perform APM cleaning in the range of 45 ° C to 55 ° C.

After APM cleaning, a chemical oxide film having a film thickness of 1 nm or less is formed on the silicon surface of the analog circuit forming region AA. Therefore, after removing the chemical oxide film formed in the analog circuit forming region AA by hydrofluoric acid cleaning, the semiconductor wafer 2w is transferred to the epitaxial growth apparatus. During the hydrofluoric acid cleaning of the semiconductor wafer 2w and the transfer to the epitaxial growth apparatus, a natural oxide film grows on the silicon surface (that is, the surface of the well layer 81) of the analog circuit forming region AA. If the non-doped episilicon film is formed in the presence of the natural oxide film, the quality of the non-doped episilicon film deteriorates, such as deterioration of the interface state density and mobility. Therefore, after the semiconductor wafer 2w is transferred to the epitaxial growth apparatus, hydrogen annealing is performed in the range of 850 ° C to 950 ° C for about 1 minute to form a natural oxide film formed on the surface of the well layer 81 of the analog circuit forming region AA. Remove. After that, as shown in FIG. 24, the non-doped episilicon film 87 is epitaxially grown on the well layer 81. The non-doped episilicon film 87 is formed only on the well layer 81, not on the through film 21 and the device separation layer 4.

Next, a gate insulating film forming step of forming the gate insulating films 62 and 82 on the surface of the semiconductor substrate (that is, the semiconductor wafer 2w) of the digital circuit forming region DA and the surface of the non-doped episilicon film 87 of the analog circuit forming region AA is performed. implement.

In the gate insulating film forming step, as shown in FIG. 26, the insulating film 42a is formed on the well layer 61, and the insulating film 42b covering the upper surface and the side surface of the non-doped episilicon film 87 is formed. A part of each of the insulating film 42a and the insulating film 42b finally becomes the gate insulating film.

Next, for example, a polysilicon film is formed on the entire surface of the semiconductor wafer 2w including the insulating films 42a and 42b. Next, a resist is applied to the entire surface of the polysilicon film to pattern it, and finally a resist mask in which the resist remains in the formed regions of the gate electrodes 63 and 83 is formed. Next, the resist mask is removed after etching the polysilicon film using this resist mask as a mask. As a result, as shown in FIG. 26, the gate electrode 63 is formed on the surface of the insulating film 42a, and the gate electrode 83 is formed on the surface of the insulating film 42b (an example of the gate electrode forming step). After that, the semiconductor wafer 2w is reoxidized.

Next, an extension implantation step of ion-implanting into the region of the semiconductor wafer 2w which finally becomes the extension region 651,652 of the N-type MOS transistor 6 for a digital circuit and the extension region 851,852 of the N-type MOS transistor 8 for an analog circuit is performed. The extension injection step to be formed (an example of the second conductive type impurity layer forming step) is carried out. Specifically, in the extension implantation step, for example, arsenic (As) is ion-implanted as a second conductive type impurity into the semiconductor wafer 2w using the gate electrodes 63 and 83 as a mask to implant the extension. In order to suppress transient accelerated diffusion, ion implantation is performed so that the average range of extension injection in the analog circuit forming region AA is equal to or less than the thickness of the non-doped episilicon film 87.

As a result, as shown in FIG. 27, in the analog circuit forming region AA, the non-doped episilicon films 87 on both sides of the gate electrode 83 are covered with the second conductive type impurity layer (an example of the analog side second conductive type impurity layer) 851a, 852a. Is formed, and in the digital circuit forming region DA, the second conductive type impurity layer (an example of the digital side second conductive type impurity layer) 651a and 652a are formed in the well layers 61 on both sides of the gate electrode 63.

As described above, in the extension injection step, the second conductive type impurities are injected into the well layer 61 using the gate electrode 63 as a mask to form the second conductive type impurity layers 651a and 652a. The forming step and the analog-side second conductive impurity layer forming step of injecting the second conductive type impurities into the non- doped episilicon film 87 using the gate electrode 83 as a mask to form the second conductive type impurity layers 851a and 852a. , Is equipped. In the present embodiment, the digital side second conductive type impurity layer forming step and the analog side second conductive type impurity layer forming step are carried out at the same time.

Next, the semiconductor wafer 2w is annealed to activate the extension impurities to activate the second conductive impurity layers 651a and 652a and the second conductive impurity layers 851a and 852a. As a result, extension regions 651 and 652 are formed in the formation regions of the second conductive impurity layers 651a and 652a, and extension regions 851 and 852 are formed in the formation regions of the second conductive impurity layers 851a and 852a (FIG. 20). reference). In the present embodiment, it may be regarded as an example of the second conductive type impurity layer forming step including this extension impurity activation annealing step.

Next, as shown in FIG. 28, a step (sidewall forming step) of forming sidewalls 64 and 84 with an insulating film on the respective side surfaces of the gate electrode 63 and the gate electrode 83 is carried out. The sidewalls 64 and 84 are formed by depositing an insulating film using a chemical vapor deposition (CVD) method and performing anisotropic etching.

Next, using the gate electrode 63, the gate electrode 83, and the sidewalls 64, 84 as masks, the second conductive type impurities are injected into the digital side second conductive type impurity layer and the analog side second conductive type impurity layer, and the digital side. A source / drain forming step is carried out in which the source region 65s and the drain region 65d are formed in the second conductive type impurity layer, and the source region 85s and the drain region 85d are formed in the analog side second conductive type impurity layer.

Specifically, in the source / drain forming step, for example, arsenic (As) is ion-implanted into the semiconductor wafer 2w as a second conductive type impurity using the gate electrode 63 and the sidewall 64 as masks, and the gate electrode 83 and the sidewall 84 are formed. As a mask, for example, arsenic (As) is ion-implanted into the semiconductor wafer 2w as a second conductive type impurity to perform deep source-drain implantation. As a result, as shown in FIG. 29, the second conductive deep impurity layer 653a and the second conductive deep impurity layer 654a are formed on the well layers 61 on both sides of the gate electrode 63, and the well layers 81 on both sides of the gate electrode 83 are formed. A second conductive type deep impurity layer 853a and a second conductive type deep impurity layer 854a are formed on the surface. The second conductive type deep impurity layer 653a and the second conductive type deep impurity layer 654a are injected into the well layer 61 deeper than the extension regions 651 and 652. Further, the second conductive type deep impurity layer 853a and the second conductive type deep impurity layer 854a are injected into the well layer 81 to a position deeper than the thickness of the non-doped episilicon film 87.

Next, activation annealing is performed on the semiconductor wafer 2w to activate the second conductive deep impurity layers 653a and 654a and the second conductive deep impurity layers 853a and 854a. As a result, the deep source region 653 is formed in the formation region of the second conductive type deep impurity layer 653a, and the deep drain region 654 is formed in the formation region of the second conductive type deep impurity layer 654a. Further, a deep source region 853 is formed in the formation region of the second conductive type deep impurity layer 853a, and a deep drain region 854 is formed in the formation region of the second conductive type deep impurity layer 854a. As a result, as shown in FIG. 20, the well layers 61 on both sides of the gate electrode 63 have a source region 65s having an extension region 651 and a deep source region 653, and a drain region 65d having an extension region 652 and a deep drain region 654. Is formed. Further, a source region 85s having an extension region 851 and a deep source region 853 and a drain region 85d having an extension region 852 and a deep drain region 854 are formed in the well layers 81 on both sides of the gate electrode 83. In the present embodiment, it may be regarded as corresponding to an example of the source / drain forming step including this activation annealing step.

Next, the insulating film 42a is etched with the gate electrode 63 and the sidewall 64 as masks, and the insulating film 42b is etched with the gate electrode 83 and the sidewall 84 as masks. The insulating film 42a and the insulating film 42b are etched at the same time. As a result, as shown in FIG. 20, the gate insulating film 62 is formed below the gate electrode 63 and the sidewall 64, and the gate insulating film 82 is formed below the gate electrode 83 and the sidewall 84.

Next, a step of forming a silicide film on the surfaces of the source region 65s, the drain region 65d, the gate electrode 63, the source region 85s, the drain region 85d, and the gate electrode 83 (silicide film forming step) is carried out. In the silicide film forming step, a metal film is formed on the entire surface of the semiconductor wafer 2w including the source region 65s, the drain region 65d, the gate electrode 63, the source region 85s, the drain region 85d, and the gate electrode 83, and the metal film is annealed. I do. As a result, the surfaces of the source region 65s, the drain region 65d, the gate electrode 63, the source region 85s, the drain region 85d, and the gate electrode 83 react with the metal film to form silicide. Then, the unnecessary metal film is removed by the chemical treatment. As a result, as shown in FIG. 20, the silicide film 66 is formed on the source region 65s, the drain region 65d, and the gate electrode 63, and the silicide film 86 is formed on the source region 85s, the drain region 85d, and the gate electrode 83. ..

In this way, the N-type MOS transistor 6 for digital circuits is formed in the digital circuit formation region DA, and the N-type MOS transistor 8 for analog circuits is formed in the analog circuit formation region AA.

Although not shown, a protective layer is subsequently formed on the entire surface of the semiconductor wafer 2w including the N-type MOS transistor 6 for digital circuits and the N-type MOS transistor 8 for analog circuits. Next, a contact hole is formed in a predetermined region of the protective layer, and the contact hole is electrically connected to the source region 65s, the drain region 65d and the gate electrode 63 and the source region 85s, the drain region 85d and the gate electrode 83. Form an electrode plug. Next, the wiring connected to this electrode plug is formed. Next, the semiconductor wafer 2w is separated by cutting at a predetermined position. This completes the semiconductor device 11 including the N-type MOS transistor 6 for digital circuits and the N-type MOS transistor 8 for analog circuits.

As described above, the method for manufacturing a semiconductor device according to the present embodiment includes a non-doped film forming step of selectively growing a non-doped episilicon film 87 as a non-doped film on the surface of the semiconductor wafer 2w in the analog circuit forming region AA. , The second conductive type impurities are injected into the well layer 61 and the non- doped episilicon film 87 with an average flight distance equal to or less than the thickness of the non-doped episilicon film 87, and the second conductive type impurity layers 651a and 652a are added to the well layer 61. It is provided with a second conductive type impurity layer forming step of forming and forming the second conductive type impurity layers 851a and 852b on the non-doped episilicon film 87.

As a result, according to the method for manufacturing a semiconductor device according to the present embodiment, impurities having a retrograde distribution in the non-doped episilicon film 87 and the well layer 81 without carrying out a complicated impurity injection step such as special impurity injection conditions. A profile of the concentration distribution can be formed. Further, according to the method for manufacturing a semiconductor device according to the present embodiment, the second conductive impurity layers 851a and 852b can be formed in the non-doped episilicon film 87 which is a non-doped region of the retrograde distribution. As described above, in the method for manufacturing a semiconductor device according to the present embodiment, the overlap between the interstitial silicon generated by ion implantation when forming the extension regions 851 and 852 and the channel impurities is reduced by a simple manufacturing process, and the analog circuit TED in the formation region AA can be suppressed.

The present invention can be modified in various ways regardless of the above embodiment.
In the first embodiment, co-injection is performed in both the extension injection step (an example of the analog side second conductive impurity layer forming step) and the deep source injection step (an example of the second source / drain forming step). , The present invention is not limited to this. The co-injection step may be performed in either an extension injection step or a deep source injection step.

In the first embodiment, in the extension injection step (an example of the process of forming the second conductive type impurity layer on the analog side), phosphorus (P) is injected as an impurity and the second conductive type is injected into the well layers 91 on both sides of the gate electrode 93. Impurity layers 951a and 952a are formed, but the present invention is not limited to this. For example, arsenic (As) may be injected instead of phosphorus (P). In this case, the arsenic distribution of the second conductive impurity layers 951a and 952a of the second conductive impurity layers 751a and 752a formed in the extension injection step (an example of the digital side second conductive impurity layer forming step). Arsenic is injected so that it is shallower than the arsenic distribution.

In the second embodiment, in the extension injection step, the digital side second conductive type impurity layer forming step and the analog side second conductive type impurity layer forming step are carried out at the same time. Not limited. For example, in the extension injection step, the digital side second conductive type impurity layer forming step and the analog side second conductive type impurity layer forming step may be carried out separately.

In this case, in the extension injection step, in order to reduce the degree of transient acceleration diffusion in the analog circuit forming region AA, a mask is added to separate the extension injection conditions of the digital circuit forming region DA and the analog circuit forming region AA. You may. That is, in the digital side second conductive type impurity layer forming step, a resist mask that covers the analog circuit forming region AA and opens the digital circuit forming region DA is formed on the entire surface of the semiconductor wafer 2w, and then the gate electrode 63 is used as a mask. , The extension injection is carried out by ion-implanting the second conductive type impurity into the well layer 61. Similarly, in the analog side second conductive type impurity layer forming step, a resist mask that covers the digital circuit forming region DA and opens the analog circuit forming region AA is formed on the entire surface of the semiconductor wafer 2w, and then the gate electrode 83 is masked. As a result, extension injection is performed by ion-injecting a second conductive type impurity into the non-doped episilicon film 87.

Further, the extension injection conditions on the source region side and the drain region side of the analog circuit forming region AA may be different. In this case, in the analog side second conductive type impurity layer forming step, at least a predetermined region of the digital circuit forming region DA and the analog circuit forming region AA which finally becomes the drain region 85d is covered, and finally becomes the source region 85s. After forming a resist mask that opens at least a predetermined region of the analog circuit forming region AA on the entire surface of the semiconductor wafer 2w, an extension injection is performed by ion-injecting a second conductive type impurity into the non-doped episilicon film 87. Similarly, in the analog side second conductive type impurity layer forming step, at least a predetermined region of the digital circuit forming region DA and the analog circuit forming region AA which finally becomes the source region 85s is covered, and finally becomes the drain region 85d. After forming a resist mask that opens at least a predetermined region of the analog circuit forming region AA on the entire surface of the semiconductor wafer 2w, an extension injection is performed by ion-injecting a second conductive type impurity into the non-doped episilicon film 87.

In the second embodiment, in the source / drain forming step, the second conductive type impurities are simultaneously injected into the digital circuit forming region DA and the analog circuit forming region AA, and the source region 65s, the drain region 65d, the source region 85s, and the source region 85s are simultaneously injected. The drain region 85d is formed, but the present invention is not limited to this.

For example, in the source / drain forming step, the first source / drain forming step of injecting a second conductive type impurity into the well layer 61 using the gate electrode 63 and the sidewall 64 as a mask to form the source region 65s and the drain region 65d. Then, using the gate electrode 83 and the sidewall 84 as masks, the second conductive type impurities are injected into the second conductive type impurity layer 81, which is shallower than the second conductive type impurities injected in the first source / drain forming step. , A second source / drain forming step of forming the source region 85s and the drain region 85d may be provided. In this case, when the second conductive type impurity is injected into the well layer 61, a resist mask that covers the analog circuit forming region AA and opens the digital circuit forming region DA is formed on the entire surface of the semiconductor wafer 2w, and then the second is formed. (Ii) Conductive impurities are injected into the well layer 61. Similarly, when the second conductive type impurity is injected into the well layer 81, a resist mask that covers the digital circuit forming region DA and opens the analog circuit forming region AA is formed on the entire surface of the semiconductor wafer 2w, and then the second is formed. (Ii) Conductive impurities are injected into the well layer 81.

Although the embodiments of the present invention have been described above, the technical scope of the present invention is not limited to the technical scope described in the above-described embodiments. It is possible to make various changes or improvements to the above-described embodiments, and it is possible to include such changes or improvements in the technical scope of the present invention from the description of the claims. it is obvious.

1,11 Semiconductor device 12, 42a, 42b Insulation film 2, 3 Semiconductor substrate 2w, 3w Semiconductor wafer 4, 5 Element separation layer 6, 7 N-type MOS transistor for digital circuit 8, 9 N-type MOS transistor for analog circuit 21, 31 Through film 61, 71, 81, 91 Well layer 61a, 71a First impurity layer 62, 72, 82, 92 Gate insulating film 63, 73, 83, 93 Gate electrode 64, 74, 84, 94 Sidewall 65d, 75d , 85d, 95d Drain region 65s, 75s, 85s, 95s Source region 66,76,86,96 EtOAc film 81a, 91a Second impurity layer 87 Non-doped episilicon film 651,652,751,752,851,852,951 952 Extension region 651a, 652a, 751a, 752a, 851a, 852a, 951a, 952a Second conductive type impurity layer 653, 753, 853, 953 Deep source region 653a, 654a, 753a, 754a, 853a, 854a, 953a, 954a No. (Ii) Conductive deep impurity layer 654,754,854,954 Deep drain region AA Analog circuit formation region DA Digital circuit formation region RM21, RM61, RM71, RM75, RM81, RM91, RM95a, RM95b, RM750, RM950a, RM950b, RM951, RM952 resist mask

Claims (11)

The element separation layer forming process for forming the element separation layer on the semiconductor substrate,
A first-well layer forming step of injecting a first conductive type impurity into a digital circuit forming region of the semiconductor substrate to form a first-well layer.
A second well layer forming step of injecting a first conductive type impurity into an analog circuit forming region of the semiconductor substrate separated from the digital circuit forming region by the element separating layer to form a second well layer.
A gate insulating film forming step of forming a gate insulating film on the surface of the semiconductor substrate,
A gate electrode forming step of forming a first gate electrode on the surface of the gate insulating film in the digital circuit forming region and forming a second gate electrode on the surface of the gate insulating film in the analog circuit forming region.
A step of forming a second conductive type impurity layer on the digital side by injecting a second conductive type impurity into the first well layer using the first gate electrode as a mask to form a second conductive type impurity layer on the digital side.
An analog-side second conductive-type impurity layer forming step of injecting a second conductive-type impurity into the second-well layer using the second gate electrode as a mask to form an analog-side second conductive-type impurity layer.
A sidewall forming step of forming a sidewall with an insulating film on each side surface of the first gate electrode and the second gate electrode.
Forming a first source / drain to form a first source region and a first drain region by injecting a second conductive type impurity into the digital side second conductive type impurity layer using the first gate electrode and the sidewall as a mask. Process and
A second conductive type impurity that is shallower than the second conductive type impurity injected in the first source / drain forming step into the analog side second conductive type impurity layer using the second gate electrode and the sidewall as a mask. A second source / drain forming step of injecting a second source / drain region to form a second source region and a second drain region.
The present invention comprises a silicide film forming step of forming a silicide film on the surfaces of the first source region, the first drain region, the first gate electrode, the second source region, the second drain region, and the second gate electrode. Manufacturing method for semiconductor devices. The method for manufacturing a semiconductor device according to claim 1, wherein in the analog side second conductive type impurity layer forming step, the injection amount of the second conductive type impurities is smaller than that in the digital side second conductive type impurity layer forming step. .. In the process of forming the second conductive type impurity layer on the digital side, arsenic is used as the second conductive type impurity layer.
The method for manufacturing a semiconductor device according to claim 1 or 2, wherein phosphorus is used as the second conductive type impurity in the process of forming the second conductive type impurity layer on the analog side. The semiconductor device according to any one of claims 1 to 3, wherein in the second source / drain forming step, the injection amount of the second conductive type impurities is smaller than that in the first source / drain forming step. Production method. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein in the second well layer forming step, fluorine or carbon is co-injected together with the first conductive type impurities. Any one of claims 1 to 5 in which fluorine or carbon is co-injected together with the second conductive type impurity in at least one of the analog side second conductive type impurity layer forming step and the second source / drain forming step. The method for manufacturing a semiconductor device according to the section. Any of claims 1 to 6 in which the first conductive type impurities are injected so that the concentration of the first conductive type impurities increases in the depth direction of the semiconductor substrate in the second well layer forming step. The method for manufacturing a semiconductor device according to item 1. The element separation layer forming process for forming the element separation layer on the semiconductor substrate,
A first-well layer forming step of injecting a first conductive type impurity into a digital circuit forming region of the semiconductor substrate to form a first-well layer.
A second well layer forming step of injecting a first conductive type impurity into an analog circuit forming region of the semiconductor substrate separated from the digital circuit forming region by the element separating layer to form a second well layer.
A non-doped film forming step of selectively growing a non-doped film on the surface of the semiconductor substrate in the analog circuit forming region,
A gate insulating film forming step of forming a gate insulating film on the surface of the semiconductor substrate in the digital circuit forming region and the surface of the non-doped film in the analog circuit forming region.
A gate electrode forming step of forming a first gate electrode on the surface of the gate insulating film in the digital circuit forming region and forming a second gate electrode on the surface of the gate insulating film in the analog circuit forming region.
A second conductive type impurity is injected into the first well layer and the non-doped film with an average flight length equal to or less than the thickness of the non-doped film, and the digital side second conductive type impurity layer and the analog side second conductive type impurity layer are injected. Second conductive type impurity layer forming step to form
A sidewall forming step of forming a sidewall with an insulating film on each side surface of the first gate electrode and the second gate electrode.
Using the first gate electrode, the second gate electrode, and the sidewall as masks, the second conductive type impurities are injected into the digital side second conductive type impurity layer and the analog side second conductive type impurity layer. A source / drain forming step of forming a first source region and a first drain region on the digital side second conductive type impurity layer and forming a second source region and a second drain region on the analog side second conductive type impurity layer. ,
The present invention comprises a silicide film forming step of forming a silicide film on the surfaces of the first source region, the first drain region, the first gate electrode, the second source region, the second drain region, and the second gate electrode. ,
The source / drain forming step is
A first source that forms the first source region and the first drain region by injecting the second conductive type impurities into the digital side second conductive type impurity layer using the first gate electrode and the sidewall as a mask.・ Drain formation process and
A second conductive type impurity that is shallower than the second conductive type impurity injected in the first source / drain forming step into the analog side second conductive type impurity layer using the second gate electrode and the sidewall as a mask. A second source / drain forming step of injecting a second source / drain region to form a second source region and a second drain region.
Equipped with
Manufacturing method of semiconductor devices. The second conductive type impurity layer forming step is
A step of forming a second conductive type impurity layer on the digital side by injecting a second conductive type impurity into the first well layer using the first gate electrode as a mask to form a second conductive type impurity layer on the digital side.
A claim comprising a step of forming an analog-side second conductive-type impurity layer by injecting a second conductive-type impurity into the non- doped film using the second gate electrode as a mask to form an analog-side second conductive-type impurity layer. 8. The method for manufacturing a semiconductor device according to 8. An element separation layer formed on a semiconductor substrate and separating the semiconductor substrate into a digital circuit forming region and an analog circuit forming region,
The first conductive type first well layer formed in the digital circuit forming region and
The first conductive type second well layer formed in the analog circuit forming region and
The first gate insulating film formed on the surface of the first well layer and
The second gate insulating film formed on the surface of the second well layer and
The first gate electrode formed on the surface of the first gate insulating film and
The second gate electrode formed on the surface of the second gate insulating film and
A sidewall formed of an insulating film on each side surface of the first gate electrode and the second gate electrode,
The second conductive type first source region and first drain region formed in the first well layer across the first gate electrode,
A second conductive type second source region formed in the second well layer with the second gate electrode interposed therebetween and having a depth shallower from the surface of the semiconductor substrate than the first source region and the first drain region. And the second drain area,
A semiconductor device including the first source region, the first drain region, the first gate electrode, and a silicide film formed on the surface of the second source region, the second drain region, and the second gate electrode. An element separation layer formed on a semiconductor substrate and separating the semiconductor substrate into a digital circuit forming region and an analog circuit forming region,
The first conductive type first well layer formed in the digital circuit forming region and
The first conductive type second well layer formed in the analog circuit forming region and
A non-doped episilicon film formed on the surface of the second well layer,
The first gate insulating film formed on the surface of the first well layer and
The second gate insulating film formed on the surface of the non-doped episilicon film and
The first gate electrode formed on the surface of the first gate insulating film and
The second gate electrode formed on the surface of the second gate insulating film and
A sidewall formed of an insulating film on each side surface of the first gate electrode and the second gate electrode,
The second conductive type first source region and first drain region formed in the first well layer across the first gate electrode,
The second conductive type second source region and second drain region formed on the non-doped episilicon film and the second well layer with the second gate electrode interposed therebetween.
A semiconductor device including the first source region, the first drain region, the first gate electrode, and a silicide film formed on the surface of the second source region, the second drain region, and the second gate electrode.

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