JP2013105838A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing a tunnel off-leak current of a tunnel transistor.SOLUTION: According to one embodiment, a semiconductor device comprises a substrate and a gate electrode formed on the substrate via a gate insulating film. The semiconductor device further comprises a source region of a first conductivity type and a drain region of a second conductivity type being a conductivity type opposite to the first conductivity type both of which are formed so as to interpose the gate electrode therebetween in the substrate. In addition, the gate electrode has a first region of the first conductivity type formed at a source region side in the gate electrode and a second region which is formed at a drain region side in the gate electrode and has a smaller value obtained by subtracting an impurity concentration of the second conductivity type from an impurity concentration of the first conductivity type in comparison with that of the first region.

Description

  Embodiments described herein relate generally to a semiconductor device and a method for manufacturing the same.

  In recent years, tunnel transistors have been intensively studied with the aim of achieving higher performance and lower power consumption than MOSFETs. In the tunnel transistor, the drain current gradient (subthreshold slope) with respect to the gate voltage in the subthreshold region can exceed the theoretical limit value of the gradient in the MOSFET, and it is expected to lead to lower power consumption than the MOSFET. Has been. On the other hand, in the tunnel transistor, reduction of the tunnel-off leakage current in the drain region is an issue, and no matter how steep the subthreshold slope is, it is difficult to reduce power consumption unless this leakage current is reduced.

F. Mayer et al., “Impact of SOI, Si1-xGexOI and GeOI substrates on CMOS compatible Tunnel FET performance”, IEDM, 163-166 (2008)

  Provided are a semiconductor device capable of reducing a tunnel-off leakage current of a tunnel transistor and a method for manufacturing the same.

  A semiconductor device according to an embodiment includes a substrate and a gate electrode formed on the substrate via a gate insulating film. The device further includes a source region of a first conductivity type formed so as to sandwich the gate electrode in the substrate, and a drain region of a second conductivity type opposite to the first conductivity type. Further, the gate electrode is formed on the first conductivity type first region formed on the source region side in the gate electrode and on the drain region side in the gate electrode, and compared with the first region. And a second region having a low value obtained by subtracting the impurity concentration of the second conductivity type from the impurity concentration of the first conductivity type.

It is sectional drawing which shows the structure of the semiconductor device of 1st Embodiment. FIG. 6 is a cross-sectional view (1/4) illustrating the method for manufacturing the semiconductor device of the first embodiment. FIG. 6 is a cross-sectional view (2/4) illustrating the method for manufacturing the semiconductor device of the first embodiment. FIG. 3D is a cross-sectional view (3/4) illustrating the method for manufacturing the semiconductor device of the first embodiment. FIG. 4D is a cross-sectional view (4/4) illustrating the method for manufacturing the semiconductor device of the first embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device of the modification of 1st Embodiment. It is sectional drawing which shows the structure of the semiconductor device of 2nd Embodiment.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 is a cross-sectional view showing the structure of the semiconductor device of the first embodiment.

  The semiconductor device in FIG. 1 includes a semiconductor substrate 101, an element isolation insulating film 102, a gate insulating film 111, a gate electrode 112, a first sidewall insulating film 113, and a second sidewall as constituent elements of a tunnel transistor. An insulating film 114, a source region 121, a drain region 122, a source extension region 123, a silicide layer 124, and an interlayer insulating film 131 are provided.

  The semiconductor substrate 101 is a silicon substrate, for example. FIG. 1 shows an X direction and a Y direction that are parallel to the main surface of the semiconductor substrate 101 and perpendicular to each other, and a Z direction that is perpendicular to the main surface of the semiconductor substrate 101. The X direction and the Y direction correspond to the gate length direction and the channel width direction of the tunnel transistor, respectively.

The element isolation insulating film 102 is formed in the semiconductor substrate 101 so as to electrically isolate the tunnel transistors from each other. The element isolation insulating film 102 is, for example, a silicon oxide film (SiO ₂ ). The element isolation insulating film 102 of this embodiment corresponds to an STI (Shallow Trench Isolation) insulating film.

  The gate electrode 112 is formed on the semiconductor substrate 101 between the element isolation insulating films 102 via the gate insulating film 111. The gate insulating film 111 is, for example, a silicon oxide film. The gate electrode 112 is a polysilicon layer, for example. Symbol Sa indicates the first side surface of the gate electrode 112 on the source region 121 side, and symbol Sb indicates the second side surface of the gate electrode 112 on the drain region 122 side.

  The first sidewall insulating film 113 is formed on the first and second side surfaces Sa and Sb of the gate electrode 112. The first sidewall insulating film 113 is, for example, a silicon oxide film. The second sidewall insulating film 114 is formed on the first and second side surfaces Sa and Sb of the gate electrode 112 with the first sidewall insulating film 113 interposed therebetween. The second sidewall insulating film 114 is, for example, a silicon oxide film.

  The source region 121 and the drain region 122 are formed in the semiconductor substrate 101 so as to sandwich the gate electrode 112. In the present embodiment, the source region 121 is a P-type region, and the drain region 122 is an N-type region. The P conductivity type is an example of the first conductivity type, and the N conductivity type is an example of the second conductivity type opposite to the first conductivity type.

  The source extension region 123 is formed adjacent to the source region 121 between the source region 121 and the drain region 122. In the present embodiment, the source extension region 123 is a P-type region. In the present embodiment, the drain extension region is not formed in order to reduce the tunnel-off leakage current in the drain region 122.

  The silicide layer 124 is formed on the gate electrode 122, the source region 121, and the drain region 122. Examples of the silicide layer 124 include a NiSi (nickel silicide) layer and a CoSi (cobalt silicide) layer.

  The interlayer insulating film 131 is formed on the semiconductor substrate 101 so as to cover the tunnel transistor. The interlayer insulating film 131 is, for example, a silicon oxide film.

  The tunnel transistor in FIG. 1 is an N-type transistor, but may be a P-type transistor. In this case, the source region 111 and the source extension region 113 are N-type regions, and the drain region 112 is a P-type region.

(1) Structure of Gate Electrode 112 Next, the structure of the gate electrode 112 will be described with reference to FIG.

  The gate electrode 112 of the present embodiment has a first region Ra formed on the source region 121 side in the gate electrode 112 and a second region Rb formed on the drain region 122 side in the gate electrode 112. Yes.

  The first region Ra is a P-type region containing P-type impurities. The first region Ra generally contains only P-type impurities in this embodiment, but if the concentration of P-type impurities is higher than the concentration of N-type impurities, it contains both P-type impurities and N-type impurities. It may be.

The second region Rb is a region containing both P-type impurities and N-type impurities. The second region Rb may be a P-type region or an N-type region. However, in the second region Rb, a value ΔC (= C _P −C _N ) obtained by subtracting the N-type impurity concentration C _N from the P-type impurity concentration C _{P is} set to be lower than that in the first region Ra. Therefore, when the values ΔC of the first and second regions Ra and Rb are represented by ΔCa and ΔCb, respectively, a relationship of ΔCa> ΔCb is established.

  Therefore, when both the first and second regions Ra and Rb are P-type regions (that is, when ΔCa and ΔCb> 0), the first region Ra becomes a P + type region and the second region Rb becomes a P− type region. .

  Further, when the first and second regions Ra and Rb are P-type and N-type regions, respectively (that is, when ΔCa> 0 and ΔCb <0), the absolute value of ΔCb may be smaller or larger than the absolute value of ΔCa. Alternatively, it may be equal to the absolute value of ΔCa.

  In this embodiment, a depletion layer is formed in the vicinity of the boundary between the first region Ra and the second region Rb by forming the first and second regions Ra and Rb as described above in the gate electrode 112. Therefore, according to the present embodiment, it is possible to weaken the gate dominance from the portion on the drain region 122 side in the gate electrode 112 to the channel, and to reduce the tunnel-off leakage current when the tunnel transistor is not driven.

  Symbols Wa and Wb shown in FIG. 1 indicate the widths of the first and second regions Ra and Rb in the gate length direction, respectively. In the present embodiment, the width Wb of the second region Rb is set to 10 nm or more. The reason is that by setting the width Wb of the second region Rb to 10 nm or more, the width of the depletion layer can be set to 10 nm or more that can prevent tunneling of electrons and holes. For the same reason, in this embodiment, the width Wa of the first region Ra is also set to 10 nm or more.

  In the present embodiment, the widths Wa and Wb are set so that Wa> Wb. Specifically, the width Wa is set to a value larger than 10 nm, and the width Wb is set to about 10 nm. The reason why the width Wa is set to be larger than 10 nm is to provide a non-depletion layer on the source region 121 side in the gate electrode 112.

  In the present embodiment, when the semiconductor device of FIG. 1 is manufactured, impurity diffusion from the first region Ra to the second region Rb or impurity diffusion from the second region Rb to the first region Ra is caused by annealing or the like. Arise. Therefore, in the vicinity of the boundary between the first region Ra and the second region Rb, the concentration of the P-type impurity and the N-type impurity changes gently.

(2) Manufacturing Method of Semiconductor Device Next, a manufacturing method of the semiconductor device according to the first embodiment will be described with reference to FIGS. 2 to 5 are cross-sectional views illustrating the method of manufacturing the semiconductor device according to the first embodiment.

  First, the semiconductor substrate 101 is prepared (FIG. 2A). Next, an element isolation insulating film 102 is formed in the semiconductor substrate 101 (FIG. 2A).

  Next, as shown in FIG. 2B, an insulating film for the gate insulating film 111 is formed on the semiconductor substrate 101 between the element isolation insulating films 102 by thermal oxidation. Next, as shown in FIG. 2B, an electrode material for the gate electrode 112 is deposited on the entire surface of the semiconductor substrate 101 by CVD (Chemical Vapor Deposition).

Next, P-type impurities are introduced into the electrode material of FIG. 2B by, for example, ion implantation. At this time, for example, B (boron) is used as the ion species. Further, the acceleration voltage and the dose amount at the time of ion implantation are set to, for example, 2 keV and 5 × 10 ¹⁵ cm ⁻² , respectively.

  Next, as shown in FIG. 3A, the electrode material is processed into the gate electrode 112 by lithography and RIE (Reactive Ion Etching). Thus, the P-conductivity type gate electrode 112 is formed on the semiconductor substrate 101 with the gate insulating film 111 interposed therebetween.

  Next, as shown in FIG. 3B, a first sidewall insulating film 113 is formed on the side surface of the gate electrode 112. The first sidewall insulating film 113 is formed, for example, by depositing an insulating film for the first sidewall insulating film 113 on the entire surface of the semiconductor substrate 101 by CVD and anisotropically etching the insulating film by RIE. The The thickness of this insulating film is, for example, 5 nm.

Next, as shown in FIG. 4A, the region where the drain region 122 is to be formed is covered with a resist film 201. Next, ion implantation for forming the source extension region 123 is performed using the resist film 201 as a mask. As a result, the source extension region 123 is formed in the semiconductor substrate 101 by subsequent annealing or the like. In this ion implantation, for example, BF ₂ is used as the ion species. In addition, the acceleration voltage and the dose amount at this time are set to, for example, 0.5 keV and 1 × 10 ¹⁵ cm ⁻² , respectively.

  In the present embodiment, the same conductivity type impurity (P-type impurity) is introduced into the gate electrode 112 and the source extension region 123. Therefore, the resist film 201 may or may not cover the gate electrode 112 as long as it covers even the region where the drain region 122 is to be formed. In the example shown in FIG. 4A, the resist film 201 covers only a part of the gate electrode 112. The resist film 201 is removed after the ion implantation shown in FIG.

  Next, as illustrated in FIG. 4B, a second sidewall insulating film 114 is formed on the side surface of the gate electrode 112 via the first sidewall insulating film 113. The second sidewall insulating film 114 is formed, for example, by depositing an insulating film for the second sidewall insulating film 114 on the entire surface of the semiconductor substrate 101 by CVD and anisotropically etching the insulating film by RIE. The The thickness of this insulating film is, for example, 30 nm.

Next, as shown in FIG. 5A, the region where the drain region 122 is to be formed is covered with a resist film 202. Next, ion implantation for forming the source region 121 is performed using the resist film 202 as a mask. As a result, the source region 121 is formed in the semiconductor substrate 101 by subsequent annealing or the like. In this ion implantation, for example, BF ₂ is used as the ion species. Further, the acceleration voltage and the dose amount at this time are set to, for example, ¹⁵ keV and 3 × 10 ¹⁵ cm ⁻² , respectively.

  In this embodiment, the same conductivity type impurity is introduced into the gate electrode 112 and the source region 121. Therefore, the resist film 202 may or may not cover the gate electrode 112 as long as it covers even the region where the drain region 122 is to be formed. In the example shown in FIG. 5A, the resist film 202 covers the entire gate electrode 112. The resist film 202 is removed after the ion implantation in FIG.

Next, as illustrated in FIG. 5B, a region corresponding to the source region 121 is covered with a resist film 203. Next, ion implantation for forming the drain region 122 is performed using the resist film 203 as a mask. As a result, the drain region 122 is formed in the semiconductor substrate 101 by subsequent annealing or the like. In this ion implantation, for example, As (arsenic) is used as the ion species. In addition, the acceleration voltage and the dose amount at this time are set to, for example, 2.5 keV and 3 × 10 ¹⁵ cm ⁻² , respectively.

  In the present embodiment, the resist film 203 is formed so as to cover only the first region Ra of the first and second regions Ra and Rb. As a result, N-type impurities are implanted only into the second region Rb of these regions Ra and Rb. Therefore, the first region Ra is a P-type region, and the second region Rb is a region containing P-type impurities and N-type impurities. In the present embodiment, the width Wb shown in FIG. 5B is set to about 10 nm, for example. The resist film 203 is removed after the ion implantation in FIG.

  Thereafter, in the present embodiment, spike annealing at, for example, 1025 ° C. is performed in the annealing step for activating the impurities. Further, the silicide layer 124 of FIG. 1 is formed in a self-aligned manner by a salicide process. Furthermore, an interlayer insulating film, contact plugs, via plugs, wiring layers, and the like are formed on the semiconductor substrate 101. Thus, the semiconductor device of FIG. 1 is manufactured.

In this embodiment, the introduction of the N-type impurity into the second region Rb is performed simultaneously with the introduction of the N-type impurity into the drain region 122. However, the introduction of the N-type impurity into the drain region 122 is performed. May be performed separately. The former has an advantage that the number of steps is small. On the other hand, the latter has an advantage that the impurity concentration in the second region Rb can be set independently of the impurity concentration in the drain region 122. In the latter case, for example, P (phosphorus) is used as the ion species for the second region Rb. Further, the acceleration voltage and the dose amount at this time are set to, for example, 5 keV and 5 × 10 ¹⁵ cm ⁻² , respectively.

(3) Modified Example of Manufacturing Method of Semiconductor Device Next, a manufacturing method of a semiconductor device according to a modified example of the first embodiment will be described with reference to FIG. FIG. 6 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a modification of the first embodiment.

  The second region Rb described above may be an i-type (intrinsic type) region instead of a P-type region or an N-type region. Thereby, similarly to the structure of FIG. 1, it is possible to weaken the gate dominance from the portion on the drain region 122 side in the gate electrode 112 to the channel, and to reduce the tunnel off leakage current when the tunnel transistor is not driven. Become.

  The semiconductor device having the i-type second region Rb can be manufactured by, for example, the processes of FIGS. 2A to 5B. However, in the process of FIG. 2B, it is not necessary to introduce P-type impurities into the electrode material. Therefore, the gate electrode 112 in FIG. 3A is an i-type electrode. Moreover, the process of FIG. 6 (a) and FIG.6 (b) is performed instead of the process of FIG.5 (b). Hereinafter, the steps of FIGS. 6A and 6B will be described.

  First, as shown in FIG. 6A, a region corresponding to the source region 121 and the entire gate electrode 112 are covered with a resist film 204. Next, ion implantation for forming the drain region 122 is performed using the resist film 204 as a mask. In this ion implantation, As (arsenic), for example, is used as an ion species. As a result, an N-type drain region 122 is formed in the semiconductor substrate 101 by subsequent annealing or the like.

  Next, as illustrated in FIG. 6B, a region corresponding to the source region 121 and the drain region 122 and a part of the gate electrode 112 are covered with a resist film 205. Specifically, only the second region Rb of the first and second regions Ra and Rb is covered with the resist film 205. Next, ion implantation into the first region Ra is performed using the resist film 205 as a mask. In this ion implantation, for example, B (boron) is used as an ion species. As a result, the P-type impurity is implanted only into the first region Ra of these regions Ra and Rb. Therefore, by the subsequent annealing or the like, the first region Ra becomes a P-type region, but the second region Rb remains an i-type region.

  In the present embodiment, the introduction of the P-type impurity into the first region Ra is performed separately from the introduction of the P-type impurity into the source region 121. The reason is that if these P-type impurities are introduced simultaneously, the source region 121 may be too much inside the region under the gate electrode 112. However, if this problem can be avoided, the introduction of the P-type impurity into the first region Ra may be performed simultaneously with the introduction of the P-type impurity into the source region 121.

(4) Effects of First Embodiment Finally, effects of the first embodiment will be described.

  As described above, the gate electrode 112 of the present embodiment is formed on the first conductivity type first region Ra formed on the source region 121 side in the gate electrode 112 and on the drain region 122 side in the gate electrode 112. The second region Rb has a lower value obtained by subtracting the second conductivity type impurity concentration from the first conductivity type impurity concentration than the first region Ra.

  Therefore, according to the present embodiment, it is possible to realize a structure in which the gate dominant force from the portion on the drain region 122 side in the gate electrode 112 to the channel gradually weakens as it approaches the drain region 122 side. As a result, the tunnel off leakage current of the tunnel transistor can be reduced.

(Second Embodiment)
FIG. 7 is a cross-sectional view showing the structure of the semiconductor device of the second embodiment.

  In FIG. 7, the semiconductor substrate 101 is replaced with an SOI (Semiconductor On Insulator) substrate 301. The SOI substrate 301 includes a semiconductor substrate 311, a buried insulating film 312 on the semiconductor substrate 311, and a semiconductor layer 313 on the buried insulating film 312. The semiconductor substrate 311, the buried insulating film 312, and the semiconductor layer 313 are, for example, a silicon substrate, a silicon oxide film, and a silicon layer, respectively.

  In FIG. 7, the element isolation insulating film 102 penetrates the buried insulating film 312, and the bottom surface of the element isolation insulating film 102 is at a position lower than the upper surface of the semiconductor substrate 301. Therefore, in this embodiment, the tunnel transistors are electrically isolated by the element isolation insulating film 102 and the buried insulating film 312. The source region 121, the drain region 122, and the source extension region 123 are formed in the semiconductor layer 313.

  According to the present embodiment, since the tunnel transistors are electrically isolated by the element isolation insulating film 102 and the buried insulating film 312, it is possible to effectively suppress punch-through compared to the first embodiment. It becomes.

  Although the first and second embodiments have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms. Moreover, various modifications can be obtained by making various omissions, substitutions, and changes to these embodiments without departing from the scope of the invention. These forms and modifications are included in the scope and gist of the invention, and these forms and modifications are included in the claims and the scope equivalent thereto.

101: Semiconductor substrate, 102: Element isolation insulating film,
111: Gate insulating film, 112: Gate electrode,
113: 1st side wall insulating film, 114: 2nd side wall insulating film,
121: source region, 122: drain region,
123: Source extension region, 124: Silicide layer,
131: interlayer insulating film, 201-205: resist film, 301: SOI substrate,
311: Semiconductor substrate, 312: Embedded insulating film, 313: Semiconductor layer

Claims (9)

A substrate,
A gate electrode formed on the substrate via a gate insulating film;
A source region of a first conductivity type formed so as to sandwich the gate electrode in the substrate, and a drain region of a second conductivity type opposite to the first conductivity type,
A source extension region of the first conductivity type formed adjacent to the source region between the source region and the drain region;
The gate electrode is
A first region of the first conductivity type formed on the source region side in the gate electrode;
A second region formed on the drain region side in the gate electrode and having a lower value obtained by subtracting the impurity concentration of the second conductivity type from the impurity concentration of the first conductivity type than the first region; And
The second region contains both the first conductivity type impurity and the second conductivity type impurity, or is an intrinsic type,
The width of the first region is longer than the width of the second region,
Semiconductor device. A substrate,
A gate electrode formed on the substrate via a gate insulating film;
A source region of a first conductivity type formed so as to sandwich the gate electrode in the substrate, and a drain region of a second conductivity type opposite to the first conductivity type,
The gate electrode is
A first region of the first conductivity type formed on the source region side in the gate electrode;
A second region formed on the drain region side in the gate electrode and having a lower value obtained by subtracting the impurity concentration of the second conductivity type from the impurity concentration of the first conductivity type than the first region;
A semiconductor device.   The semiconductor device according to claim 2, wherein the second region contains both the first conductivity type impurity and the second conductivity type impurity, or is an intrinsic type.   The semiconductor device according to claim 2, wherein a width of the first region is longer than a width of the second region.   5. The semiconductor according to claim 2, further comprising a source extension region of the first conductivity type formed adjacent to the source region between the source region and the drain region. 6. apparatus. Forming a first conductivity type gate electrode on the substrate via a gate insulating film;
Forming a source region of the first conductivity type and a drain region of a second conductivity type opposite to the first conductivity type so as to sandwich the gate electrode in the substrate;
Of the first region located on the source region side in the gate electrode and the second region located on the drain region side in the gate electrode, the impurity of the second conductivity type is introduced only in the second region. Introduce,
A method for manufacturing a semiconductor device.   The method of manufacturing a semiconductor device according to claim 6, wherein the introduction of the second conductivity type impurity into the second region is performed simultaneously with the introduction of the second conductivity type impurity into the drain region. An intrinsic gate electrode is formed on the substrate via a gate insulating film,
A source region of a first conductivity type and a drain region of a second conductivity type opposite to the first conductivity type are formed in the substrate so as to sandwich the gate electrode,
Of the first region located on the source region side in the gate electrode and the second region located on the drain region side in the gate electrode, the impurity of the first conductivity type is only in the first region. Introduce,
A method for manufacturing a semiconductor device.   9. The manufacturing of a semiconductor device according to claim 8, wherein the introduction of the first conductivity type impurity into the first region is performed separately from the introduction of the first conductivity type impurity into the source region. Method.

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