JP5434489B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device capable of reducing flicker noise and a manufacturing method thereof.

FIG. 5 shows a PMOS transistor portion in a conventional example of a CMOS semiconductor device. In this conventional example, an SiO ₂ film 12 for element isolation is formed on the surface of a Si substrate 11, and an N well 14 is formed in a formation region of a PMOS transistor 13.

A SiO ₂ film 15 as a gate oxide film is formed on the surface of the Si substrate 11 surrounded by the SiO ₂ film 12. A gate electrode 18 is formed of a polycide layer composed of an N ⁺ type polycrystalline Si film 16 and a WSi _x film 17, and the side wall for the LDD structure is formed of the SiO ₂ film 21 and the like on the gate electrode 18. Is formed.

A P ⁻⁻ region 22 for correcting the work function of the N ⁺ -type gate electrode 18 is formed under the polycrystalline Si film 16 in the N well 14, and an LDD is formed under the SiO ₂ film 21. A P ⁻ region 23 as a portion and an N ⁻ region 24 as a so-called pocket portion are formed. Further, P ⁺ regions 25 as source / drain portions are formed in portions of the N well 14 other than under the polycrystalline Si film 16 and the SiO ₂ film 21 (see, for example, Patent Document 1).

  By the way, although the MOS transistor by the dual gate process uses a surface channel type, flicker noise may be a problem in a product operating in a low frequency region. In the surface channel type dual gate structure, the electrical channel of the MOS transistor is formed on the surface of the silicon substrate for both the N-type transistor and the P-type transistor. The NMOS transistor is formed with an N-type polysilicon gate electrode, and the PMOS transistor is formed with a P-type polysilicon gate electrode.

  Flicker noise is inversely proportional to the area (L / W) of the transistor, and the flicker noise that is likely to occur at the interface between the gate insulating film and the channel layer is increased in the surface channel structure of the MOS transistor by the conventional dual gate process. Therefore, as a countermeasure against flicker noise, flicker noise has been reduced by increasing the area of the transistor. Further, the transistor has a bipolar structure to reduce flicker noise.

JP-A-8-186179 (FIG. 5)

  As described above, in the case of the conventional dual gate process, the flicker noise is reduced by increasing the area of the transistor, which increases the area of the product chip. Further, when a bipolar transistor is mixedly mounted on the COMS process, the process becomes complicated.

  An object of one embodiment of the present invention is to provide a semiconductor device that can reduce flicker noise even when the area of a transistor is reduced, and a manufacturing method thereof.

One aspect of the present invention is a method for manufacturing a semiconductor device in which a low flicker noise transistor and a PMOS transistor are formed on a semiconductor substrate,
Forming first and second P-type low concentration impurity layers in a low flicker noise transistor formation region of the semiconductor substrate;
Forming a buried channel layer buried in the semiconductor substrate and positioned between the first and second P-type low-concentration impurity layers;
Forming a gate electrode made of a polysilicon film on a surface of each of the semiconductor substrate located above the buried channel layer and the semiconductor substrate located in a PMOS transistor formation region via a gate insulating film;
Forming a P-type layer in the LDD region of the PMOS transistor by introducing P-type impurities into the semiconductor substrate using the gate electrode of the PMOS transistor as a mask;
Forming a sidewall on a sidewall of the gate electrode of each of the low flicker noise transistor and the PMOS transistor;
Introducing an N-type impurity into the gate electrode of the low flicker noise transistor while covering the PMOS transistor formation region with a first resist mask;
By introducing the P-type impurity into the semiconductor substrate using the gate electrode and the sidewall as a mask while covering the gate electrode into which the N-type impurity has been introduced with a second resist mask, the first and second A P-type layer of a source region and a drain region is formed in a P-type low-concentration impurity layer and in a region shallower than the depth of the first and second P-type low-concentration impurity layers, and the source region and drain of the PMOS transistor are formed Forming a P-type layer in the region;
A method for manufacturing a semiconductor device, comprising:

One aspect of the present invention is a method for manufacturing a semiconductor device in which a low flicker noise transistor and a PMOS transistor are formed on a semiconductor substrate,
Forming first and second LOCOS offset oxide films in a low flicker noise transistor formation region of the semiconductor substrate;
A first P-type low-concentration impurity layer is formed on the semiconductor substrate located under the first LOCOS offset oxide film, and a second is formed on the semiconductor substrate located under the second LOCOS offset oxide film. Forming a P-type low-concentration impurity layer of
Forming a buried channel layer embedded in the semiconductor substrate while being positioned between the first and second P-type low-concentration impurity layers;
Forming a gate electrode made of a polysilicon film on a surface of each of the semiconductor substrate located above the buried channel layer and the semiconductor substrate located in a PMOS transistor formation region via a gate insulating film;
Forming a P-type layer in the LDD region of the PMOS transistor by introducing P-type impurities into the semiconductor substrate using the gate electrode of the PMOS transistor as a mask;
Forming a sidewall on a sidewall of the gate electrode of each of the low flicker noise transistor and the PMOS transistor;
Introducing an N-type impurity into the gate electrode of the low flicker noise transistor while covering the PMOS transistor formation region with a first resist mask;
Covering the gate electrode into which the N-type impurity has been introduced with a second resist mask, introducing the P-type impurity into the semiconductor substrate using the gate electrode and the sidewall of each of the low flicker noise transistor and the PMOS transistor as a mask. By doing so, the first P-type low-concentration impurity layer and the first LOCOS offset oxide film are located outside, connected to the first P-type low-concentration impurity layer, and the first P-type low-concentration impurity layer. One P-type layer of a source region and a drain region is formed in a region shallower than the depth of the concentration impurity layer, and is located outside the second P-type low concentration impurity layer and the second LOCOS offset oxide film, and A source region and a drain in a region connected to the second P-type low concentration impurity layer and shallower than the depth of the second P-type low concentration impurity layer. And forming the other of the P-type layer of the band, forming a P-type layer of the source and drain regions of the PMOS transistor,
A method for manufacturing a semiconductor device, comprising:

FIGS. 4A to 4D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the first embodiment. FIGS. FIGS. 4A to 4C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a first embodiment. FIG. 3 is a plan view of the semiconductor device shown in FIG. Sectional drawing which shows the low flicker noise transistor in the semiconductor device by 2nd Embodiment. Sectional drawing which shows the conventional semiconductor device.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below.

(First embodiment)
1A to 1D and FIGS. 2A to 2C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

In the semiconductor device according to the present embodiment, a low-flicker noise PMOS transistor having an N ⁺ -type gate electrode and a DDD structure is mixedly mounted on a dual-gate transistor. A transistor and a PMOS transistor of a dual gate transistor are shown.

  First, as shown in FIG. 1A, a low flicker noise PMOS transistor formation region (hereinafter also referred to as “low flicker noise transistor formation region”) 30 and a dual gate transistor PMOS transistor formation region (hereinafter referred to as “low flicker noise transistor formation region”). Also referred to as “PMOS transistor formation region.”) A well is formed in the silicon substrate 1 located in each of the regions 31, and a LOCOS oxide film 2 as an element isolation film is formed on the surface of the silicon substrate 1.

Next, as shown in FIG. 1B, a resist pattern (not shown) is formed on the silicon substrate 1, and P-type impurity ions are implanted into the silicon substrate 1 using the resist pattern as a mask. As a result, the first and second P ⁻ type low concentration impurity layers (DDD) 3 a and 3 b which are offset are formed on the silicon substrate 1 located in the low flicker noise transistor formation region 30. Thereafter, the resist pattern is peeled off.

Next, as shown in FIG. 1C, a resist pattern (not shown) is formed on the silicon substrate 1, and ions are implanted into the silicon substrate 1 using the resist pattern as a mask. As a result, a buried channel layer 5 is formed which is buried in the silicon substrate 1 and located between the first and second P ⁻ -type low-concentration impurity layers 3a and 3b. Thereafter, the resist pattern is peeled off.

  Next, as shown in FIG. 1D, a gate oxide film to be the gate insulating film 6 is formed on the surface of the silicon substrate 1 by a thermal oxidation method. Thereafter, a polysilicon film is formed on the gate insulating film 6 and the LOCOS oxide film 2 by a CVD (Chemical Vapor Deposition) method, and this polysilicon film is processed using a photolithography method and a dry etching method. As a result, the gate electrode 7 is formed on the gate insulating film 6 in the low flicker noise transistor forming region 30, and the gate electrode 7 c is formed on the gate insulating film 6 in the PMOS transistor forming region 31.

  Next, a resist mask (not shown) covering the low flicker noise transistor formation region 30 is formed, and P-type impurity ions are implanted into the silicon substrate 1 using this resist mask and the gate electrode 7c of the PMOS transistor formation region 31 as a mask. Thus, the P-type layer 4 in the LDD region of the PMOS transistor is formed. Thereafter, the resist mask is peeled off.

  Next, for example, a silicon nitride film is formed on the entire surface including the gate electrodes 7 and 7c by the CVD method. Thereafter, the entire surface of the silicon nitride film is etched back by etch back, so that the side walls 8 are formed on the side walls of the gate electrodes 7 and 7c.

Next, as shown in FIG. 2A, a first resist pattern 9 having an opening on the central portion 7a of the gate electrode 7 is formed. The outer side 7 b of the gate electrode 7 is covered with the first resist pattern 9. Next, by implanting N-type impurity ions 7 into the gate electrode 7 using the first resist pattern 9 as a mask, N-type impurities are introduced into the central portion 7 a of the gate electrode in the low flicker noise transistor formation region 30. This ion implantation step is preferably performed simultaneously with the step of implanting N-type impurity ions into the source region and drain region of an NMOS transistor (not shown) of a dual gate transistor.
Thereafter, the first resist pattern 9 is peeled off.

Next, as shown in FIG. 2B, a second resist pattern 12a is formed which covers the central portion 7a of the gate electrode and opens the source / drain regions of the low flicker noise transistor formation region 30. Next, by implanting P-type impurity ions 11a into the silicon substrate 1 using the second resist pattern 12a, the gate electrode 7c and the sidewalls 8 as a mask, the first and second P ⁻ -type low-concentration impurity layers 3a and 3b are implanted. The source region and the drain region P-type layers 13a and 13b are formed in a region shallower than the depth of the first and second P ⁻ -type low-concentration impurity layers 3a and 3b, and the source region of the PMOS transistor formation region 31 is formed. Then, P-type layers 13c and 13d in the drain region are formed.

  Next, as shown in FIG. 2C, the second resist pattern 12a is peeled off. As a result, a low flicker noise transistor and a PMOS transistor are mixedly mounted on the same silicon substrate 1 and can be easily mounted in a dual gate process. The low flicker noise transistor is a buried channel transistor, and the PMOS transistor is a surface channel transistor.

FIG. 3 shows a plan view of the semiconductor device shown in FIG.
As shown in FIGS. 2C and 3, the semiconductor device has a silicon substrate 1 having a low flicker noise transistor formation region 30 and a PMOS transistor formation region 31.

First and second P ⁻ type low concentration impurity layers 3 a and 3 b are formed in the low flicker noise transistor forming region 30 of the silicon substrate 1. A buried channel layer 5 located between the first and second P ⁻ type low concentration impurity layers 3 a and 3 b is formed on the silicon substrate 1. The boundary between each of the first and second P ⁻ -type low-concentration impurity layers 3 a and 3 b and the buried channel layer 5 is located inside the gate electrode 7 below the region 7 a into which the N-type impurity is introduced. A gate electrode 7 is formed on the surface of the silicon substrate 1 located above the buried channel layer 5 via a gate insulating film 6. An N-type impurity is introduced into the central portion 7 a of the gate electrode 7. Yes. In the first P ⁻ -type low-concentration impurity layer 3 a, one P-type layer 13 a of the source region and the drain region is formed in the shallow region, and the second P ⁻ -type low-concentration impurity layer 3 b The other P-type layer 13b of the source region and the drain region is formed in the region where the depth at is shallow. Further, the low flicker noise transistor has an active region (field) 15a and an offset region 3 as shown in FIG.

  A PMOS transistor is formed in the PMOS transistor formation region 31 of the silicon substrate 1. This PMOS transistor has a gate electrode 7c, a gate insulating film 6, P-type layers 13c and 13d in the source and drain regions, and a P-type layer 4 in the LDD region. Further, the PMOS transistor has an active region (field) 15b and an offset region 3 as shown in FIG.

According to the first embodiment, the silicon substrate depth deep first and second to 1 P ^- -type low concentration impurity layer (DDD) 3a, 3b is formed, first and second P ^- -type A buried channel layer 5 located between the low-concentration impurity layers 3 a and 3 b is formed on the silicon substrate 1, and an N-type impurity is introduced into the central portion 7 a of the gate electrode 7. Therefore, a current path of the transistor can be formed below the gate insulating film by the buried channel layer 5, and the current path of the transistor can be further pushed down by making the gate electrode 7 N-type. As a result, flicker noise that easily occurs at the interface between the gate insulating film and the channel layer can be reduced. Specifically, when the thickness of the gate insulating film is 70 angstroms, flicker noise can be reduced to 1/20 compared with a conventional transistor. This makes it possible to reduce the area of the transistor in the area where flicker noise is reduced, thereby realizing a reduction in product size.

  Further, it is preferable that the low flicker noise transistor according to the present embodiment is used in, for example, a semiconductor circuit constituting an amplifier in which a minute current flows, and a dual gate surface channel structure transistor is used in other portions.

  Further, in the present embodiment, when a low flicker noise transistor is mixedly mounted on an existing transistor, a buried channel structure transistor and a surface channel structure transistor are changed only by an ion implantation process and a design change with respect to the existing transistor formation process. It can be easily formed in a mixed manner on the same substrate.

(Second Embodiment)
FIG. 4 is a cross-sectional view showing a low flicker noise transistor in the semiconductor device according to the second embodiment of the present invention. The low flicker noise transistor shown in FIG. 4 is a transistor formed in the low flicker noise transistor formation region 30 shown in FIGS. 4, the same parts as those in FIGS. 1 and 2 are denoted by the same reference numerals, and the description of the same parts is omitted.

  When the LOCOS oxide film 2 as the element isolation film is formed on the surface of the silicon substrate 1 by the same method as in the first embodiment, the LOCOS oxide film 2a is formed as shown in FIG. Then, a second LOCOS offset oxide film 2a is formed.

Next, in the same manner as in the first embodiment, the first P ⁻ type low concentration impurity layer 3a is formed on the silicon substrate 1 located under the first LOCOS offset oxide film 3a, and the second LOCOS is formed. A second P ⁻ type low concentration impurity layer 3b is formed on silicon substrate 1 located under offset oxide film 2a.

Next, a buried channel layer 5 buried in the silicon substrate 1 is formed while being located between the first and second P ⁻ type low concentration impurity layers. Next, a gate electrode 7 d made of a polysilicon film is formed on the surface of each of the silicon substrate located above the buried channel layer 5 and the silicon substrate 1 located in the PMOS transistor formation region via the gate insulating film 6.

  Next, P-type impurity ions are implanted into the silicon substrate 1 using the gate electrode 7c in the PMOS transistor formation region 31 as a mask, thereby forming the P-type layer 4 in the LDD region of the PMOS transistor (see FIG. 1D).

  Next, sidewalls 8 are formed on the side walls of the gate electrodes of the low flicker noise transistor formation region 30 and the PMOS transistor formation region 31. Next, N-type impurity ions are implanted into the gate electrode 7d of the low flicker noise transistor formation region 30 while covering the PMOS transistor formation region 31 with the first resist pattern 9 (see FIG. 2A).

Next, while covering the gate electrode 7d into which the N-type impurity has been introduced with the second resist pattern 12a, the gate electrode and the sidewall 8 of each of the low flicker noise transistor formation region 30 and the PMOS transistor formation region 31 are masked on the silicon substrate 1. P-type impurity ions are implanted (see FIG. 2B). Thus, the first P ^- type low concentration located outside impurity layer 3a and the first LOCOS offset oxide film 2a and the first P ^- type is linked to the low concentration impurity layer 3a and the first P ^- type One P-type layer 13a of the source region and the drain region is formed in a region shallower than the depth of the low-concentration impurity layer 3a, and outside the second P ^- type low-concentration impurity layer 3b and the second LOCOS offset oxide film 2a. position and and second P ^- -type low concentration region shallower than the depth of the impurity layer 3b of the source and drain regions other P-type layer 13b ^- -type low concentration and is linked to the impurity layer 3b of the second P At the same time, the P-type layers 13c and 13d of the source region and drain region of the PMOS transistor formation region 31 are formed.

  As described above, also in the second embodiment of the present invention, the same effect as that of the first embodiment can be obtained.

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... LOCOS oxide film, 3 ... Offset area | region, 3a, 3b ... 1st and 2nd P < ^- > type | mold low concentration impurity layer (DDD), 4 ... P-type layer of LDD area | region, 5 ... Embedded channel Layer, 6 ... gate insulating film, 7, 7c, 7d ... gate electrode, 7a ... central portion of gate electrode, 8 ... sidewall, 9 ... first resist pattern, 11a ... P-type impurity ion, 11 ... Si substrate, 12a, second resist pattern, 12 element isolation SiO ₂ film, 13a to 13d, source region and drain region P-type layer, 13 PMOS transistor, 14 N well, 15a, 15b active region (field ), 15 ... SiO ₂ film, 16 ... ^{N +} -type polycrystalline Si film, 17 ... WSi _x film, 18 ... gate electrode, 21 ... SiO ₂ film, 22 ... ^{P -} region, 23 ... P ^- region 24 ... N ^- region, 25 ... ^{P +} region, 30 ... PMOS transistor forming region of the low flicker noise, 31 ... PMOS transistor forming region of the dual gate transistor

Claims (2)

A method of manufacturing a semiconductor device in which a low flicker noise transistor and a PMOS transistor are formed on a semiconductor substrate,
Forming first and second P-type low concentration impurity layers in a low flicker noise transistor formation region of the semiconductor substrate;
Forming a buried channel layer buried in the semiconductor substrate and positioned between the first and second P-type low-concentration impurity layers;
Forming a gate electrode made of a polysilicon film on a surface of each of the semiconductor substrate located above the buried channel layer and the semiconductor substrate located in a PMOS transistor formation region via a gate insulating film;
Forming a P-type layer in the LDD region of the PMOS transistor by introducing P-type impurities into the semiconductor substrate using the gate electrode of the PMOS transistor as a mask;
Forming a sidewall on a sidewall of the gate electrode of each of the low flicker noise transistor and the PMOS transistor;
Introducing an N-type impurity into the gate electrode of the low flicker noise transistor while covering the PMOS transistor formation region with a first resist mask;
By introducing the P-type impurity into the semiconductor substrate using the gate electrode and the sidewall as a mask while covering the gate electrode into which the N-type impurity has been introduced with a second resist mask, the first and second A P-type layer of a source region and a drain region is formed in a P-type low-concentration impurity layer and in a region shallower than the depth of the first and second P-type low-concentration impurity layers, and the source region and drain of the PMOS transistor are formed Forming a P-type layer in the region;
A method for manufacturing a semiconductor device, comprising: A method of manufacturing a semiconductor device in which a low flicker noise transistor and a PMOS transistor are formed on a semiconductor substrate,
First and second LOCOS are formed in the low flicker noise transistor forming region of the semiconductor substrate.
Forming an offset oxide film;
A first P-type low-concentration impurity layer is formed on the semiconductor substrate located under the first LOCOS offset oxide film, and a second is formed on the semiconductor substrate located under the second LOCOS offset oxide film. Forming a P-type low-concentration impurity layer of
Forming a buried channel layer embedded in the semiconductor substrate while being positioned between the first and second P-type low-concentration impurity layers;
Forming a gate electrode made of a polysilicon film on a surface of each of the semiconductor substrate located above the buried channel layer and the semiconductor substrate located in a PMOS transistor formation region via a gate insulating film;
Forming a P-type layer in the LDD region of the PMOS transistor by introducing P-type impurities into the semiconductor substrate using the gate electrode of the PMOS transistor as a mask;
Forming a sidewall on a sidewall of the gate electrode of each of the low flicker noise transistor and the PMOS transistor;
Introducing an N-type impurity into the gate electrode of the low flicker noise transistor while covering the PMOS transistor formation region with a first resist mask;
Covering the gate electrode into which the N-type impurity has been introduced with a second resist mask, introducing the P-type impurity into the semiconductor substrate using the gate electrode and the sidewall of each of the low flicker noise transistor and the PMOS transistor as a mask. By doing so, the first P-type low-concentration impurity layer and the first LOCOS offset oxide film are located outside, connected to the first P-type low-concentration impurity layer, and the first P-type low-concentration impurity layer. One P-type layer of a source region and a drain region is formed in a region shallower than the depth of the concentration impurity layer, and is located outside the second P-type low concentration impurity layer and the second LOCOS offset oxide film, and A source region and a drain in a region connected to the second P-type low concentration impurity layer and shallower than the depth of the second P-type low concentration impurity layer. And forming the other of the P-type layer of the band, forming a P-type layer of the source and drain regions of the PMOS transistor,
A method for manufacturing a semiconductor device, comprising:

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