JPH09205151A - Manufacture of complementary semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a complementary semiconductor device excellent in current driving capability as a whole though a transistor of one conductivity type is of so-called pocket structure. SOLUTION: A SiN film 43 is formed only in a n-MOS transistor formation region 32, and a side wall spacer is formed using a BSG film 52. Then the workpiece is subjected to annealing. In a p-MOS transistor formation region 33, boron is diffused from the BSG film 52 into a Si substrate 31, and increase in sheet resistance of a p<-> -region 47 due to compensation by As in a n-region 51, is thereby prevented. In the n-MOS transistor formation region 32, the diffusion of boron is prevented by the SiN film 43, and the sheet resistance of a n<-> -region 45 is not increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a complementary semiconductor device in which both first and second conductivity type channel transistors have an LDD structure and second conductivity type channel transistors have a so-called pocket structure.

[0002]

2. Description of the Related Art Since the size of transistors has been reduced along with the miniaturization of semiconductor devices, particularly in a buried channel type PMOS transistor, punch-through between source / drain is likely to occur due to variations in gate length. ing. Therefore, an N-type so-called pocket region is formed at a deep position in the channel region to suppress the extension of the depletion layer from the drain.

FIG. 3 shows a conventional example of a method for manufacturing a PMOS transistor having the above-mentioned pocket structure among CMOS transistors. In this conventional example,
As shown in FIG. 3 (a), the SiO ₂ film 12, polycide layer 13 and the SiO ₂ film 14 for offset as the gate oxide film are sequentially formed on the Si substrate 11, SiO ₂ film 14
Then, the polycide layer 13 is processed into a gate electrode pattern.

After that, using the SiO ₂ film 14 as a mask, BF ₂ is 1 × 1 from the direction close to the normal to the Si substrate 11.
Ions are implanted into the Si substrate 11 at a dose of 0 ¹³ cm ⁻² to form a P ⁻ region 15 as an LDD region. Further, using the SiO ₂ film 14 and the like as a mask, 1 × 10 × 10 × 16 of As16 is applied from a direction of about 45 ° with respect to the normal line of the Si substrate 11.
Diagonal rotary ion implantation is performed on the Si substrate 11 at a dose of ¹³ cm ⁻² to form an N region 17 as a pocket region.

Next, as shown in FIG. 3B, sidewall spacers made of the SiO ₂ film 21 are formed on the polycide layer 13 and the like, and the SiO ₂ film 14 and the SiO ₂ film 21 are used as masks to form Si. 1 × 1 BF ₂ from the direction close to the normal line of the substrate 11.
Ions are implanted into the Si substrate 11 at a dose of 0 ¹⁵ cm ⁻² to form P ⁺ regions 22 as source / drain regions.

[0006]

However, the P ⁻ region 15 which is the LDD region and the N region 17 which is the pocket region have opposite conductivity types and the impurity concentrations are almost equal to each other. Therefore, in the overlapping region 23 with the N region 17 in the P ⁻ region 15 which is not covered with the P ⁺ region 22, B of the P ⁻ region 15 is compensated by As of the N region 17, and the P ⁻ region 15 is compensated. Sheet resistance increases.

When the sheet resistance of the P ⁻ region 15 which is the LDD region increases, it becomes difficult for current to flow between the source and the drain. Therefore, the CM manufactured by the conventional example shown in FIG.
In the PMOS transistor of the OS transistor, punch-through is unlikely to occur between the source / drain due to the pocket structure, and the reliability is high, but the current driving capability is low.

[0008]

According to a first aspect of the present invention, there is provided a method of manufacturing a complementary semiconductor device, wherein a relatively low concentration first conductivity type impurity region contacting a channel region of a first conductivity type channel transistor is formed on a semiconductor substrate. And a step of forming a relatively low concentration second conductivity type impurity region in contact with the channel region of the second conductivity type channel transistor in the semiconductor substrate, and the relatively low concentration second conductivity type impurity region. Forming a first conductivity type impurity region that is deeper and protruding toward the channel region side in the semiconductor substrate, and forming an impurity diffusion prevention film only in the formation region of the first conductivity type channel transistor, After forming the impurity diffusion barrier layer, sidewall spacers containing impurities of the second conductivity type are formed on the gate electrodes of the first and second conductivity type channel transistors. A step, first the relatively high concentration into the semiconductor substrate opposite the channel region of the sidewall spacer in said first conductivity type channel transistor
Forming a conductivity type impurity region, and forming a relatively high concentration second conductivity type impurity region in the semiconductor substrate on the side of the sidewall spacer of the second conductivity type channel transistor opposite to the channel region. And the second
Diffusing the second conductivity type impurity contained in the sidewall spacer of the conductivity type channel transistor into the semiconductor substrate.

The method for manufacturing a complementary semiconductor device according to a second aspect is characterized in that the second conductivity type channel transistor is a PMOS transistor and the side wall spacer is formed of a BSG film.

In the method of manufacturing the complementary semiconductor device according to the present invention, the first and second conductivity type channel transistors having the LDD structure are manufactured, and the second conductivity type channel transistor has a so-called pocket structure. A side wall spacer containing two conductivity type impurities is formed in the gate electrode, and the second conductivity type impurity contained in this side wall spacer is diffused into the semiconductor substrate in the formation region of the second conductivity type channel transistor.

Therefore, the impurity concentration of the LDD region under the sidewall spacer of the second conductivity type channel transistor is increased, and the second conductivity type impurity of the LDD region is formed despite the pocket structure of the second conductivity type channel transistor. Can be suppressed from being increased by the first conductivity type impurities in the pocket region and increasing the sheet resistance in the LDD region.

On the other hand, although the sidewall spacer containing the second conductivity type impurity is formed also on the gate electrode of the first conductivity type channel transistor, it is formed only in the formation region of the first conductivity type channel transistor before the sidewall spacer is formed. Since the impurity diffusion preventing film is formed, the second conductivity type impurities contained in the sidewall spacers do not diffuse into the semiconductor substrate in the formation region of the first conductivity type channel transistor.

Therefore, the impurity of the first conductivity type in the LDD region of the first conductivity type channel transistor is not compensated for by the impurity of the second conductivity type from the sidewall spacer, and the increase of the sheet resistance of the LDD region is prevented. You can

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention applied to the manufacture of a CMOS transistor will be described below with reference to FIGS. In this embodiment, as shown in FIG. 1A, the NMOS transistor forming region 32 of the Si substrate 31 is formed.
After the P well 34 and the N well 35 are formed in the PMOS transistor formation region 33, the SiO ₂ film 36 for element isolation is selectively formed on the surface of the Si substrate 31.

After that, the SiO ₂ film 3 as a gate oxide film is formed on the surface of the element active region surrounded by the SiO ₂ film 36.
7, a polycide layer 41 and a SiO ₂ film 42 for offset are sequentially formed. And SiO ₂
After processing the film 42 and the polycide layer 41 into the pattern of the gate electrode, the SiN film 43 with a film thickness of about 10 nm is CV.
It is deposited on the entire surface by the D method.

After that, the PMOS transistor formation region 3
3 is covered with a photoresist 44, and the photoresist 44 and the SiO ₂ films 42 and 36 are used as a mask to
s is ion-implanted into the Si substrate 31 at a dose amount of 1 × 10 ¹³ cm ⁻² to form an N ⁻ region 45 as an LDD region in the NM region.
It is formed in the OS transistor formation region 32.

Next, as shown in FIG. 1B, after removing the photoresist 44, only the NMOS transistor forming region 32 is covered with the photoresist 46, and the photoresist 46 and the SiO ₂ film 42 are removed. 36 and the like as a mask, and BF ₂ at a dose amount of 1 × 10 ¹³ cm ^-2 Si
Ions are implanted into the substrate 31 to form a P ⁻ region 47 as an LDD region in the PMOS transistor formation region 33.

Further, the photoresist 46 and the SiO ₂ film 4
As masked with 2, 36 etc., As was 1 × 10 ¹³ cm ^-2
Diagonal rotary ion implantation is performed on the Si substrate 31 at a dose of the table to form an N region 51 as a pocket region in the PMOS transistor formation region 33.

Next, as shown in FIG. 1C, the SiN film 43 is removed from the entire PMOS transistor formation region 33 by etching using the photoresist 46 as a mask. At this time, since a sufficient etching selection ratio can be secured between the SiN film 43 and the SiO ₂ film 37, the etching does not proceed to the Si substrate 31.

Next, as shown in FIG. 2A, after removing the photoresist 46, a BSG film 52 is deposited on the entire surface by a CVD method, and the entire surface of the BSG film 52 is etched back.
Sidewall spacers made of this BSG film 52 are formed on the polycide layer 41 and the SiO ₂ film 42.

Next, the PMOS transistor formation region 33
Only the surface of the Si substrate 31 is covered with a photoresist (not shown), and the As and the BSG film 52 and the SiO ₂ films 42 and 36 are used as a mask, and the dose of As is 1 × 10 ¹⁵ cm ^−2. 2B, the N ⁺ regions 53 as the source / drain regions are formed into NM as shown in FIG. 2B.
It is formed in the OS transistor formation region 32.

Then, only the NMOS transistor forming region 32 is covered with a photoresist (not shown) this time.
This photoresist, BSG film 52, and SiO ₂ film 4
BF ₂ is 1 × 10 ¹⁵ cm with masks such as ₂ , 36 etc.
Ions are implanted into the Si substrate 31 with a dose amount of ⁻² to form P ⁺ regions 54 as source / drain regions in the PMOS transistor formation region 33.

Next, as shown in FIG. 2C, after depositing the interlayer insulating film 55, the impurities in the impurity regions formed by ion implantation are activated by electric furnace annealing at about 900.degree. At this time, in the PMOS transistor formation region 33, from the BSG film 52 which is the sidewall spacer to the Si substrate 31.
B is diffused into the P ^- region 47 under the BSG film 52 to increase the impurity concentration.

[0024] Therefore, P ^- even overlapping region between the region 47 and the N region 51, P ^- P due to the B region 47 is compensated to As the N region 51 ^- increase in the sheet resistance of the region 47 is suppressed It On the other hand, the NMOS transistor formation region 3
In 2, the SiN film 43 is left and covers the surface of the Si substrate 31. Therefore, from the BSG film 52 to the Si substrate 3
The diffusion of B to 1 is prevented by the SiN film 43,
The sheet resistance of the N ⁻ region 45 below the SG film 52 does not increase.

Through the above steps, the NMOS transistor forming region 32 and the PMOS transistor forming region 33 are formed.
Then, the CMOS transistor 58 in which the NMOS transistor 56 and the PMOS transistor 57 are manufactured is completed.

Although the SiN film 43 is used as the impurity diffusion preventing film in the above embodiments, an impurity diffusion preventing film other than the SiN film 43 may be used. Further, in the above-described embodiments, the present invention is applied to the manufacture of CMOS transistors, but the present invention can also be applied to the manufacture of complementary field effect semiconductor devices other than CMOS transistors.

[0027]

According to the method of manufacturing a complementary semiconductor device according to the present invention, the second conductivity type impurity in the LDD region is the first conductivity type impurity in the pocket region even though the second conductivity type channel transistor has the pocket structure. It is possible to suppress the increase of the sheet resistance of the LDD region due to the compensation of the above, and it is also possible to prevent the increase of the sheet resistance of the LDD region in the first conductivity type channel transistor.

For this reason, punch-through hardly occurs between the source / drain of the second conductivity type channel transistor, the reliability is high, and the current driving capability is high in both the first and second conductivity type channel transistors. Type semiconductor device can be manufactured.

[Brief description of drawings]

FIG. 1 is a side sectional view sequentially showing a first half step of an embodiment of the present invention.

FIG. 2 is a side sectional view sequentially showing a latter half of steps of one embodiment.

FIG. 3 is a side sectional view sequentially showing a process in the middle of a conventional example of the present invention.

[Explanation of symbols]

31 Si substrate 41 Polycide layer 43 SiN film 45 N ^- region 47 P ^- region 51 N region 52 BSG film 53 N ⁺ region 54 P ⁺ region 56 NMOS transistor 57 PMOS transistor 58 CMOS transistor

Claims (2)

[Claims] 1. A step of forming a relatively low-concentration first conductivity type impurity region in contact with a channel region of a first conductivity type channel transistor on a semiconductor substrate, and a step of relatively contacting a channel region of a second conductivity type channel transistor. A low-concentration second-conductivity-type impurity region in the semiconductor substrate, and a first-conductivity-type impurity deeper than the relatively low-concentration second-conductivity-type impurity region and protruding toward the channel region side. Forming a region on the semiconductor substrate, forming an impurity diffusion prevention film only in a formation region of the first conductivity type channel transistor, and forming a second conductivity type impurity after forming the impurity diffusion prevention film. Forming sidewall spacers on the gate electrodes of the first and second conductivity type channel transistors; and Forming a relatively high-concentration first conductivity type impurity region in the semiconductor substrate on the side opposite to the channel region of the sidewall spacer; and forming a channel region of the sidewall spacer in the second conductivity type channel transistor. Forming a relatively high concentration second conductivity type impurity region on the opposite side of the semiconductor substrate; and removing the second conductivity type impurity contained in the sidewall spacer of the second conductivity type channel transistor. And a step of diffusing into a semiconductor substrate. 2. The method of manufacturing a complementary semiconductor device according to claim 1, wherein the second conductivity type channel transistor is a PMOS transistor, and the sidewall spacer is formed of a BSG film.