JP5064841B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Semiconductor device and manufacturing method of semiconductor device Download PDF

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JP5064841B2
JP5064841B2 JP2007055648A JP2007055648A JP5064841B2 JP 5064841 B2 JP5064841 B2 JP 5064841B2 JP 2007055648 A JP2007055648 A JP 2007055648A JP 2007055648 A JP2007055648 A JP 2007055648A JP 5064841 B2 JP5064841 B2 JP 5064841B2
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清志 林
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Renesas Electronics Corp
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本発明は、（１００）面基板上に（１１０）面結晶層が部分的に形成された半導体装置および半導体装置の製造方法に関するものである。   The present invention relates to a semiconductor device in which a (110) plane crystal layer is partially formed on a (100) plane substrate, and a method for manufacturing the semiconductor device.

従来より同一基板上にCMOSを形成する場合は、（１００）面基板を用いてPチャネルMOSFET（以下PMOSと略記），NチャネルMOSFET（以下NMOSと略記）を形成するのが一般的であった。しかし、トランジスタの特性向上の要求がある中、（１００）面基板にPMOS，NMOSを形成する半導体装置では特にPMOSの特性向上に限界があった。電子移動度は（１００）面基板の方が（１１０）面基板よりも大きいことから、NMOSは（１００）面基板上に形成すると動作が最大になるが、正孔移動度は（１１０）面基板の方が（１００）面基板よりも大きいことから、PMOSは（１１０）面基板上に形成した方が動作が最大になるためである。   Conventionally, when a CMOS is formed on the same substrate, it is common to form a P-channel MOSFET (hereinafter abbreviated as PMOS) and an N-channel MOSFET (hereinafter abbreviated as NMOS) using a (100) plane substrate. . However, while there is a demand for improving the characteristics of transistors, there is a limit to improving the characteristics of PMOS in particular in a semiconductor device in which PMOS and NMOS are formed on a (100) plane substrate. Since the (100) plane substrate has a higher electron mobility than the (110) plane substrate, the NMOS has maximum operation when formed on the (100) plane substrate, but the hole mobility has a (110) plane. This is because, since the substrate is larger than the (100) plane substrate, the operation of the PMOS is maximized when it is formed on the (110) plane substrate.

そこで、（１００）面基板上に、結晶方位＜１１０＞方向を同一方向に揃えた（１１０）面結晶層を部分的に形成するHOT（Hybrid Orientation Technology）基板を用いて、（１００）面基板上にNMOSを形成し、（１１０）面結晶層上にPMOSを形成する半導体装置が提案されている（下記非特許文献参照）。   Therefore, a (100) plane substrate is formed using a HOT (Hybrid Orientation Technology) substrate that partially forms a (110) plane crystal layer in which the crystal orientation <110> direction is aligned in the same direction on the (100) plane substrate. A semiconductor device has been proposed in which an NMOS is formed thereon and a PMOS is formed on a (110) plane crystal layer (see the following non-patent document).

M.Yang et al.，IEEE TRANSACTIONS ON ELECTRON DEVICES,VOL.５３,NO．５，２００６年５月，p９６５M. Yang et al., IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL.53, NO. 5, May 2006, p965 C.Y.Sung et al.，IEDM，２００５年，p２３５C.Y.Sung et al., IEDM, 2005, p235

半導体装置の効率的なレイアウトは一般的にNMOS，PMOSともチャネル方向が直交するような２種類の方向を混在して省スペース化を実現している。上記非特許文献に記載されているHOT基板を用いた半導体装置において、（１００）面基板ではチャネル方向が直交する場合、それぞれの結晶方位は同等であるため直交するNMOSのドレイン電流（Id）は同一である。また、チャネルの移動度が最大の結晶方位＜１１０＞方向が使えるためIdが最大になる。   An efficient layout of a semiconductor device generally achieves space saving by mixing two types of directions in which the channel directions are orthogonal to each other in both NMOS and PMOS. In the semiconductor device using the HOT substrate described in the above non-patent document, when the channel directions are orthogonal to each other on the (100) plane substrate, the respective NMOSs have the same crystal orientation, so the drain current (Id) of the orthogonal NMOS is Are the same. Also, since the crystal orientation <110> direction with the maximum channel mobility can be used, Id is maximized.

しかしながら、（１１０）面結晶上にチャネル方向が直交するようにPMOSを形成する場合、最大の移動度を示す結晶方位＜１１０＞方向に対して直交する結晶方位は最小の移動度を示す＜１００＞方向に相当する。従って、（１１０）面結晶層上にPMOSを形成する場合、チャネルが直交するレイアウトでは、それぞれのIdが同一にならないためデバイスの特性が変わるという問題があった。   However, when the PMOS is formed on the (110) plane crystal so that the channel directions are orthogonal, the crystal orientation perpendicular to the crystal orientation <110> showing the maximum mobility shows the minimum mobility <100. > Corresponds to the direction. Therefore, when a PMOS is formed on a (110) plane crystal layer, there is a problem that the characteristics of the device change because the respective Ids are not the same in a layout in which the channels are orthogonal.

また、上記問題を解消するために、チャネル方向を直交二方向でなく結晶方位＜１１０＞方向の一方向にそろえることによりPMOSの特性は向上しIdのバラツキも解消するが、レイアウトの自由度がなくなり、チップサイズが大きくなるという問題があった。   In addition, in order to solve the above problem, by aligning the channel direction to one direction of the crystal orientation <110> instead of the two orthogonal directions, the characteristics of the PMOS are improved and the variation in Id is also eliminated. There was a problem that the chip size was increased.

そこで本発明はかかる問題を解決するためになされたものであり、チャネル方向が直交する効率的なレイアウト構成をとり、（１００）結晶面上に形成したPMOSよりも特性が向上し、IdのバラツキのないCMOS領域を備えた半導体装置を得ることを目的としている。   Accordingly, the present invention has been made to solve such a problem, and has an efficient layout configuration in which the channel directions are orthogonal to each other, has improved characteristics as compared with a PMOS formed on a (100) crystal plane, and has a variation in Id. An object of the present invention is to obtain a semiconductor device having a CMOS region without any defects.

本発明の一実施形態における半導体装置は、（１００）面基板と、前記（１００）面基板上に部分的に形成された（１１０）面結晶層と、前記（１００）面基板上にチャネルが直交する方向に配置された複数のNチャネルMOSFETと、前記（１１０）面結晶層上にチャネルが直交する方向に配置された複数のPチャネルMOSFETとを備える。前記（１１０）面結晶層は、その結晶方位＜１１０＞方向が、前記（１００）面基板の結晶方位＜１１０＞方向と同一方向であり、前記複数のNチャネルMOSFETは、チャネルの方向が前記（１００）面基板の結晶方位＜１１０＞方向とその直交方向とに配置され、前記複数のPチャネルMOSFETは、チャネルの方向が前記（１１０）面結晶層の結晶方位＜１１０＞方向に対し４５°回転した方向に配置される。 A semiconductor device according to an embodiment of the present invention includes a (100) plane substrate, a (110) plane crystal layer partially formed on the (100) plane substrate, and a channel on the (100) plane substrate. A plurality of N-channel MOSFETs arranged in a direction orthogonal to each other and a plurality of P-channel MOSFETs arranged in a direction perpendicular to the channel on the (110) plane crystal layer . The (110) plane crystal layer has a crystal orientation <110> direction is a crystal orientation <110> in the same direction of the (100) plane substrate, said plurality of N-channel a MOSFET T, the direction of Ji Yaneru Are arranged in the crystal orientation <110> direction of the (100) plane substrate and the orthogonal direction thereof, and the plurality of P-channel MOSFETs have a channel direction in the crystal orientation <110> direction of the (110) plane crystal layer. Ru is located 45 ° rotated direction against.

本発明の一実施形態によれば、PMOSを形成する（１１０）面結晶層の結晶方位＜１１０＞方向を、NMOSを形成する（１００）面基板の結晶方位＜１１０＞方向と揃うように張り合わせてHOT基板を形成する。NMOSはチャネルの方向が（１００）面基板の結晶方位＜１１０＞方向とその直交方向とに配置され、PMOSはチャネル方向が（１１０）面結晶層および（１００）面基板の結晶方位＜１１０＞方向から４５°回転した結晶方向に配置される。この構成により、PMOSのチャネル方向は（１１０）面結晶層の結晶方位＜１１０＞方向から４５°回転した方向となり、直交して配置されたチャネル方向の結晶方位は同等になる。よって、チャネル方向が直交する効率的なレイアウト構成をとることができ、かつ、それぞれのPMOSのIdは同一になり、さらに（１００）結晶面上に形成したPMOSよりも特性が向上した半導体装置を得ることができる。 According to an embodiment of the present invention, to form a PMOS (110) plane crystal orientation <110> direction of the crystal layer, to form the NMOS (100) plane crystal orientation <1 1 0> of the substrate so as to align with the direction The HOT substrate is formed by bonding to The NMOS has a channel direction arranged in the <100> plane crystal orientation <110> direction and a direction orthogonal thereto, and the PMOS has a (110) plane crystal layer and a (100) plane crystal orientation <110> in the channel direction. to 45 ° rotated crystal direction from the direction Ru is placed. With this configuration, the channel direction of the PMOS is a direction rotated by 45 ° from the crystal orientation <110> direction of the (110) plane crystal layer , and the crystal orientations of the channel directions arranged orthogonally are equal. Therefore, an efficient layout configuration in which the channel directions are orthogonal to each other, the Id of each PMOS is the same, and a semiconductor device with improved characteristics as compared to a PMOS formed on a (100) crystal plane Obtainable.

［参考形態１］
図１はCMOS領域４を形成するSPE（Solid Phase Epitaxy）技術を示した図である。図１（a）の（１００）面基板１上に図１（a）の（１１０）面基板２を張り合わせたHOT（Hybrid Orientation Technology）基板３（図１（b））のうち、CMOSを形成する領域の一部（図１（c））を抜き出して説明する。 [ Reference Form 1]
FIG. 1 is a diagram showing an SPE (Solid Phase Epitaxy) technique for forming a CMOS region 4. Of the HOT (Hybrid Orientation Technology) substrate 3 (FIG. 1 (b)) in which the (110) surface substrate 2 of FIG. 1 (a) is bonded to the (100) surface substrate 1 of FIG. 1 (a), a CMOS is formed. A part of the area to be processed (FIG. 1C) will be extracted and described.

CMOS領域４のうちのPMOS領域にレジスト５を生成し、CMOS領域４上からSiを注入してNMOS領域のみ（１１０）面基板２をアモルファス化する（図１（d））。次にアニール処理を行いアモルファス化された部分が基板を種結晶として固層エピ成長し、（１１０）面基板２の結晶状態が（１００）面基板１と同じ結晶状態に変換される（図１（e））。次に素子分離（STI）を行い、PMOS，NMOS領域にそれぞれPMOS２２，NMOS２１（図２参照）を形成することにより、HOT基板３上にCMOS領域４が形成される（図１（f））。   A resist 5 is formed in the PMOS region of the CMOS region 4 and Si is implanted from above the CMOS region 4 to amorphize the (110) plane substrate 2 only in the NMOS region (FIG. 1 (d)). Next, the annealed portion is subjected to solid-phase epi growth using the substrate as a seed crystal, and the crystal state of the (110) plane substrate 2 is converted to the same crystal state as that of the (100) plane substrate 1 (FIG. 1). (E)). Next, element isolation (STI) is performed, and PMOS 22 and NMOS 21 (see FIG. 2) are formed in the PMOS and NMOS regions, respectively, thereby forming the CMOS region 4 on the HOT substrate 3 (FIG. 1 (f)).

図２は本発明の参考形態１における半導体装置のCMOS領域４の一部を示した図である。本発明の参考形態１の特徴は、図１の工程を行い、（１００）面基板１上に部分的に（１１０）面結晶層１０（図１の（１１０）面基板２よりなる）を形成する際に、（１１０）面結晶層１０の結晶方位＜１１０＞方向が、ベース基板の（１００）面基板１の結晶方位＜１１０＞方向に対し、４５°回転して張り合わせて図１（a），（b）の工程を行うことによりHOT基板３を形成する点である。このHOT基板３を用いて、NMOS２１は（１００）面基板１上にチャネルが直交する方向に複数配置され、PMOS２２は（１１０）面結晶層１０上にチャネルが直交する方向に複数配置され、CMOS領域４を形成する。 Figure 2 is a diagram showing a part of the CMOS region 4 of the semiconductor device in Reference Embodiment 1 of the present invention. Features of Reference Embodiment 1 of the present invention performs the steps of FIG. 1, forming in part on (100) plane on the substrate 1 (110) plane crystal layer 10 (made of (110) plane substrate 2 in FIG. 1) In this case, the crystal orientation <110> direction of the (110) plane crystal layer 10 is rotated by 45 ° with respect to the crystal orientation <110> direction of the (100) plane substrate 1 of the base substrate and bonded together as shown in FIG. ), (B) is the point at which the HOT substrate 3 is formed. Using this HOT substrate 3, a plurality of NMOSs 21 are arranged on the (100) plane substrate 1 in the direction in which the channels are orthogonal, and a plurality of PMOSs 22 are arranged on the (110) plane crystal layer 10 in the direction in which the channels are orthogonal to each other. Region 4 is formed.

ここで、NMOS２１およびPMOS２２は、ともにチャネルの方向が同一であり、（１００）面基板１の結晶方位＜１１０＞方向とその直交方向とに配置される。すなわち、PMOS２２のチャネル方向は（１１０）面結晶層１０の結晶方位＜１１０＞方向から４５°回転した結晶方向になる。   Here, both the NMOS 21 and the PMOS 22 have the same channel direction, and are arranged in the crystal orientation <110> direction of the (100) plane substrate 1 and the orthogonal direction thereof. That is, the channel direction of the PMOS 22 is a crystal direction rotated by 45 ° from the crystal orientation <110> direction of the (110) plane crystal layer 10.

以上のレイアウト構成から、PMOS２２は（１１０）面結晶層１０の結晶方位＜１１０＞方向から４５°回転した方向がチャネルとなり、直交して配置されたチャネル方向の結晶方位は同等になるため、それぞれのPMOS２２のIdは同等になる。また、PMOS２２の配置とNMOS２１の配置が同一方向に設定できるので、CMOSとして効率良くレイアウトができる。また、この時のNMOS２１のチャネル方向は、（１００）面基板１の結晶方位＜１１０＞方向が使えるためチャネルの移動度が最大になる。   From the above layout configuration, the PMOS 22 has a channel rotated by 45 ° from the crystal orientation <110> direction of the (110) plane crystal layer 10, and the crystal orientation in the channel direction arranged orthogonally becomes equal. The Id of the PMOS 22 is equal. Further, since the arrangement of the PMOS 22 and the arrangement of the NMOS 21 can be set in the same direction, the layout can be efficiently performed as a CMOS. Further, since the channel direction of the NMOS 21 at this time can use the crystal orientation <110> direction of the (100) plane substrate 1, the channel mobility is maximized.

［実施の形態１］
図３は本発明の実施の形態１における半導体装置のCMOS領域４の一部を示した図である。図１の工程を行い、（１００）面基板１上に部分的に（１１０）面結晶層１０（図１の（１１０）面基板２よりなる）を形成する際に、（１１０）面結晶層１０の結晶方位＜１１０＞方向が、ベース基板の（１００）面基板１の結晶方位＜１１０＞方向と揃うように張り合わせて図１（a），（b）の工程を行うことによりHOT基板３を形成する。このHOT基板３を用いて、NMOS２１は（１００）面基板１上にチャネルが直交する方向に複数配置され、PMOS２２は（１１０）面結晶層１０上にチャネルが直交する方向に複数配置され、CMOS領域４を形成する。 [Embodiment 1 ]
FIG. 3 is a diagram showing a part of CMOS region 4 of the semiconductor device according to the first embodiment of the present invention. When the step of FIG. 1 is performed to partially form the (110) plane crystal layer 10 (consisting of the (110) plane substrate 2 of FIG. 1) on the (100) plane substrate 1, the (110) plane crystal layer is formed. The HOT substrate 3 is obtained by performing the steps of FIGS. 1A and 1B by bonding the 10 crystal orientation <110> directions to the crystal orientation <110> direction of the (100) plane substrate 1 of the base substrate. Form. Using this HOT substrate 3, a plurality of NMOSs 21 are arranged on the (100) plane substrate 1 in the direction in which the channels are orthogonal, and a plurality of PMOSs 22 are arranged on the (110) plane crystal layer 10 in the direction in which the channels are orthogonal to each other. Region 4 is formed.

ここで本発明の実施の形態１の特徴は、NMOS２１はチャネルの方向が（１００）面基板１の結晶方位＜１１０＞方向とその直交方向とに配置され、PMOS２２はチャネル方向が（１１０）面結晶層１０および（１００）面基板１の結晶方位＜１１０＞方向から４５°回転した結晶方向に配置される点である。 Here, the first embodiment of the present invention is characterized in that the NMOS 21 has a channel direction arranged in the (100) plane substrate 1 in the crystal orientation <110> direction and a direction perpendicular thereto, and the PMOS 22 has a channel direction (110) plane. The crystal layer 10 and the (100) plane substrate 1 are arranged in a crystal direction rotated by 45 ° from the crystal orientation <110> direction.

以上のレイアウト構成から、PMOS２２は（１１０）面結晶層１０の結晶方位＜１１０＞方向から４５°回転した方向がチャネルとなり、直交して配置されたチャネル方向の結晶方位は同等になるため、それぞれのPMOS２２のIdは同等になる。また、この時のNMOS２１のチャネル方向は、（１００）面基板１の結晶方位＜１１０＞方向が使えるためチャネルの移動度が最大になる。   From the above layout configuration, the PMOS 22 has a channel rotated by 45 ° from the crystal orientation <110> direction of the (110) plane crystal layer 10, and the crystal orientation in the channel direction arranged orthogonally becomes equal. The Id of the PMOS 22 is equal. Further, since the channel direction of the NMOS 21 at this time can use the crystal orientation <110> direction of the (100) plane substrate 1, the channel mobility is maximized.

［参考形態２］
図４は本発明の参考形態２における半導体装置のCMOS領域４の一部を示した図である。図１の工程を行い、（１００）面基板１上に部分的に（１１０）面結晶層１０（図１の（１１０）面基板２よりなる）を形成する際に、（１１０）面結晶層１０の結晶方位＜１１０＞方向が、ベース基板の（１００）面基板１の結晶方位＜１１０＞方向と揃うように張り合わせて図１（a），（b）の工程を行うことによりHOT基板３を形成する。このHOT基板３を用いて、NMOS２１は（１００）面基板１上にチャネルが直交する方向に複数配置され、PMOS２２は（１１０）面結晶層１０上にチャネルが直交する方向に複数配置され、CMOS領域４を形成する。 [ Reference form 2 ]
Figure 4 is a diagram showing a part of the CMOS region 4 of the semiconductor device in Reference Embodiment 2 of the present invention. When the step of FIG. 1 is performed to partially form the (110) plane crystal layer 10 (consisting of the (110) plane substrate 2 of FIG. 1) on the (100) plane substrate 1, the (110) plane crystal layer is formed. The HOT substrate 3 is obtained by performing the steps of FIGS. 1A and 1B by bonding the 10 crystal orientation <110> directions to the crystal orientation <110> direction of the (100) plane substrate 1 of the base substrate. Form. Using this HOT substrate 3, a plurality of NMOSs 21 are arranged on the (100) plane substrate 1 in the direction in which the channels are orthogonal, and a plurality of PMOSs 22 are arranged on the (110) plane crystal layer 10 in the direction in which the channels are orthogonal to each other. Region 4 is formed.

NMOS２１およびPMOS２２は、ともにチャネルの方向が同一であり、（１００）面基板１および（１１０）面結晶層１０の結晶方位＜１１０＞方向とその直交方向とに配置される。   Both the NMOS 21 and the PMOS 22 have the same channel direction and are arranged in the crystal orientation <110> direction of the (100) plane substrate 1 and the (110) plane crystal layer 10 and the orthogonal direction thereof.

ここで、チャネル移動度はチャネル方向が結晶方位＜１００＞方向が最小であり、結晶方位＜１１０＞方向が最大であることから、直交して配置されたPMOS２２のうち、チャネル方向が結晶方位＜１００＞方向のPMOS２２のIdは結晶方位＜１１０＞方向に対し約３０％劣化する。そこで、本発明の参考形態２の特徴は、以下のブースト手段を付加して結晶方位＜１００＞方向のチャネルの移動度を大きくする点である。 Here, the channel mobility is such that the channel direction has the minimum crystal orientation <100> direction and the crystal orientation <110> direction has the maximum. Therefore, among the PMOSs 22 arranged orthogonally, the channel direction is the crystal orientation < The Id of the PMOS 22 in the 100> direction deteriorates by about 30% with respect to the crystal orientation <110> direction. Therefore, a feature of Reference Embodiment 2 of the present invention is that the following boost means is added to increase the mobility of the channel in the crystal orientation <100> direction.

図６は第１のブースト手段を示す図である。チャネル方向が＜１００＞方向のPMOS領域（図４の圧縮歪み領域２３）のみ、ソース・ドレイン領域のSiをリセスエッチングして、エッチングしたソース・ドレイン領域にSiGe等のSiより格子定数の大きい材料を選択エピタキシャル成長させる。例えば、ボロン（B）をドーピングしたGe濃度２０％のSiGeが用いられる。これによりSiの結晶格子中のGeにより、リセス・ソース・ドレイン間チャネルが一軸圧縮応力で歪むため、正孔の移動度が大きくなり駆動電流Idが大きくなる。   FIG. 6 is a diagram showing the first boost means. Only in the PMOS region (compressive strain region 23 in FIG. 4) whose channel direction is the <100> direction, Si in the source / drain region is recess-etched, and the etched source / drain region has a larger lattice constant than Si, such as SiGe. Is selectively epitaxially grown. For example, SiGe doped with boron (B) and having a Ge concentration of 20% is used. As a result, the recess-source-drain channel is distorted by uniaxial compressive stress due to Ge in the Si crystal lattice, so that the hole mobility increases and the drive current Id increases.

図７は第２のブースト手段を示す図である。チャネル方向が＜１００＞方向のPMOS領域（図４の圧縮歪み領域２３）のみ、PMOS２２上にSiN等のストレス膜（圧縮膜）３６を導入する。これにより＜１００＞方向のチャネル部には一軸圧縮歪みが働き、正孔の移動度が大きくなり駆動電流Idが大きくなる。   FIG. 7 is a diagram showing the second boost means. A stress film (compressed film) 36 such as SiN is introduced on the PMOS 22 only in the PMOS region (compression strain region 23 in FIG. 4) whose channel direction is the <100> direction. As a result, uniaxial compression strain acts on the channel portion in the <100> direction, the hole mobility increases, and the drive current Id increases.

図８は第３のブースト手段を示す図である。チャネル方向が＜１００＞方向のPMOS領域（図４の圧縮歪み領域２３）のSi層上の表面にSiGe等のSiより格子定数の大きい半導体材料を選択エピタキシャル成長させ、このエピ層上にPMOS２２を形成する。これにより＜１００＞方向のチャネル部には二軸圧縮歪みが働き、正孔の移動度が大きくなり駆動電流Idが大きくなる。   FIG. 8 is a diagram showing third boost means. A semiconductor material having a lattice constant larger than that of Si, such as SiGe, is selectively epitaxially grown on the surface of the Si layer in the PMOS region (compressive strain region 23 in FIG. 4) whose channel direction is the <100> direction, and the PMOS 22 is formed on this epitaxial layer. To do. As a result, biaxial compression strain acts on the channel portion in the <100> direction, the hole mobility increases, and the drive current Id increases.

以上の構成から、＜１００＞方向のPMOS２２のIdが増加し、＜１１０＞方向のIdと同等にすることが出来る。また、この時のNMOS２１のチャネル方向は、（１００）面基板１の結晶方位＜１１０＞方向が使えるためチャネルの移動度が最大になる。   From the above configuration, the Id of the PMOS 22 in the <100> direction is increased and can be made equal to the Id in the <110> direction. Further, since the channel direction of the NMOS 21 at this time can use the crystal orientation <110> direction of the (100) plane substrate 1, the channel mobility is maximized.

［参考形態３］
図５は本発明の参考形態３における半導体装置のCMOS領域４の一部を示した図である。図１の工程を行い、（１００）面基板１上に部分的に（１１０）面結晶層１０（図１の（１１０）面基板２よりなる）を形成する際に、（１１０）面結晶層１０の結晶方位＜１１０＞方向が、ベース基板の（１００）面基板１の結晶方位＜１１０＞方向と揃うように張り合わせて図１（a），（b）の工程を行うことによりHOT基板３を形成する。このHOT基板３を用いて、NMOS２１は（１００）面基板１上にチャネルが直交する方向に複数配置され、PMOS２２は（１１０）面結晶層１０上にチャネルが直交する方向に複数配置され、CMOS領域４を形成する。 [ Reference form 3 ]
Figure 5 is a diagram showing a part of the CMOS region 4 of the semiconductor device in Reference Embodiment 3 of the present invention. When the step of FIG. 1 is performed to partially form the (110) plane crystal layer 10 (consisting of the (110) plane substrate 2 of FIG. 1) on the (100) plane substrate 1, the (110) plane crystal layer is formed. The HOT substrate 3 is obtained by performing the steps of FIGS. 1A and 1B by bonding the 10 crystal orientation <110> directions to the crystal orientation <110> direction of the (100) plane substrate 1 of the base substrate. Form. Using this HOT substrate 3, a plurality of NMOSs 21 are arranged on the (100) plane substrate 1 in the direction in which the channels are orthogonal, and a plurality of PMOSs 22 are arranged on the (110) plane crystal layer 10 in the direction in which the channels are orthogonal to each other. Region 4 is formed.

NMOS２１およびPMOS２２は、ともにチャネルの方向が同一であり、（１００）面基板１および（１１０）面結晶層１０の結晶方位＜１１０＞方向とその直交方向とに配置される。   Both the NMOS 21 and the PMOS 22 have the same channel direction and are arranged in the crystal orientation <110> direction of the (100) plane substrate 1 and the (110) plane crystal layer 10 and the orthogonal direction thereof.

ここで、参考形態２と同様に、直交して配置されたPMOS２２のうち、チャネル方向が＜１００＞方向のPMOS２２のIdは＜１１０＞方向に対し約３０％劣化する。そこで、本発明の参考形態３の特徴は、チャネル方向が＜１００＞方向のPMOS２２のW（チャネル幅）を＜１１０＞方向のPMOS２２のWより大きくする点である。 Here, similarly to Reference Embodiment 2, among the PMOS22 which are arranged orthogonally, the channel direction Id of PMOS22 the <100> direction is deteriorated by about 30% to <110> direction. Therefore, characteristics of the reference embodiment 3 of the present invention is that the channel direction is larger than W of the <100> direction of the PMOS 22 of the W (channel width) of the <110> direction PMOS 22.

以上の構成から、＜１００＞方向のPMOS２２のIdが増加し、＜１１０＞方向のIdと同等にすることが出来る。また、この時のNMOS２１のチャネル方向は、（１００）面基板１の結晶方位＜１１０＞方向が使えるためチャネルの移動度が最大になる。   From the above configuration, the Id of the PMOS 22 in the <100> direction is increased and can be made equal to the Id in the <110> direction. Further, since the channel direction of the NMOS 21 at this time can use the crystal orientation <110> direction of the (100) plane substrate 1, the channel mobility is maximized.

HOT基板にCMOS領域を形成する工程を示した図である。It is the figure which showed the process of forming a CMOS area | region in a HOT substrate. 本発明の参考形態１における半導体装置のCMOS領域の一部を示した図である。It is the figure which showed a part of CMOS area | region of the semiconductor device in the reference form 1 of this invention. 本発明の実施の形態１における半導体装置のCMOS領域の一部を示した図である。It is the figure which showed a part of CMOS area | region of the semiconductor device in Embodiment 1 of this invention. 本発明の参考形態２における半導体装置のCMOS領域の一部を示した図である。It is the figure which showed a part of CMOS area | region of the semiconductor device in the reference form 2 of this invention. 本発明の参考形態３における半導体装置のCMOS領域の一部を示した図である。It is the figure which showed a part of CMOS area | region of the semiconductor device in the reference form 3 of this invention. 本発明の参考形態２における半導体装置の圧縮歪みを示した図である。It is the figure which showed the compressive distortion of the semiconductor device in the reference form 2 of this invention. 本発明の参考形態２における半導体装置の圧縮歪みを示した図である。It is the figure which showed the compressive distortion of the semiconductor device in the reference form 2 of this invention. 本発明の参考形態２における半導体装置の圧縮歪みを示した図である。It is the figure which showed the compressive distortion of the semiconductor device in the reference form 2 of this invention.

符号の説明Explanation of symbols

１ （１００）面基板、２ （１１０）面基板、３ HOT基板、４ CMOS領域、５ レジスト、１０ （１１０）面結晶層、２１ NMOS、２２ PMOS、２３ 圧縮歪み領域、３１ ゲート絶縁膜、３２ ゲート、３３ サイドウォール、３４ チャネル部、３５ エクステンション、３６ ストレス膜。   1 (100) plane substrate, 2 (110) plane substrate, 3 HOT substrate, 4 CMOS region, 5 resist, 10 (110) plane crystal layer, 21 NMOS, 22 PMOS, 23 compressive strain region, 31 gate insulating film, 32 Gate, 33 sidewall, 34 channel part, 35 extension, 36 stress film.

Claims (2)

（１００）面基板と、
前記（１００）面基板上に部分的に形成された（１１０）面結晶層と、
前記（１００）面基板上にチャネルが直交する方向に配置された複数のNチャネルMOSFETと、
前記（１１０）面結晶層上にチャネルが直交する方向に配置された複数のPチャネルMOSFETと、を備え、
前記（１１０）面結晶層は、その結晶方位＜１１０＞方向が、前記（１００）面基板の結晶方位＜１１０＞方向と同一方向であり、
前記複数のNチャネルMOSFETは、チャネルの方向が前記（１００）面基板の結晶方位＜１１０＞方向とその直交方向とに配置され、
前記複数のPチャネルMOSFETは、チャネルの方向が前記（１１０）面結晶層の結晶方位＜１１０＞方向に対し４５°回転した方向に配置される半導体装置。 A (100) surface substrate;
A (110) plane crystal layer partially formed on the (100) plane substrate;
A plurality of N-channel MOSFETs arranged on the (100) plane substrate in a direction in which the channels are orthogonal;
A plurality of P-channel MOSFETs arranged in a direction perpendicular to the channel on the (110) plane crystal layer,
The (110) plane crystal layer has a crystal orientation <110> direction, the (100) plane is a crystal orientation <110> in the same direction as the direction of the substrate,
Wherein the plurality of N-channel a MOSFET T may be disposed on the the direction of the switch Yaneru (100) plane crystal orientation of the substrate <110> direction and its perpendicular direction,
Wherein the plurality of P-channel MOSFET, the direction of the channel is the (110) plane crystal layer crystal orientation <110> semiconductor device that will be placed in the 45 ° rotated to the direction of. 請求項１に記載の半導体装置を製造する方法であって、
前記（１００）面基板を準備する工程と、
前記（１００）面基板上に（１１０）面基板を張り合わせる工程とを備え、
前記（１１０）面基板は、その結晶方位＜１１０＞方向が、前記（１００）面基板の結晶方位＜１１０＞方向と同一方向に、前記（１００）面基板に張り合わされ、
前記（１１０）面基板の結晶状態を部分的に、前記（１００）面基板と同じ結晶状態に変換する工程と、を備える半導体装置の製造方法。 A method of manufacturing the semiconductor device according to claim 1,
Preparing the (100) plane substrate;
Bonding the (110) plane substrate onto the (100) plane substrate,
The (110) plane substrate is bonded to the (100) plane substrate so that the crystal orientation <110> direction is the same as the crystal orientation <110> direction of the (100) plane substrate.
A step of partially converting the crystal state of the (110) plane substrate to the same crystal state as that of the (100) plane substrate.
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