JP6108935B2 - スタンダードセル、半導体装置、及び電子機器 - Google Patents

スタンダードセル、半導体装置、及び電子機器 Download PDF

Info

Publication number
JP6108935B2
JP6108935B2 JP2013090946A JP2013090946A JP6108935B2 JP 6108935 B2 JP6108935 B2 JP 6108935B2 JP 2013090946 A JP2013090946 A JP 2013090946A JP 2013090946 A JP2013090946 A JP 2013090946A JP 6108935 B2 JP6108935 B2 JP 6108935B2
Authority
JP
Japan
Prior art keywords
transistor
conductive layer
insulating layer
layer
electrically connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2013090946A
Other languages
English (en)
Japanese (ja)
Other versions
JP2013243353A5 (enrdf_load_stackoverflow
JP2013243353A (ja
Inventor
拓郎 王丸
拓郎 王丸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP2013090946A priority Critical patent/JP6108935B2/ja
Publication of JP2013243353A publication Critical patent/JP2013243353A/ja
Publication of JP2013243353A5 publication Critical patent/JP2013243353A5/ja
Application granted granted Critical
Publication of JP6108935B2 publication Critical patent/JP6108935B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
JP2013090946A 2012-04-27 2013-04-24 スタンダードセル、半導体装置、及び電子機器 Expired - Fee Related JP6108935B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2013090946A JP6108935B2 (ja) 2012-04-27 2013-04-24 スタンダードセル、半導体装置、及び電子機器

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2012102167 2012-04-27
JP2012102167 2012-04-27
JP2013090946A JP6108935B2 (ja) 2012-04-27 2013-04-24 スタンダードセル、半導体装置、及び電子機器

Publications (3)

Publication Number Publication Date
JP2013243353A JP2013243353A (ja) 2013-12-05
JP2013243353A5 JP2013243353A5 (enrdf_load_stackoverflow) 2016-06-16
JP6108935B2 true JP6108935B2 (ja) 2017-04-05

Family

ID=49843919

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013090946A Expired - Fee Related JP6108935B2 (ja) 2012-04-27 2013-04-24 スタンダードセル、半導体装置、及び電子機器

Country Status (1)

Country Link
JP (1) JP6108935B2 (enrdf_load_stackoverflow)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6000863B2 (ja) * 2013-01-24 2016-10-05 株式会社半導体エネルギー研究所 半導体装置、及びその駆動方法
US10074576B2 (en) * 2014-02-28 2018-09-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor memory device
JP6553444B2 (ja) * 2014-08-08 2019-07-31 株式会社半導体エネルギー研究所 半導体装置
WO2016128853A1 (en) * 2015-02-09 2016-08-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, electronic component, and electronic device
WO2021090104A1 (ja) * 2019-11-08 2021-05-14 株式会社半導体エネルギー研究所 半導体装置およびその作製方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3746979B2 (ja) * 2001-10-03 2006-02-22 富士通株式会社 半導体装置及びその製造方法
FR2839581B1 (fr) * 2002-05-07 2005-07-01 St Microelectronics Sa Circuit electronique comprenant un condensateur et au moins un composant semiconducteur, et procede de conception d'un tel circuit
JP4872197B2 (ja) * 2004-08-25 2012-02-08 カシオ計算機株式会社 薄膜トランジスタパネル及びその製造方法
WO2011074408A1 (en) * 2009-12-18 2011-06-23 Semiconductor Energy Laboratory Co., Ltd. Non-volatile latch circuit and logic circuit, and semiconductor device using the same

Also Published As

Publication number Publication date
JP2013243353A (ja) 2013-12-05

Similar Documents

Publication Publication Date Title
JP6513768B2 (ja) 半導体装置
JP6043419B2 (ja) プログラマブルロジックデバイス
JP6815446B2 (ja) 半導体装置
JP6203300B2 (ja) 半導体装置
US10090023B2 (en) Memory device including memory circuit and selection circuit
US9165632B2 (en) Memory device and semiconductor device
JP6403853B2 (ja) プロセッサ
US8896345B2 (en) Semiconductor device
JP6272713B2 (ja) プログラマブルロジックデバイス及び半導体装置
JP6108935B2 (ja) スタンダードセル、半導体装置、及び電子機器
JP2013251893A (ja) 半導体装置の駆動方法
JP2016105590A (ja) 論理回路、および論理回路を有する半導体装置
JP2019213202A (ja) 半導体装置
JP6087652B2 (ja) 記憶回路
TWI621127B (zh) 運算處理裝置及其驅動方法
JP6333028B2 (ja) 記憶装置及び半導体装置
US10095584B2 (en) Semiconductor device

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20160420

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20160420

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20170208

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20170214

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20170307

R150 Certificate of patent or registration of utility model

Ref document number: 6108935

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees