JP6081600B2 - ノイズ減衰壁 - Google Patents

ノイズ減衰壁 Download PDF

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Publication number
JP6081600B2
JP6081600B2 JP2015533073A JP2015533073A JP6081600B2 JP 6081600 B2 JP6081600 B2 JP 6081600B2 JP 2015533073 A JP2015533073 A JP 2015533073A JP 2015533073 A JP2015533073 A JP 2015533073A JP 6081600 B2 JP6081600 B2 JP 6081600B2
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Japan
Prior art keywords
vias
interconnects
noise
coupled
interposer
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JP2015533073A
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English (en)
Japanese (ja)
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JP2016500198A (ja
JP2016500198A5 (https=
Inventor
エルドマン，クリストフ
カレン，エドワード
ロウニー，ドナチャ
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Xilinx Inc
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Xilinx Inc
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Publication of JP2016500198A publication Critical patent/JP2016500198A/ja
Publication of JP2016500198A5 publication Critical patent/JP2016500198A5/ja
Application granted granted Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H10W44/203—Electrical connections
    • H10W44/209—Vertical interconnections, e.g. vias
    • H10W44/212—Coaxial feed-throughs in substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/641—Adaptable interconnections, e.g. fuses or antifuses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

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  • Semiconductor Integrated Circuits (AREA)
  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Building Environments (AREA)
JP2015533073A 2012-09-25 2013-08-21 ノイズ減衰壁 Active JP6081600B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/626,829 2012-09-25
US13/626,829 US9054096B2 (en) 2012-09-25 2012-09-25 Noise attenuation wall
PCT/US2013/055993 WO2014051894A2 (en) 2012-09-25 2013-08-21 Noise attenuation wall

Publications (3)

Publication Number Publication Date
JP2016500198A JP2016500198A (ja) 2016-01-07
JP2016500198A5 JP2016500198A5 (https=) 2016-09-15
JP6081600B2 true JP6081600B2 (ja) 2017-02-15

Family

ID=49054941

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015533073A Active JP6081600B2 (ja) 2012-09-25 2013-08-21 ノイズ減衰壁

Country Status (6)

Country Link
US (1) US9054096B2 (https=)
EP (1) EP2901478B1 (https=)
JP (1) JP6081600B2 (https=)
KR (1) KR102132046B1 (https=)
CN (1) CN104704630B (https=)
WO (1) WO2014051894A2 (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9343418B2 (en) * 2013-11-05 2016-05-17 Xilinx, Inc. Solder bump arrangements for large area analog circuitry
US10057976B1 (en) 2017-08-31 2018-08-21 Xilinx, Inc. Power-ground co-reference transceiver structure to deliver ultra-low crosstalk
US10665554B2 (en) * 2017-10-30 2020-05-26 Taiwan Semiconductor Manufacturing Company Ltd. Magnetic structure for transmission lines in a package system
CN111312692A (zh) * 2018-12-11 2020-06-19 创意电子股份有限公司 集成电路封装元件及其载板
WO2024062719A1 (en) * 2022-09-22 2024-03-28 Sony Semiconductor Solutions Corporation Semiconductor package, semiconductor module, electronic device, and semiconductor package manufacturing method

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03165058A (ja) 1989-11-24 1991-07-17 Mitsubishi Electric Corp 半導体装置
JPH11121643A (ja) * 1997-10-09 1999-04-30 Hitachi Ltd 半導体装置
JP3451038B2 (ja) * 1999-08-27 2003-09-29 シャープ株式会社 誘電体回路基板およびそれを含むミリ波半導体装置
US6362525B1 (en) * 1999-11-09 2002-03-26 Cypress Semiconductor Corp. Circuit structure including a passive element formed within a grid array substrate and method for making the same
US6486534B1 (en) 2001-02-16 2002-11-26 Ashvattha Semiconductor, Inc. Integrated circuit die having an interference shield
US6686649B1 (en) 2001-05-14 2004-02-03 Amkor Technology, Inc. Multi-chip semiconductor package with integral shield and antenna
JP4057921B2 (ja) * 2003-01-07 2008-03-05 株式会社東芝 半導体装置およびそのアセンブリ方法
EP1775761A4 (en) * 2004-07-06 2007-08-29 Tokyo Electron Ltd SUBSTRATE AND INTERMEDIATE AND METHOD FOR PRODUCING A SUBSTRATE
DE102006022360B4 (de) 2006-05-12 2009-07-09 Infineon Technologies Ag Abschirmvorrichtung
KR100817070B1 (ko) * 2006-10-30 2008-03-26 삼성전자주식회사 다중 그라운드 쉴딩 반도체 패키지, 그 패키지의 제조방법 및 그 그라운드 쉴딩을 이용한 노이즈 방지방법
TWI337399B (en) * 2007-01-26 2011-02-11 Advanced Semiconductor Eng Semiconductor package for electromagnetic shielding
DE602007009375D1 (de) 2007-07-27 2010-11-04 Fujitsu Semiconductor Ltd Rauscharme Flip-Chip-Verpackungen und Flip-Chips dafür
JP2009147150A (ja) * 2007-12-14 2009-07-02 Nec Electronics Corp 半導体装置
US8169059B2 (en) 2008-09-30 2012-05-01 Infineon Technologies Ag On-chip RF shields with through substrate conductors
JP5189032B2 (ja) * 2009-06-16 2013-04-24 新光電気工業株式会社 半導体装置および多層配線基板
CN102104033A (zh) * 2009-12-18 2011-06-22 中国科学院微电子研究所 三维混合信号芯片堆叠封装体及其制备方法
JP2011146519A (ja) 2010-01-14 2011-07-28 Panasonic Corp 半導体装置及びその製造方法
KR101719636B1 (ko) * 2011-01-28 2017-04-05 삼성전자 주식회사 반도체 장치 및 그 제조 방법
US8835226B2 (en) 2011-02-25 2014-09-16 Rf Micro Devices, Inc. Connection using conductive vias

Also Published As

Publication number Publication date
CN104704630A (zh) 2015-06-10
JP2016500198A (ja) 2016-01-07
EP2901478B1 (en) 2018-10-10
EP2901478A2 (en) 2015-08-05
WO2014051894A2 (en) 2014-04-03
WO2014051894A3 (en) 2014-09-18
US20140084477A1 (en) 2014-03-27
KR102132046B1 (ko) 2020-07-08
CN104704630B (zh) 2017-03-29
US9054096B2 (en) 2015-06-09
KR20150058201A (ko) 2015-05-28

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