DE602007009375D1 - Rauscharme Flip-Chip-Verpackungen und Flip-Chips dafür - Google Patents

Rauscharme Flip-Chip-Verpackungen und Flip-Chips dafür

Info

Publication number
DE602007009375D1
DE602007009375D1 DE200760009375 DE602007009375T DE602007009375D1 DE 602007009375 D1 DE602007009375 D1 DE 602007009375D1 DE 200760009375 DE200760009375 DE 200760009375 DE 602007009375 T DE602007009375 T DE 602007009375T DE 602007009375 D1 DE602007009375 D1 DE 602007009375D1
Authority
DE
Germany
Prior art keywords
flip
low
noise
chip packaging
chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE200760009375
Other languages
English (en)
Inventor
Ian Juso Dedic
Ghazanfer Ali
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Semiconductor Ltd filed Critical Fujitsu Semiconductor Ltd
Publication of DE602007009375D1 publication Critical patent/DE602007009375D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
DE200760009375 2007-07-27 2007-07-27 Rauscharme Flip-Chip-Verpackungen und Flip-Chips dafür Active DE602007009375D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP20070113378 EP2019427B1 (de) 2007-07-27 2007-07-27 Rauscharme Flip-Chip-Verpackungen und Flip-Chips dafür

Publications (1)

Publication Number Publication Date
DE602007009375D1 true DE602007009375D1 (de) 2010-11-04

Family

ID=38668979

Family Applications (1)

Application Number Title Priority Date Filing Date
DE200760009375 Active DE602007009375D1 (de) 2007-07-27 2007-07-27 Rauscharme Flip-Chip-Verpackungen und Flip-Chips dafür

Country Status (4)

Country Link
US (6) US8178979B2 (de)
EP (1) EP2019427B1 (de)
JP (1) JP5428233B2 (de)
DE (1) DE602007009375D1 (de)

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EP2019486B1 (de) 2007-07-27 2014-12-10 Fujitsu Semiconductor Limited HF-Sender
EP2019427B1 (de) * 2007-07-27 2010-09-22 Fujitsu Semiconductor Limited Rauscharme Flip-Chip-Verpackungen und Flip-Chips dafür
US8555230B2 (en) * 2008-09-19 2013-10-08 The Boeing Company Isolation method and package using a high isolation differential ball grid array (BGA) pattern
JP2011151367A (ja) * 2009-12-25 2011-08-04 Sony Corp 回路基板積層モジュール及び電子機器
US9070700B2 (en) * 2011-11-04 2015-06-30 Broadcom Corporation Apparatus for electrostatic discharge protection and noise suppression in circuits
US9054096B2 (en) * 2012-09-25 2015-06-09 Xilinx, Inc. Noise attenuation wall
EP2849543B1 (de) 2013-09-12 2021-02-24 Socionext Inc. Bauelemente und Schaltungen zum Abschluss von Ausgängen
EP2849344B1 (de) 2013-09-12 2019-11-06 Socionext Inc. Schaltungen und Verfahren zur Verwendung in Schaltungen mit gemischten Signalen
US9054722B2 (en) 2013-09-12 2015-06-09 Fujitsu Semiconductor Limited Circuitry and methods for use in mixed-signal circuitry
EP2849021B1 (de) 2013-09-12 2020-01-01 Socionext Inc. Signalausrichtungsschaltungen und Verfahren
US8976050B1 (en) 2013-09-12 2015-03-10 Fujitsu Semiconductor Limited Circuitry and methods for use in mixed-signal circuitry
EP3062189B1 (de) 2013-09-12 2020-06-24 Socionext Inc. Schaltungen, die zur takterzeugung und verteilung verwendbar sind
EP2849346B1 (de) 2013-09-12 2019-08-21 Socionext Inc. Schaltungen für gemischte Signalen
US9201813B2 (en) 2013-09-12 2015-12-01 Socionext Inc. Signal distribution circuitry
EP2849345B1 (de) 2013-09-12 2020-11-04 Socionext Inc. Schaltungen und Verfahren zur Verwendung in Schaltungen mit gemischten Signalen
JP6274917B2 (ja) * 2014-03-11 2018-02-07 三菱電機株式会社 高周波パッケージ
EP3430646B1 (de) * 2016-03-16 2021-11-10 INTEL Corporation Stairstep-zwischenstücke mit integrierter abschirmung für elektronikgehäuse
CN111048492B (zh) * 2019-12-30 2021-10-15 中国电子科技集团公司第十三研究所 一种限幅低噪声放大器芯片结构
US20220310497A1 (en) 2021-03-25 2022-09-29 Dialog Semiconductor (Uk) Limited Partially Staggered Ball Array for Reduced Noise Injection

Family Cites Families (13)

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Publication number Priority date Publication date Assignee Title
KR0150206B1 (ko) 1989-02-21 1998-12-15 오가 노리오 디지탈/아날로그 변환기
JP3743131B2 (ja) * 1997-08-06 2006-02-08 ソニー株式会社 送受信機用集積回路
US6294407B1 (en) * 1998-05-06 2001-09-25 Virtual Integration, Inc. Microelectronic packages including thin film decal and dielectric adhesive layer having conductive vias therein, and methods of fabricating the same
US6239485B1 (en) * 1998-11-13 2001-05-29 Fujitsu Limited Reduced cross-talk noise high density signal interposer with power and ground wrap
US6121827A (en) 1999-04-15 2000-09-19 Lucent Technologies, Inc. Digital noise reduction in integrated circuits and circuit assemblies
US6775150B1 (en) * 2000-08-30 2004-08-10 Intel Corporation Electronic assembly comprising ceramic/organic hybrid substrate with embedded capacitors and methods of manufacture
TW511414B (en) * 2001-04-19 2002-11-21 Via Tech Inc Data processing system and method, and control chip, and printed circuit board thereof
JP2004179255A (ja) * 2002-11-25 2004-06-24 Sony Corp 半導体集積回路
US6936502B2 (en) * 2003-05-14 2005-08-30 Nortel Networks Limited Package modification for channel-routed circuit boards
JP2005150248A (ja) * 2003-11-12 2005-06-09 Matsushita Electric Ind Co Ltd 半導体集積回路装置
JP2005167276A (ja) * 2005-01-26 2005-06-23 Matsushita Electric Ind Co Ltd 半導体集積回路
JP2006261543A (ja) * 2005-03-18 2006-09-28 Fuji Xerox Co Ltd 半導体装置実装パッケージ及び中継プリント配線基板
EP2019427B1 (de) * 2007-07-27 2010-09-22 Fujitsu Semiconductor Limited Rauscharme Flip-Chip-Verpackungen und Flip-Chips dafür

Also Published As

Publication number Publication date
US20120187579A1 (en) 2012-07-26
EP2019427A1 (de) 2009-01-28
US20120326335A1 (en) 2012-12-27
US9490227B2 (en) 2016-11-08
US20120106094A1 (en) 2012-05-03
US8334600B2 (en) 2012-12-18
JP5428233B2 (ja) 2014-02-26
US8637999B2 (en) 2014-01-28
US20140124930A1 (en) 2014-05-08
US20090057920A1 (en) 2009-03-05
US20160043052A1 (en) 2016-02-11
US8648475B2 (en) 2014-02-11
US8178979B2 (en) 2012-05-15
EP2019427B1 (de) 2010-09-22
JP2009033175A (ja) 2009-02-12
US9136238B2 (en) 2015-09-15

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