JP6039107B2 - インテリジェントな電流／電力消費最小化を伴う、向上した動的メモリ管理 - Google Patents

インテリジェントな電流／電力消費最小化を伴う、向上した動的メモリ管理 Download PDF

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JP6039107B2
JP6039107B2 JP2015551844A JP2015551844A JP6039107B2 JP 6039107 B2 JP6039107 B2 JP 6039107B2 JP 2015551844 A JP2015551844 A JP 2015551844A JP 2015551844 A JP2015551844 A JP 2015551844A JP 6039107 B2 JP6039107 B2 JP 6039107B2
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volatile memory
power
memory devices
power consumption
state
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Japanese (ja)
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JP2016507826A (ja
JP2016507826A5 (enExample
Inventor
パク、ヘ・ジュン
ホフマン、リチャード・ジェラルド
リ、ヨン・ジュ
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Qualcomm Inc
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Qualcomm Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3215—Monitoring of peripheral devices
    • G06F1/3225—Monitoring of peripheral devices of memory devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Power Sources (AREA)
  • Dram (AREA)
JP2015551844A 2013-01-08 2014-01-07 インテリジェントな電流／電力消費最小化を伴う、向上した動的メモリ管理 Active JP6039107B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/736,268 2013-01-08
US13/736,268 US9760149B2 (en) 2013-01-08 2013-01-08 Enhanced dynamic memory management with intelligent current/power consumption minimization
PCT/US2014/010546 WO2014110051A1 (en) 2013-01-08 2014-01-07 Enhanced dynamic memory management with intelligent current/power consumption minimization

Publications (3)

Publication Number Publication Date
JP2016507826A JP2016507826A (ja) 2016-03-10
JP2016507826A5 JP2016507826A5 (enExample) 2016-10-27
JP6039107B2 true JP6039107B2 (ja) 2016-12-07

Family

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JP2015551844A Active JP6039107B2 (ja) 2013-01-08 2014-01-07 インテリジェントな電流／電力消費最小化を伴う、向上した動的メモリ管理

Country Status (8)

Country Link
US (2) US9760149B2 (enExample)
EP (1) EP2943848B1 (enExample)
JP (1) JP6039107B2 (enExample)
KR (1) KR101718462B1 (enExample)
CN (1) CN104903815B (enExample)
ES (1) ES2602287T3 (enExample)
HU (1) HUE028997T2 (enExample)
WO (1) WO2014110051A1 (enExample)

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US10877693B2 (en) * 2018-06-29 2020-12-29 Intel Corporation Architecture for dynamic transformation of memory configuration
US11243596B2 (en) 2019-08-26 2022-02-08 Micron Technology, Inc. Architecture-based power management for a memory device
US12045113B2 (en) * 2019-08-26 2024-07-23 Micron Technology, Inc. Bank configurable power modes
US11579876B2 (en) * 2020-08-05 2023-02-14 Advanced Micro Devices, Inc. Reducing save restore latency for power control based on write signals
US11720261B2 (en) * 2020-08-10 2023-08-08 Micron Technology, Inc. Transferring memory system data to a host system
US11868266B2 (en) * 2021-03-11 2024-01-09 Micron Technology, Inc. Bank redistribution based on power consumption
US11721406B2 (en) * 2021-08-06 2023-08-08 Micron Technology, Inc. Generating test data for a memory system design based on operation of a test system, and related methods, devices, and systems
US20230214270A1 (en) * 2021-12-31 2023-07-06 Western Digital Technologies, Inc. Readiness states for partitioned internal resources of a memory controller

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Also Published As

Publication number Publication date
KR20150104602A (ko) 2015-09-15
US20170329385A1 (en) 2017-11-16
US10429915B2 (en) 2019-10-01
US20140195837A1 (en) 2014-07-10
WO2014110051A1 (en) 2014-07-17
EP2943848A1 (en) 2015-11-18
HUE028997T2 (en) 2017-01-30
US9760149B2 (en) 2017-09-12
EP2943848B1 (en) 2016-09-07
JP2016507826A (ja) 2016-03-10
ES2602287T3 (es) 2017-02-20
CN104903815B (zh) 2017-09-12
KR101718462B1 (ko) 2017-03-21
CN104903815A (zh) 2015-09-09

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