CN104903815B - 具有智能电流/功耗最小化的增强型动态存储器管理 - Google Patents

具有智能电流/功耗最小化的增强型动态存储器管理 Download PDF

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Publication number
CN104903815B
CN104903815B CN201480004109.0A CN201480004109A CN104903815B CN 104903815 B CN104903815 B CN 104903815B CN 201480004109 A CN201480004109 A CN 201480004109A CN 104903815 B CN104903815 B CN 104903815B
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Prior art keywords
volatile memory
memory devices
power
consumption
low power
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Chinese (zh)
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CN104903815A (zh
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H·J·朴
R·G·霍夫曼
Y·J·李
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Qualcomm Inc
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Qualcomm Inc
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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3215Monitoring of peripheral devices
    • G06F1/3225Monitoring of peripheral devices of memory devices
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234Power saving characterised by the action undertaken
    • G06F1/3287Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Power Sources (AREA)
  • Dram (AREA)
CN201480004109.0A 2013-01-08 2014-01-07 具有智能电流/功耗最小化的增强型动态存储器管理 Active CN104903815B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/736,268 2013-01-08
US13/736,268 US9760149B2 (en) 2013-01-08 2013-01-08 Enhanced dynamic memory management with intelligent current/power consumption minimization
PCT/US2014/010546 WO2014110051A1 (en) 2013-01-08 2014-01-07 Enhanced dynamic memory management with intelligent current/power consumption minimization

Publications (2)

Publication Number Publication Date
CN104903815A CN104903815A (zh) 2015-09-09
CN104903815B true CN104903815B (zh) 2017-09-12

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CN201480004109.0A Active CN104903815B (zh) 2013-01-08 2014-01-07 具有智能电流/功耗最小化的增强型动态存储器管理

Country Status (8)

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US (2) US9760149B2 (enExample)
EP (1) EP2943848B1 (enExample)
JP (1) JP6039107B2 (enExample)
KR (1) KR101718462B1 (enExample)
CN (1) CN104903815B (enExample)
ES (1) ES2602287T3 (enExample)
HU (1) HUE028997T2 (enExample)
WO (1) WO2014110051A1 (enExample)

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US10877693B2 (en) * 2018-06-29 2020-12-29 Intel Corporation Architecture for dynamic transformation of memory configuration
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US11243596B2 (en) 2019-08-26 2022-02-08 Micron Technology, Inc. Architecture-based power management for a memory device
US11579876B2 (en) * 2020-08-05 2023-02-14 Advanced Micro Devices, Inc. Reducing save restore latency for power control based on write signals
US11720261B2 (en) * 2020-08-10 2023-08-08 Micron Technology, Inc. Transferring memory system data to a host system
US11868266B2 (en) * 2021-03-11 2024-01-09 Micron Technology, Inc. Bank redistribution based on power consumption
US11721406B2 (en) * 2021-08-06 2023-08-08 Micron Technology, Inc. Generating test data for a memory system design based on operation of a test system, and related methods, devices, and systems
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Also Published As

Publication number Publication date
WO2014110051A1 (en) 2014-07-17
HUE028997T2 (en) 2017-01-30
ES2602287T3 (es) 2017-02-20
US9760149B2 (en) 2017-09-12
KR20150104602A (ko) 2015-09-15
EP2943848B1 (en) 2016-09-07
EP2943848A1 (en) 2015-11-18
US10429915B2 (en) 2019-10-01
CN104903815A (zh) 2015-09-09
US20140195837A1 (en) 2014-07-10
JP2016507826A (ja) 2016-03-10
KR101718462B1 (ko) 2017-03-21
JP6039107B2 (ja) 2016-12-07
US20170329385A1 (en) 2017-11-16

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