JP6031765B2 - 半導体装置、電子機器、及び、半導体装置の製造方法 - Google Patents

半導体装置、電子機器、及び、半導体装置の製造方法 Download PDF

Info

Publication number
JP6031765B2
JP6031765B2 JP2012006356A JP2012006356A JP6031765B2 JP 6031765 B2 JP6031765 B2 JP 6031765B2 JP 2012006356 A JP2012006356 A JP 2012006356A JP 2012006356 A JP2012006356 A JP 2012006356A JP 6031765 B2 JP6031765 B2 JP 6031765B2
Authority
JP
Japan
Prior art keywords
film
semiconductor
interface
bonding
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2012006356A
Other languages
English (en)
Japanese (ja)
Other versions
JP2013033900A (ja
JP2013033900A5 (https=
Inventor
恵永 香川
恵永 香川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP2012006356A priority Critical patent/JP6031765B2/ja
Priority to TW101121190A priority patent/TWI495041B/zh
Priority to US13/533,526 priority patent/US8896125B2/en
Priority to KR1020120069684A priority patent/KR102030852B1/ko
Priority to CN201210233277.XA priority patent/CN102867847B/zh
Publication of JP2013033900A publication Critical patent/JP2013033900A/ja
Priority to US14/467,852 priority patent/US9111763B2/en
Publication of JP2013033900A5 publication Critical patent/JP2013033900A5/ja
Priority to US14/718,942 priority patent/US9443802B2/en
Priority to US15/228,894 priority patent/US9911778B2/en
Priority to US15/228,860 priority patent/US10038024B2/en
Application granted granted Critical
Publication of JP6031765B2 publication Critical patent/JP6031765B2/ja
Priority to US15/992,908 priority patent/US10431621B2/en
Priority to US16/410,877 priority patent/US10985102B2/en
Priority to KR1020190069266A priority patent/KR20190071647A/ko
Priority to KR1020200069977A priority patent/KR102298787B1/ko
Priority to US17/194,641 priority patent/US11569123B2/en
Priority to KR1020210112763A priority patent/KR102439964B1/ko
Priority to KR1020220109225A priority patent/KR102673911B1/ko
Priority to KR1020240073260A priority patent/KR102934233B1/ko
Priority to KR1020260036365A priority patent/KR20260036502A/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/934—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/701—Direct bonding of chips, wafers or substrates characterised by the pads after the direct bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/701—Direct bonding of chips, wafers or substrates characterised by the pads after the direct bonding
    • H10W80/732—Direct bonding of chips, wafers or substrates characterised by the pads after the direct bonding having shape changed during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/701—Direct bonding of chips, wafers or substrates characterised by the pads after the direct bonding
    • H10W80/754—Direct bonding of chips, wafers or substrates characterised by the pads after the direct bonding having material changed during the connecting

Landscapes

  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2012006356A 2011-07-05 2012-01-16 半導体装置、電子機器、及び、半導体装置の製造方法 Active JP6031765B2 (ja)

Priority Applications (18)

Application Number Priority Date Filing Date Title
JP2012006356A JP6031765B2 (ja) 2011-07-05 2012-01-16 半導体装置、電子機器、及び、半導体装置の製造方法
TW101121190A TWI495041B (zh) 2011-07-05 2012-06-13 半導體裝置、用於半導體裝置之製造方法及電子設備
US13/533,526 US8896125B2 (en) 2011-07-05 2012-06-26 Semiconductor device, fabrication method for a semiconductor device and electronic apparatus
KR1020120069684A KR102030852B1 (ko) 2011-07-05 2012-06-28 반도체 장치, 반도체 장치의 제조 방법 및 전자 기기
CN201210233277.XA CN102867847B (zh) 2011-07-05 2012-07-05 半导体器件、半导体器件制造方法及电子装置
US14/467,852 US9111763B2 (en) 2011-07-05 2014-08-25 Semiconductor device, fabrication method for a semiconductor device and electronic apparatus
US14/718,942 US9443802B2 (en) 2011-07-05 2015-05-21 Semiconductor device, fabrication method for a semiconductor device and electronic apparatus
US15/228,894 US9911778B2 (en) 2011-07-05 2016-08-04 Semiconductor device, fabrication method for a semiconductor device and electronic apparatus
US15/228,860 US10038024B2 (en) 2011-07-05 2016-08-04 Semiconductor device, fabrication method for a semiconductor device and electronic apparatus
US15/992,908 US10431621B2 (en) 2011-07-05 2018-05-30 Semiconductor device, fabrication method for a semiconductor device and electronic apparatus
US16/410,877 US10985102B2 (en) 2011-07-05 2019-05-13 Semiconductor device, fabrication method for a semiconductor device and electronic apparatus
KR1020190069266A KR20190071647A (ko) 2011-07-05 2019-06-12 반도체 장치, 반도체 장치의 제조 방법 및 전자 기기
KR1020200069977A KR102298787B1 (ko) 2011-07-05 2020-06-10 반도체 장치, 반도체 장치의 제조 방법 및 전자 기기
US17/194,641 US11569123B2 (en) 2011-07-05 2021-03-08 Semiconductor device, fabrication method for a semiconductor device and electronic apparatus
KR1020210112763A KR102439964B1 (ko) 2011-07-05 2021-08-26 반도체 장치, 반도체 장치의 제조 방법 및 전자 기기
KR1020220109225A KR102673911B1 (ko) 2011-07-05 2022-08-30 반도체 장치, 반도체 장치의 제조 방법 및 전자 장치
KR1020240073260A KR102934233B1 (ko) 2011-07-05 2024-06-04 반도체 장치, 반도체 장치의 제조 방법 및 전자 장치
KR1020260036365A KR20260036502A (ko) 2011-07-05 2026-02-27 반도체 장치, 반도체 장치의 제조 방법 및 전자 장치

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2011148883 2011-07-05
JP2011148883 2011-07-05
JP2012006356A JP6031765B2 (ja) 2011-07-05 2012-01-16 半導体装置、電子機器、及び、半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2013033900A JP2013033900A (ja) 2013-02-14
JP2013033900A5 JP2013033900A5 (https=) 2015-03-05
JP6031765B2 true JP6031765B2 (ja) 2016-11-24

Family

ID=47789516

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012006356A Active JP6031765B2 (ja) 2011-07-05 2012-01-16 半導体装置、電子機器、及び、半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JP6031765B2 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11355441B2 (en) 2018-03-20 2022-06-07 Kabushiki Kaisha Toshiba Semiconductor device

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014099582A (ja) 2012-10-18 2014-05-29 Sony Corp 固体撮像装置
JP2015079901A (ja) * 2013-10-18 2015-04-23 株式会社東芝 半導体装置及び半導体装置の製造方法
JP6335099B2 (ja) 2014-11-04 2018-05-30 東芝メモリ株式会社 半導体装置および半導体装置の製造方法
US10355039B2 (en) * 2015-05-18 2019-07-16 Sony Corporation Semiconductor device and imaging device
JP2016219660A (ja) 2015-05-22 2016-12-22 ソニー株式会社 半導体装置、製造方法、固体撮像素子、および電子機器
KR102505856B1 (ko) * 2016-06-09 2023-03-03 삼성전자 주식회사 웨이퍼 대 웨이퍼 접합 구조체
US10840205B2 (en) 2017-09-24 2020-11-17 Invensas Bonding Technologies, Inc. Chemical mechanical polishing for hybrid bonding
JP7293323B2 (ja) * 2017-09-29 2023-06-19 キヤノン株式会社 半導体装置および機器
JP2019110260A (ja) * 2017-12-20 2019-07-04 ソニーセミコンダクタソリューションズ株式会社 固体撮像装置、及びその製造方法
JP2019160866A (ja) * 2018-03-08 2019-09-19 ソニーセミコンダクタソリューションズ株式会社 撮像装置
JP7046678B2 (ja) * 2018-03-30 2022-04-04 キヤノン株式会社 半導体装置、機器
US11056348B2 (en) 2018-04-05 2021-07-06 Invensas Bonding Technologies, Inc. Bonding surfaces for microelectronics
US11393779B2 (en) 2018-06-13 2022-07-19 Invensas Bonding Technologies, Inc. Large metal pads over TSV
US11749645B2 (en) 2018-06-13 2023-09-05 Adeia Semiconductor Bonding Technologies Inc. TSV as pad
US11011494B2 (en) 2018-08-31 2021-05-18 Invensas Bonding Technologies, Inc. Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
WO2020071103A1 (ja) * 2018-10-05 2020-04-09 ソニーセミコンダクタソリューションズ株式会社 半導体装置およびその製造方法、撮像素子
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
JP2020096225A (ja) * 2018-12-10 2020-06-18 ソニーセミコンダクタソリューションズ株式会社 撮像装置及び電子機器
WO2021163823A1 (en) 2020-02-17 2021-08-26 Yangtze Memory Technologies Co., Ltd. Hybrid wafer bonding method and structure thereof
US11264357B1 (en) 2020-10-20 2022-03-01 Invensas Corporation Mixed exposure for large die
JP2022082187A (ja) * 2020-11-20 2022-06-01 ソニーセミコンダクタソリューションズ株式会社 固体撮像装置及びその製造方法、並びに電子機器
JP7652560B2 (ja) * 2020-12-16 2025-03-27 キオクシア株式会社 半導体記憶装置、半導体装置およびその製造方法
WO2022147429A1 (en) 2020-12-28 2022-07-07 Invensas Bonding Technologies, Inc. Structures with through-substrate vias and methods for forming the same
CN116762163A (zh) 2020-12-28 2023-09-15 美商艾德亚半导体接合科技有限公司 具有贯穿衬底过孔的结构及其形成方法
JP7652586B2 (ja) * 2021-02-25 2025-03-27 キオクシア株式会社 半導体装置およびその製造方法
DE112022004086T5 (de) * 2021-08-24 2024-05-29 Sony Semiconductor Solutions Corporation Lichtdetektionsvorrichtung und elektronische einrichtung
JP2023177154A (ja) * 2022-06-01 2023-12-13 キオクシア株式会社 半導体装置およびその製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7396732B2 (en) * 2004-12-17 2008-07-08 Interuniversitair Microelektronica Centrum Vzw (Imec) Formation of deep trench airgaps and related applications
JP5585447B2 (ja) * 2008-07-31 2014-09-10 日本電気株式会社 半導体装置及びその製造方法
JP2010129693A (ja) * 2008-11-26 2010-06-10 Fujitsu Microelectronics Ltd 半導体装置及びその製造方法
JP5304536B2 (ja) * 2009-08-24 2013-10-02 ソニー株式会社 半導体装置
JP5407660B2 (ja) * 2009-08-26 2014-02-05 ソニー株式会社 半導体装置の製造方法
JP2011054637A (ja) * 2009-08-31 2011-03-17 Sony Corp 半導体装置およびその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11355441B2 (en) 2018-03-20 2022-06-07 Kabushiki Kaisha Toshiba Semiconductor device

Also Published As

Publication number Publication date
JP2013033900A (ja) 2013-02-14

Similar Documents

Publication Publication Date Title
JP6031765B2 (ja) 半導体装置、電子機器、及び、半導体装置の製造方法
KR102439964B1 (ko) 반도체 장치, 반도체 장치의 제조 방법 및 전자 기기
US11569123B2 (en) Semiconductor device, fabrication method for a semiconductor device and electronic apparatus
US8664763B2 (en) Semiconductor apparatus, electronic device, and method of manufacturing semiconductor apparatus
CN108110023B (zh) 半导体器件和电子器件
JP5696513B2 (ja) 固体撮像装置とその製造方法、及び電子機器
JP5994274B2 (ja) 半導体装置、半導体装置の製造方法、及び、電子機器
TWI497696B (zh) 半導體器件，其製造方法及電子裝置
KR20200011414A (ko) 촬상 장치 및 전자 기기
JP2020053701A (ja) 半導体デバイスの製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20150109

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20150109

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20150908

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20150910

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20151028

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20160419

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20160615

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20160927

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20161010

R151 Written notification of patent or utility model registration

Ref document number: 6031765

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250