JP6016952B2 - エラーコード化スキームと変調スキームを組合せるための装置及び方法 - Google Patents
エラーコード化スキームと変調スキームを組合せるための装置及び方法 Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1072—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in multilevel memories
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
- H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
- H03M13/256—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with trellis coding, e.g. with convolutional codes and TCM
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/63—Joint error correction and other techniques
- H03M13/6325—Error control coding in combination with demodulation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/63—Joint error correction and other techniques
- H03M13/6331—Error control coding in combination with equalisation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
- H04L1/0047—Decoding adapted to other signal detection operation
- H04L1/005—Iterative decoding, including iteration between signal detection and decoding operation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0059—Convolutional codes
- H04L1/006—Trellis-coded modulation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0064—Concatenated codes
- H04L1/0065—Serial concatenated codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
- H03M13/4138—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors soft-output Viterbi algorithm based decoding, i.e. Viterbi decoding with weighted decisions
- H03M13/4146—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors soft-output Viterbi algorithm based decoding, i.e. Viterbi decoding with weighted decisions soft-output Viterbi decoding according to Battail and Hagenauer in which the soft-output is determined using path metric differences along the maximum-likelihood path, i.e. "SOVA" decoding
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- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Quality & Reliability (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Error Detection And Correction (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Description
Claims (8)
- メモリを動作させる方法であって、
線形エラー訂正コードを使用してデータを符号化すること、
前記符号化されたデータに関してトレリスコード化変調(TCM)を実施し前記符号化されたデータを変調すること、
前記変調されたデータをメモリに書込むこと、及び、
ビタビアルゴリズム及び線形エラー訂正コードデコーダの間の反復的なソフトデータの交換を使用して、前記書込まれたデータを復号化すること
を含み、
前記TCMを実施することは、マルチレベルトレリスを生成することを含み、前記マルチレベルトレリスを生成することは、(1/(1xorD))プリコーダオペレーションを使用して前記符号化されたデータをプリコード化すること、及び、前記プリコード化されたエラーコード化データに関して(1+D)オペレーションを実施することを含み、ここで、Dは、1つのユニットの遅延に対応する、
方法。 - データを符号化することは、低密度パリティチェック(LDPC)コードを使用してデータをエラーコード化することを含む、請求項1に記載の方法。
- 変調スキームを実施することは、前記符号化されたデータの信号セットを拡張することを含む、請求項1又は2に記載の方法。
- 前記符号化されたデータを変調することは、前記符号化されたデータに関連する2つの最も近いマルチレベルシーケンス間の2乗ユークリッド距離を増加させることを含み、
前記マルチレベルデータ内の2つの最も近いマルチレベルシーケンス間の2乗ユークリッド距離は、前記符号化されたバイナリデータに関連する2つの最も近いマルチレベルシーケンス間の前記2乗ユークリッド距離の約2倍である、
請求項1又は2に記載の方法。 - 装置であって、
メモリと、
前記メモリに結合されたコントローラと、
前記コントローラに結合され、バイナリデータを符号化するように構成されるエラー訂正コードエンコーダと、
前記コントローラに結合され、トレリスコード化変調(TCM)を使用して前記符号化されたバイナリデータの信号セットを拡張することによって前記符号化されたバイナリデータを変調するように構成される変調コンポーネントと、
前記コントローラに結合され、ソフト出力ビダビアルゴリズムによって生成されるハードデータ及びソフトデータを復号化するように構成される線形エラー訂正コードデコーダと、
を備え、
前記コントローラは、
前記変調されたデータを前記メモリに書込むこと、
前記変調されたデータを前記メモリから読出すこと、及び、
ビタビアルゴリズムを使用して前記変調されたデータを復号化すること
を制御するように構成されると共に、前記ビタビアルゴリズムと線形エラー訂正コードデコーダとの間でソフトデータを反復的に交換するように構成されることを含み、
前記TCMを、(1/(1xorD))オペレーションを使用し、その後、(1+D)オペレーションを使用して、前記符号化されたバイナリデータに関して実施する、装置。 - 前記ソフトデータを反復的に交換する反復プロセスは、前記ビダビアルゴリズムから出力されるソフトデータに関連する雑音が所望の閾値レベルに到達されるまで実行される請求項5に記載の装置。
- 前記エラー訂正コードエンコーダは、低密度パリティチェック(LDPC)コードを使用してバイナリデータを符号化するように更に構成される、請求項5に記載の装置。
- 前記ビタビアルゴリズムは、ソフト出力ビタビアルゴリズム(SOVA)を含む、請求項5に記載の装置。
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US13/415,422 | 2012-03-08 | ||
US13/415,422 US8892986B2 (en) | 2012-03-08 | 2012-03-08 | Apparatuses and methods for combining error coding and modulation schemes |
PCT/US2013/028678 WO2013134071A1 (en) | 2012-03-08 | 2013-03-01 | Apparatuses and methods for combining error coding and modulation schemes |
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EP (1) | EP2823399B1 (ja) |
JP (1) | JP6016952B2 (ja) |
KR (1) | KR101645837B1 (ja) |
CN (1) | CN104303155B (ja) |
TW (1) | TWI510000B (ja) |
WO (1) | WO2013134071A1 (ja) |
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EP2823399A4 (en) | 2015-12-09 |
TWI510000B (zh) | 2015-11-21 |
KR101645837B1 (ko) | 2016-08-04 |
US8892986B2 (en) | 2014-11-18 |
CN104303155A (zh) | 2015-01-21 |
US20130238952A1 (en) | 2013-09-12 |
EP2823399B1 (en) | 2017-10-18 |
EP2823399A1 (en) | 2015-01-14 |
TW201342812A (zh) | 2013-10-16 |
KR20140139537A (ko) | 2014-12-05 |
US20150074498A1 (en) | 2015-03-12 |
CN104303155B (zh) | 2018-12-11 |
US9251000B2 (en) | 2016-02-02 |
WO2013134071A1 (en) | 2013-09-12 |
JP2015513866A (ja) | 2015-05-14 |
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