JP5971635B2 - ベクトルユニット共有の装置および方法 - Google Patents
ベクトルユニット共有の装置および方法 Download PDFInfo
- Publication number
- JP5971635B2 JP5971635B2 JP2013550709A JP2013550709A JP5971635B2 JP 5971635 B2 JP5971635 B2 JP 5971635B2 JP 2013550709 A JP2013550709 A JP 2013550709A JP 2013550709 A JP2013550709 A JP 2013550709A JP 5971635 B2 JP5971635 B2 JP 5971635B2
- Authority
- JP
- Japan
- Prior art keywords
- unit
- processor
- vector
- units
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8053—Vector processors
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8053—Vector processors
- G06F15/8076—Details on data register access
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8053—Vector processors
- G06F15/8076—Details on data register access
- G06F15/8084—Special arrangements thereof, e.g. mask or switch
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8053—Vector processors
- G06F15/8092—Array of vector units
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30105—Register structure
- G06F9/30112—Register structure comprising data of variable length
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Mathematical Physics (AREA)
- Image Processing (AREA)
- Advance Control (AREA)
- Complex Calculations (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CA2011/000080 WO2012100316A1 (en) | 2011-01-25 | 2011-01-25 | Apparatus and method of vector unit sharing |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2014509419A JP2014509419A (ja) | 2014-04-17 |
| JP2014509419A5 JP2014509419A5 (https=) | 2015-08-20 |
| JP5971635B2 true JP5971635B2 (ja) | 2016-08-17 |
Family
ID=46580137
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2013550709A Active JP5971635B2 (ja) | 2011-01-25 | 2011-01-25 | ベクトルユニット共有の装置および方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US9727526B2 (https=) |
| JP (1) | JP5971635B2 (https=) |
| CA (1) | CA2859999A1 (https=) |
| DE (1) | DE112011104770B4 (https=) |
| WO (1) | WO2012100316A1 (https=) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9063974B2 (en) * | 2012-10-02 | 2015-06-23 | Oracle International Corporation | Hardware for table scan acceleration |
| JP6102528B2 (ja) * | 2013-06-03 | 2017-03-29 | 富士通株式会社 | 信号処理装置及び信号処理方法 |
| KR102332523B1 (ko) * | 2014-12-24 | 2021-11-29 | 삼성전자주식회사 | 연산 처리 장치 및 방법 |
| CN105335130B (zh) * | 2015-09-28 | 2018-06-26 | 深圳市中兴微电子技术有限公司 | 一种处理器及其处理任务的方法 |
| US10620957B2 (en) | 2015-10-22 | 2020-04-14 | Texas Instruments Incorporated | Method for forming constant extensions in the same execute packet in a VLIW processor |
| US10241946B2 (en) | 2017-01-18 | 2019-03-26 | Nxp Usa, Inc. | Multi-channel DMA system with command queue structure supporting three DMA modes |
| US12189564B2 (en) * | 2022-02-14 | 2025-01-07 | SambaNova Systems, Inc. | Dynamically-sized data structures on data flow architectures |
| US20230418604A1 (en) * | 2022-06-27 | 2023-12-28 | Intel Corporation | Reconfigurable vector processing in a memory |
Family Cites Families (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58134357A (ja) | 1982-02-03 | 1983-08-10 | Hitachi Ltd | ベクトルプロセッサ |
| NL192637C (nl) * | 1984-02-27 | 1997-11-04 | Nippon Telegraph & Telephone | Stelselprocessor. |
| US4771380A (en) * | 1984-06-22 | 1988-09-13 | International Business Machines Corp. | Virtual vector registers for vector processing system |
| US4760525A (en) * | 1986-06-10 | 1988-07-26 | The United States Of America As Represented By The Secretary Of The Air Force | Complex arithmetic vector processor for performing control function, scalar operation, and set-up of vector signal processing instruction |
| US5010477A (en) * | 1986-10-17 | 1991-04-23 | Hitachi, Ltd. | Method and apparatus for transferring vector data between parallel processing system with registers & logic for inter-processor data communication independents of processing operations |
| US5475656A (en) | 1989-09-27 | 1995-12-12 | Hitachi, Ltd. | Optical disk memory and information processing apparatus |
| US5197130A (en) * | 1989-12-29 | 1993-03-23 | Supercomputer Systems Limited Partnership | Cluster architecture for a highly parallel scalar/vector multiprocessor system |
| JPH0520283A (ja) | 1991-07-11 | 1993-01-29 | Mitsubishi Electric Corp | 並列データ処理装置 |
| CA2073516A1 (en) * | 1991-11-27 | 1993-05-28 | Peter Michael Kogge | Dynamic multi-mode parallel processor array architecture computer system |
| JP3639323B2 (ja) * | 1994-03-31 | 2005-04-20 | 富士通株式会社 | メモリ分散型並列計算機による連立1次方程式計算処理方法および計算機 |
| US5513366A (en) * | 1994-09-28 | 1996-04-30 | International Business Machines Corporation | Method and system for dynamically reconfiguring a register file in a vector processor |
| US6317819B1 (en) * | 1996-01-11 | 2001-11-13 | Steven G. Morton | Digital signal processor containing scalar processor and a plurality of vector processors operating from a single instruction |
| JP3344345B2 (ja) | 1998-12-15 | 2002-11-11 | 日本電気株式会社 | 共有メモリ型ベクトル処理システムとその制御方法及びベクトル処理の制御プログラムを格納する記憶媒体 |
| IL145245A0 (en) * | 2001-09-03 | 2002-06-30 | Jtc 2000 Dev Delaware Inc | System and method including vector-matrix multiplication |
| ATE372542T1 (de) * | 2002-05-24 | 2007-09-15 | Nxp Bv | Zugriff zum breiten speicher |
| EP1512100A2 (en) * | 2002-05-24 | 2005-03-09 | Koninklijke Philips Electronics N.V. | A scalar/vector processor |
| US6986023B2 (en) * | 2002-08-09 | 2006-01-10 | Intel Corporation | Conditional execution of coprocessor instruction based on main processor arithmetic flags |
| US7334110B1 (en) * | 2003-08-18 | 2008-02-19 | Cray Inc. | Decoupled scalar/vector computer architecture system and method |
| JP5240424B2 (ja) * | 2004-11-05 | 2013-07-17 | 日本電気株式会社 | Simd型並列演算装置、プロセッシング・エレメント、simd型並列演算装置の制御方式 |
| US20090150648A1 (en) * | 2007-12-06 | 2009-06-11 | Eric Oliver Mejdrich | Vector Permute and Vector Register File Write Mask Instruction Variant State Extension for RISC Length Vector Instructions |
| US8495342B2 (en) | 2008-12-16 | 2013-07-23 | International Business Machines Corporation | Configuring plural cores to perform an instruction having a multi-core characteristic |
-
2011
- 2011-01-25 US US13/981,851 patent/US9727526B2/en active Active
- 2011-01-25 WO PCT/CA2011/000080 patent/WO2012100316A1/en not_active Ceased
- 2011-01-25 JP JP2013550709A patent/JP5971635B2/ja active Active
- 2011-01-25 DE DE112011104770.3T patent/DE112011104770B4/de active Active
- 2011-01-25 CA CA2859999A patent/CA2859999A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| JP2014509419A (ja) | 2014-04-17 |
| US9727526B2 (en) | 2017-08-08 |
| WO2012100316A1 (en) | 2012-08-02 |
| DE112011104770T5 (de) | 2013-10-31 |
| US20140006748A1 (en) | 2014-01-02 |
| DE112011104770B4 (de) | 2022-08-25 |
| CA2859999A1 (en) | 2012-08-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5971635B2 (ja) | ベクトルユニット共有の装置および方法 | |
| US11995027B2 (en) | Neural processing accelerator | |
| US12554502B2 (en) | Method for performing random read access to a block of data using parallel LUT read instruction in vector processors | |
| US6366998B1 (en) | Reconfigurable functional units for implementing a hybrid VLIW-SIMD programming model | |
| KR19990077230A (ko) | 이미지-처리 프로세서 | |
| CN109711539B (zh) | 运算方法、装置及相关产品 | |
| JP4624098B2 (ja) | プロセッサのアドレス発生ユニット | |
| WO2015073646A1 (en) | Vector processing engine employing reordering circuitry in data flow paths between vector data memory and execution units, and related method | |
| JPH0850575A (ja) | プログラマブルプロセッサ、前記プログラマブルプロセッサを用いてデジタル信号処理を行なうための方法およびその改良 | |
| EP3069237A1 (en) | Vector processing engines employing a tapped-delay line for filter vector processing operations, and related vector processor systems and methods | |
| GB2458554A (en) | Coalescing memory accesses from multiple threads in a parallel processing system | |
| TWI803634B (zh) | 子向量數值之加載及複製之處理器、操作一處理器之方法、處理設備及包含指令的非暫時性電腦可讀媒體 | |
| US11341210B2 (en) | Two-dimensional multi-layer convolution for deep learning | |
| JP2020508512A (ja) | データ処理装置における乗累算 | |
| US10908916B2 (en) | Apparatus and method for executing a plurality of threads | |
| JP7245833B2 (ja) | 構成可能なハードウェアの実行時の最適化 | |
| CN108319559B (zh) | 用于控制矢量内存存取的数据处理装置及方法 | |
| US8060726B2 (en) | SIMD microprocessor, image processing apparatus including same, and image processing method used therein | |
| US20230059970A1 (en) | Weight sparsity in data processing engines | |
| EP4195062A1 (en) | Method and apparatus for separable convolution filter operations on matrix multiplication arrays | |
| US20060069897A1 (en) | Information processing device and information processing method | |
| US20150254076A1 (en) | Data processing apparatus and method for performing vector scan operation | |
| CN115390924B (zh) | 指令执行方法、执行引擎、处理器、芯片及电子设备 | |
| US20130138928A1 (en) | Vliw processor, instruction structure, and instruction execution method | |
| CN121209829B (zh) | 用于执行矩阵乘法的方法、计算装置、介质和程序产品 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140124 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20140124 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20141217 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20150106 |
|
| A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20150404 |
|
| A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20150507 |
|
| A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20150606 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20150703 |
|
| A524 | Written submission of copy of amendment under article 19 pct |
Free format text: JAPANESE INTERMEDIATE CODE: A524 Effective date: 20150703 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20160202 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20160502 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20160607 |
|
| A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20160623 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20160704 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20160623 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 5971635 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |