DE112011104770B4 - Apparat und Verfahren zum gemeinsamen Vektoreinheit Benutzen - Google Patents

Apparat und Verfahren zum gemeinsamen Vektoreinheit Benutzen Download PDF

Info

Publication number
DE112011104770B4
DE112011104770B4 DE112011104770.3T DE112011104770T DE112011104770B4 DE 112011104770 B4 DE112011104770 B4 DE 112011104770B4 DE 112011104770 T DE112011104770 T DE 112011104770T DE 112011104770 B4 DE112011104770 B4 DE 112011104770B4
Authority
DE
Germany
Prior art keywords
vector
unit
processor
units
reconfigurable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE112011104770.3T
Other languages
German (de)
English (en)
Other versions
DE112011104770T5 (de
Inventor
Malcom Stewart
Ali Osman Ors
Daniel Laroche
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP Canada Inc
Original Assignee
Nxp Canada Inc
NXP Canada Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Canada Inc, NXP Canada Inc filed Critical Nxp Canada Inc
Publication of DE112011104770T5 publication Critical patent/DE112011104770T5/de
Application granted granted Critical
Publication of DE112011104770B4 publication Critical patent/DE112011104770B4/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • G06F15/8076—Details on data register access
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • G06F15/8076—Details on data register access
    • G06F15/8084—Special arrangements thereof, e.g. mask or switch
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • G06F15/8092—Array of vector units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30112—Register structure comprising data of variable length
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Image Processing (AREA)
  • Advance Control (AREA)
  • Complex Calculations (AREA)
DE112011104770.3T 2011-01-25 2011-01-25 Apparat und Verfahren zum gemeinsamen Vektoreinheit Benutzen Active DE112011104770B4 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CA2011/000080 WO2012100316A1 (en) 2011-01-25 2011-01-25 Apparatus and method of vector unit sharing

Publications (2)

Publication Number Publication Date
DE112011104770T5 DE112011104770T5 (de) 2013-10-31
DE112011104770B4 true DE112011104770B4 (de) 2022-08-25

Family

ID=46580137

Family Applications (1)

Application Number Title Priority Date Filing Date
DE112011104770.3T Active DE112011104770B4 (de) 2011-01-25 2011-01-25 Apparat und Verfahren zum gemeinsamen Vektoreinheit Benutzen

Country Status (5)

Country Link
US (1) US9727526B2 (https=)
JP (1) JP5971635B2 (https=)
CA (1) CA2859999A1 (https=)
DE (1) DE112011104770B4 (https=)
WO (1) WO2012100316A1 (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9063974B2 (en) * 2012-10-02 2015-06-23 Oracle International Corporation Hardware for table scan acceleration
JP6102528B2 (ja) * 2013-06-03 2017-03-29 富士通株式会社 信号処理装置及び信号処理方法
KR102332523B1 (ko) * 2014-12-24 2021-11-29 삼성전자주식회사 연산 처리 장치 및 방법
CN105335130B (zh) * 2015-09-28 2018-06-26 深圳市中兴微电子技术有限公司 一种处理器及其处理任务的方法
US10620957B2 (en) 2015-10-22 2020-04-14 Texas Instruments Incorporated Method for forming constant extensions in the same execute packet in a VLIW processor
US10241946B2 (en) 2017-01-18 2019-03-26 Nxp Usa, Inc. Multi-channel DMA system with command queue structure supporting three DMA modes
US12189564B2 (en) * 2022-02-14 2025-01-07 SambaNova Systems, Inc. Dynamically-sized data structures on data flow architectures
US20230418604A1 (en) * 2022-06-27 2023-12-28 Intel Corporation Reconfigurable vector processing in a memory

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58134357A (ja) 1982-02-03 1983-08-10 Hitachi Ltd ベクトルプロセッサ
NL192637C (nl) * 1984-02-27 1997-11-04 Nippon Telegraph & Telephone Stelselprocessor.
US4771380A (en) * 1984-06-22 1988-09-13 International Business Machines Corp. Virtual vector registers for vector processing system
US4760525A (en) * 1986-06-10 1988-07-26 The United States Of America As Represented By The Secretary Of The Air Force Complex arithmetic vector processor for performing control function, scalar operation, and set-up of vector signal processing instruction
US5010477A (en) * 1986-10-17 1991-04-23 Hitachi, Ltd. Method and apparatus for transferring vector data between parallel processing system with registers & logic for inter-processor data communication independents of processing operations
US5475656A (en) 1989-09-27 1995-12-12 Hitachi, Ltd. Optical disk memory and information processing apparatus
US5197130A (en) * 1989-12-29 1993-03-23 Supercomputer Systems Limited Partnership Cluster architecture for a highly parallel scalar/vector multiprocessor system
JPH0520283A (ja) 1991-07-11 1993-01-29 Mitsubishi Electric Corp 並列データ処理装置
CA2073516A1 (en) * 1991-11-27 1993-05-28 Peter Michael Kogge Dynamic multi-mode parallel processor array architecture computer system
JP3639323B2 (ja) * 1994-03-31 2005-04-20 富士通株式会社 メモリ分散型並列計算機による連立１次方程式計算処理方法および計算機
US5513366A (en) * 1994-09-28 1996-04-30 International Business Machines Corporation Method and system for dynamically reconfiguring a register file in a vector processor
US6317819B1 (en) * 1996-01-11 2001-11-13 Steven G. Morton Digital signal processor containing scalar processor and a plurality of vector processors operating from a single instruction
JP3344345B2 (ja) 1998-12-15 2002-11-11 日本電気株式会社 共有メモリ型ベクトル処理システムとその制御方法及びベクトル処理の制御プログラムを格納する記憶媒体
IL145245A0 (en) * 2001-09-03 2002-06-30 Jtc 2000 Dev Delaware Inc System and method including vector-matrix multiplication
ATE372542T1 (de) * 2002-05-24 2007-09-15 Nxp Bv Zugriff zum breiten speicher
EP1512100A2 (en) * 2002-05-24 2005-03-09 Koninklijke Philips Electronics N.V. A scalar/vector processor
US6986023B2 (en) * 2002-08-09 2006-01-10 Intel Corporation Conditional execution of coprocessor instruction based on main processor arithmetic flags
US7334110B1 (en) * 2003-08-18 2008-02-19 Cray Inc. Decoupled scalar/vector computer architecture system and method
JP5240424B2 (ja) * 2004-11-05 2013-07-17 日本電気株式会社 Ｓｉｍｄ型並列演算装置、プロセッシング・エレメント、ｓｉｍｄ型並列演算装置の制御方式
US20090150648A1 (en) * 2007-12-06 2009-06-11 Eric Oliver Mejdrich Vector Permute and Vector Register File Write Mask Instruction Variant State Extension for RISC Length Vector Instructions
US8495342B2 (en) 2008-12-16 2013-07-23 International Business Machines Corporation Configuring plural cores to perform an instruction having a multi-core characteristic

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
Nutt, G. J.: Microprocessor implementation of a parallel processor, Report CU-CS-091-76, Department of Computer Science, University of Colorado, 1976. URL: http://www.cs.colorado.edu/department/publications/reports/docs/CU-CS-091-76.pdf [abgerufen am 04.08.2016]
Schwederski, T.; Meyer, D. G.; Siegel, H. J.: Computer Architecture: Concepts and Systems. New York, NY : Elsevier Science Ltd, 1987. S. 178-184, 191-193, 196-198, 204-207, 214-224. Kapitel 5: Parallel Processing. - ISBN 044401019X. http://www.engr.colostate.edu/~hj/book_chapters/11.pdf [abgerufen am 04.08.2016]
Siegel, H. J. [u.a.]: An Overview of the PASM Parallel Processing System. In: Computer Architecture, 1987, S. 387-407. http://www.engr.colostate.edu/~hj/book_chapters/9.pdf [abgerufen am 04.08.2016]

Also Published As

Publication number Publication date
JP2014509419A (ja) 2014-04-17
US9727526B2 (en) 2017-08-08
WO2012100316A1 (en) 2012-08-02
DE112011104770T5 (de) 2013-10-31
US20140006748A1 (en) 2014-01-02
JP5971635B2 (ja) 2016-08-17
CA2859999A1 (en) 2012-08-02

Similar Documents

Publication Publication Date Title
DE112011104770B4 (de) Apparat und Verfahren zum gemeinsamen Vektoreinheit Benutzen
DE19914210B4 (de) Verfahren und Prozessor für eine gestaffelte Ausführung einer Anweisung
EP0875031B1 (de) Prozessor zur bildverarbeitung
DE69625256T2 (de) Mikrorechner
DE102017113733B4 (de) Faltendes neuronales Netzwerk auf programmierbarem zweidimensionalem Bildprozessor
DE69709078T2 (de) Verwaltungssystem zur datenverarbeitung
DE3851858T2 (de) Digitaler Signalprozessor.
DE69919059T2 (de) Datenverarbeitungssytem mit einem digitalen Signalprozessor und einem Koprozessor und Datenverarbeitungsverfahren
DE68927371T2 (de) Verfahren und Vorrichtung zur Verarbeitung von mehreren Zustandscodes wie für einen Parallel-Pipeline-Rechner
DE112013006309T5 (de) Funktionseinheit mit Baumstruktur zur Unterstützung eines Vektorsortieralgorithmus und anderer Algorithmen
DE112015005597T5 (de) Verknüpfungsfähige Parallelausführungs-Schicht einer Ausgabewarteschlange für einen Prozessor
DE3933171A1 (de) Einzelchip-prozessor fuer komplexe gleitkommazahlen
DE602004006516T2 (de) Parallel-verarbeitungs-array
DE112019002981T5 (de) Parallelberechnungsarchitektur mit rekonfigurierbarer kernebenen- und vektorebenen-parallelität
DE102020131925A1 (de) Gleitkomma-zerlegungsschaltungsanordnung dynamischergenauigkeit
DE112015004983T5 (de) Parallel-Slice-Prozessor mit einer Lade-Speicher-Umlaufwarteschlange für eine schnelle Freigabe von Einträgen in einer Ausgabewarteschlange
DE10297000T5 (de) Verfahren und Vorrichtung zur parallelen Datenverschiebung nach rechts mit Datenzusammenfügung
DE102017113735B4 (de) Statistische Operationen auf einem zweidimensionalen Bildprozessor
DE102018006744A1 (de) Bitmatrixmultiplikation
DE112020005055T5 (de) Prozessoreinheit für multiplizier- und akkumulieroperationen
DE3485771T2 (de) Leistungsfaehiger paralleler vektorprozessor.
DE102021122785A1 (de) Flexibler beschleuniger für eine tensor-arbeitslast
DE4430195B4 (de) Verfahren zur Auswertung von Booleschen Ausdrücken
DE102015109969A1 (de) Replizieren von Logikblöcken zum Ermöglichen eines erhöhten Durchsatzes
DE102014002510A1 (de) Präzise Ausnahmesignalisierung für Mehrfachdatenarchitektur

Legal Events

Date Code Title Description
R012 Request for examination validly filed
R016 Response to examination communication
R081 Change of applicant/patentee

Owner name: NXP CANADA INC., CA

Free format text: FORMER OWNER: COGNIVUE CORP., GATINEAU, QUEBEC, CA

R082 Change of representative

Representative=s name: DILG, HAEUSLER, SCHINDELMANN PATENTANWALTSGESE, DE

Representative=s name: DILG HAEUSLER SCHINDELMANN PATENTANWALTSGESELL, DE

R018 Grant decision by examination section/examining division
R020 Patent grant now final