JP5947397B2 - 競合のないメモリ構成 - Google Patents

競合のないメモリ構成 Download PDF

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Publication number
JP5947397B2
JP5947397B2 JP2014545893A JP2014545893A JP5947397B2 JP 5947397 B2 JP5947397 B2 JP 5947397B2 JP 2014545893 A JP2014545893 A JP 2014545893A JP 2014545893 A JP2014545893 A JP 2014545893A JP 5947397 B2 JP5947397 B2 JP 5947397B2
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JP
Japan
Prior art keywords
memory
access
memory blocks
blocks
ports
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Active
Application number
JP2014545893A
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English (en)
Japanese (ja)
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JP2015506025A (ja
Inventor
ウー，エフレム・シィ
サハリア，ギャネシュ
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Xilinx Inc
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Xilinx Inc
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Publication of JP2015506025A publication Critical patent/JP2015506025A/ja
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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/023—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Static Random-Access Memory (AREA)
  • Information Transfer Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Dram (AREA)
JP2014545893A 2011-12-07 2012-09-28 競合のないメモリ構成 Active JP5947397B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/314,079 2011-12-07
US13/314,079 US8611175B2 (en) 2011-12-07 2011-12-07 Contention-free memory arrangement
PCT/US2012/058039 WO2013085606A2 (en) 2011-12-07 2012-09-28 Contention-free memory arrangement

Publications (2)

Publication Number Publication Date
JP2015506025A JP2015506025A (ja) 2015-02-26
JP5947397B2 true JP5947397B2 (ja) 2016-07-06

Family

ID=47172872

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014545893A Active JP5947397B2 (ja) 2011-12-07 2012-09-28 競合のないメモリ構成

Country Status (7)

Country Link
US (1) US8611175B2 (cg-RX-API-DMAC7.html)
EP (1) EP2788983B1 (cg-RX-API-DMAC7.html)
JP (1) JP5947397B2 (cg-RX-API-DMAC7.html)
KR (1) KR101816970B1 (cg-RX-API-DMAC7.html)
CN (1) CN104106115B (cg-RX-API-DMAC7.html)
IN (1) IN2014CN04171A (cg-RX-API-DMAC7.html)
WO (1) WO2013085606A2 (cg-RX-API-DMAC7.html)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8947931B1 (en) * 2014-06-13 2015-02-03 Sandisk Technologies Inc. Memory module
US9864710B2 (en) * 2015-03-30 2018-01-09 EMC IP Holding Company LLC Writing data to storage via a PCI express fabric having a fully-connected mesh topology
JP2018032141A (ja) * 2016-08-23 2018-03-01 東芝メモリ株式会社 半導体装置
US10141938B2 (en) * 2016-09-21 2018-11-27 Xilinx, Inc. Stacked columnar integrated circuits
US10635331B2 (en) * 2017-07-05 2020-04-28 Western Digital Technologies, Inc. Distribution of logical-to-physical address entries across bank groups
US10346093B1 (en) * 2018-03-16 2019-07-09 Xilinx, Inc. Memory arrangement for tensor data
KR20210065195A (ko) * 2018-10-23 2021-06-03 에트론 테크놀로지 아메리카 아이엔씨. 버스 및 시스템 내부에서 사용하기 위한 슈퍼스칼라 메모리 ic
JP7563082B2 (ja) * 2020-09-29 2024-10-08 富士フイルムビジネスイノベーション株式会社 プログラマブル論理回路、情報処理装置、情報処理システム、及びプログラム

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62145172A (ja) * 1985-12-20 1987-06-29 Fujitsu Ltd 試験回路付入出力パツフア
JP2546901B2 (ja) * 1989-12-05 1996-10-23 株式会社日立製作所 通信制御装置
JPH0668022A (ja) * 1992-08-18 1994-03-11 Oki Electric Ind Co Ltd ダイレクトメモリアクセス装置
GB9618137D0 (en) * 1996-08-30 1996-10-09 Sgs Thomson Microelectronics Improvements in or relating to an ATM switch
JP2000209172A (ja) * 1999-01-14 2000-07-28 Matsushita Electric Ind Co Ltd 多重化装置及び多重化システム
KR100546331B1 (ko) * 2003-06-03 2006-01-26 삼성전자주식회사 스택 뱅크들 마다 독립적으로 동작하는 멀티 포트 메모리장치
DE102004038211A1 (de) * 2004-08-05 2006-03-16 Robert Bosch Gmbh Botschaftsverwalter und Verfahren zur Steuerung des Zugriffs auf Daten eines Botschaftsspeichers eines Kommunikationsbausteins
KR100655081B1 (ko) 2005-12-22 2006-12-08 삼성전자주식회사 가변적 액세스 경로를 가지는 멀티 포트 반도체 메모리장치 및 그에 따른 방법
US8861300B2 (en) * 2009-06-30 2014-10-14 Infinera Corporation Non-blocking multi-port memory formed from smaller multi-port memories
US8547774B2 (en) * 2010-01-29 2013-10-01 Mosys, Inc. Hierarchical multi-bank multi-port memory organization

Also Published As

Publication number Publication date
CN104106115A (zh) 2014-10-15
WO2013085606A3 (en) 2014-08-14
KR101816970B1 (ko) 2018-01-09
IN2014CN04171A (cg-RX-API-DMAC7.html) 2015-07-17
JP2015506025A (ja) 2015-02-26
EP2788983A2 (en) 2014-10-15
KR20140102718A (ko) 2014-08-22
US20130148450A1 (en) 2013-06-13
EP2788983B1 (en) 2016-04-06
US8611175B2 (en) 2013-12-17
WO2013085606A2 (en) 2013-06-13
CN104106115B (zh) 2017-03-22

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