IN2014CN04171A - - Google Patents
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- Publication number
- IN2014CN04171A IN2014CN04171A IN4171CHN2014A IN2014CN04171A IN 2014CN04171 A IN2014CN04171 A IN 2014CN04171A IN 4171CHN2014 A IN4171CHN2014 A IN 4171CHN2014A IN 2014CN04171 A IN2014CN04171 A IN 2014CN04171A
- Authority
- IN
- India
- Prior art keywords
- access
- group
- memory blocks
- ports
- port
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/023—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Static Random-Access Memory (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Dram (AREA)
- Information Transfer Systems (AREA)
Abstract
A memory arrangement (200) includes a plurality of memory blocks (208) a first group of access ports (204) and a second group of access ports (206). Routing circuitry (209) couples each pair of the first and second groups of access ports to a respective one of the memory blocks. Each pair includes a first access port from the first group and a second access port from the second group. The first access port has write access to a first portion of the respective memory blocks but not to a second portion of the memory block and has read access to the second portion but not to the first portion. The second access port has write access to the second portion but not to the first portion and has read access to the first portion but not to the second portion.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/314,079 US8611175B2 (en) | 2011-12-07 | 2011-12-07 | Contention-free memory arrangement |
PCT/US2012/058039 WO2013085606A2 (en) | 2011-12-07 | 2012-09-28 | Contention-free memory arrangement |
Publications (1)
Publication Number | Publication Date |
---|---|
IN2014CN04171A true IN2014CN04171A (en) | 2015-07-17 |
Family
ID=47172872
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IN4171CHN2014 IN2014CN04171A (en) | 2011-12-07 | 2012-09-28 |
Country Status (7)
Country | Link |
---|---|
US (1) | US8611175B2 (en) |
EP (1) | EP2788983B1 (en) |
JP (1) | JP5947397B2 (en) |
KR (1) | KR101816970B1 (en) |
CN (1) | CN104106115B (en) |
IN (1) | IN2014CN04171A (en) |
WO (1) | WO2013085606A2 (en) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8947931B1 (en) * | 2014-06-13 | 2015-02-03 | Sandisk Technologies Inc. | Memory module |
US9864710B2 (en) * | 2015-03-30 | 2018-01-09 | EMC IP Holding Company LLC | Writing data to storage via a PCI express fabric having a fully-connected mesh topology |
JP2018032141A (en) * | 2016-08-23 | 2018-03-01 | 東芝メモリ株式会社 | Semiconductor device |
US10141938B2 (en) | 2016-09-21 | 2018-11-27 | Xilinx, Inc. | Stacked columnar integrated circuits |
US10635331B2 (en) * | 2017-07-05 | 2020-04-28 | Western Digital Technologies, Inc. | Distribution of logical-to-physical address entries across bank groups |
US10346093B1 (en) * | 2018-03-16 | 2019-07-09 | Xilinx, Inc. | Memory arrangement for tensor data |
JP2022509348A (en) * | 2018-10-23 | 2022-01-20 | エトロン・テクノロジー・アメリカ・インコーポレイテッド | Buses and systems used in superscalar memory ICs and superscalar memory ICs |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62145172A (en) * | 1985-12-20 | 1987-06-29 | Fujitsu Ltd | Input/output buffer provided with testing circuit |
JP2546901B2 (en) * | 1989-12-05 | 1996-10-23 | 株式会社日立製作所 | Communication control device |
JPH0668022A (en) * | 1992-08-18 | 1994-03-11 | Oki Electric Ind Co Ltd | Direct memory access device |
GB9618137D0 (en) * | 1996-08-30 | 1996-10-09 | Sgs Thomson Microelectronics | Improvements in or relating to an ATM switch |
JP2000209172A (en) * | 1999-01-14 | 2000-07-28 | Matsushita Electric Ind Co Ltd | Multiplexer and multiplexing system |
KR100546331B1 (en) * | 2003-06-03 | 2006-01-26 | 삼성전자주식회사 | Multi-Port memory device with stacked banks |
DE102004038211A1 (en) * | 2004-08-05 | 2006-03-16 | Robert Bosch Gmbh | Message manager and method for controlling the access to data of a message memory of a communication module |
KR100655081B1 (en) | 2005-12-22 | 2006-12-08 | 삼성전자주식회사 | Multi-port semiconductor memory device having variable access path and method therefore |
US8861300B2 (en) * | 2009-06-30 | 2014-10-14 | Infinera Corporation | Non-blocking multi-port memory formed from smaller multi-port memories |
US8547774B2 (en) * | 2010-01-29 | 2013-10-01 | Mosys, Inc. | Hierarchical multi-bank multi-port memory organization |
-
2011
- 2011-12-07 US US13/314,079 patent/US8611175B2/en active Active
-
2012
- 2012-09-28 KR KR1020147017494A patent/KR101816970B1/en active IP Right Grant
- 2012-09-28 CN CN201280069104.7A patent/CN104106115B/en active Active
- 2012-09-28 IN IN4171CHN2014 patent/IN2014CN04171A/en unknown
- 2012-09-28 JP JP2014545893A patent/JP5947397B2/en active Active
- 2012-09-28 EP EP12784372.0A patent/EP2788983B1/en active Active
- 2012-09-28 WO PCT/US2012/058039 patent/WO2013085606A2/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
JP2015506025A (en) | 2015-02-26 |
EP2788983A2 (en) | 2014-10-15 |
WO2013085606A2 (en) | 2013-06-13 |
US8611175B2 (en) | 2013-12-17 |
KR20140102718A (en) | 2014-08-22 |
US20130148450A1 (en) | 2013-06-13 |
CN104106115B (en) | 2017-03-22 |
EP2788983B1 (en) | 2016-04-06 |
KR101816970B1 (en) | 2018-01-09 |
JP5947397B2 (en) | 2016-07-06 |
CN104106115A (en) | 2014-10-15 |
WO2013085606A3 (en) | 2014-08-14 |
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