JP5925440B2 - Ｓｏｉ基板の作製方法及び半導体装置の作製方法 - Google Patents

Ｓｏｉ基板の作製方法及び半導体装置の作製方法 Download PDF

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Publication number
JP5925440B2
JP5925440B2 JP2011157815A JP2011157815A JP5925440B2 JP 5925440 B2 JP5925440 B2 JP 5925440B2 JP 2011157815 A JP2011157815 A JP 2011157815A JP 2011157815 A JP2011157815 A JP 2011157815A JP 5925440 B2 JP5925440 B2 JP 5925440B2
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Prior art keywords
single crystal
crystal semiconductor
semiconductor layer
substrate
etching
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JP2011157815A
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Japanese (ja)
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JP2012044157A5 (https=
JP2012044157A (ja
Inventor
長谷川　真也
真也 長谷川
磯部　敦生
敦生 磯部
求 倉田
求 倉田
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Publication of JP2012044157A5 publication Critical patent/JP2012044157A5/ja
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

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  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Drying Of Semiconductors (AREA)
JP2011157815A 2010-07-23 2011-07-19 Ｓｏｉ基板の作製方法及び半導体装置の作製方法 Expired - Fee Related JP5925440B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2011157815A JP5925440B2 (ja) 2010-07-23 2011-07-19 Ｓｏｉ基板の作製方法及び半導体装置の作製方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2010165811 2010-07-23
JP2010165811 2010-07-23
JP2011157815A JP5925440B2 (ja) 2010-07-23 2011-07-19 Ｓｏｉ基板の作製方法及び半導体装置の作製方法

Publications (3)

Publication Number Publication Date
JP2012044157A JP2012044157A (ja) 2012-03-01
JP2012044157A5 JP2012044157A5 (https=) 2014-08-21
JP5925440B2 true JP5925440B2 (ja) 2016-05-25

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JP2011157815A Expired - Fee Related JP5925440B2 (ja) 2010-07-23 2011-07-19 Ｓｏｉ基板の作製方法及び半導体装置の作製方法

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US (1) US20120021588A1 (https=)
JP (1) JP5925440B2 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104576387B (zh) * 2013-10-14 2017-07-25 上海和辉光电有限公司 低温多晶硅薄膜晶体管制造方法
JP6117134B2 (ja) * 2014-03-13 2017-04-19 信越化学工業株式会社 複合基板の製造方法
TWI817756B (zh) 2015-09-22 2023-10-01 美商應用材料股份有限公司 清洗方法
CN107742644B (zh) * 2017-10-30 2024-05-28 中山大学 一种高性能常关型的GaN场效应晶体管及其制备方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08153699A (ja) * 1994-09-16 1996-06-11 Semiconductor Energy Lab Co Ltd 薄膜半導体装置の作製方法
JP2004172312A (ja) * 2002-11-19 2004-06-17 Renesas Technology Corp 半導体装置の製造方法
JP5548356B2 (ja) * 2007-11-05 2014-07-16 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP5663150B2 (ja) * 2008-07-22 2015-02-04 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
SG160302A1 (en) * 2008-09-29 2010-04-29 Semiconductor Energy Lab Method for manufacturing semiconductor substrate
US8138093B2 (en) * 2009-08-12 2012-03-20 International Business Machines Corporation Method for forming trenches having different widths and the same depth

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Publication number Publication date
US20120021588A1 (en) 2012-01-26
JP2012044157A (ja) 2012-03-01

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