JP5903973B2 - 電子部品内蔵基板及びその製造方法 - Google Patents
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- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/82009—Pre-treatment of the connector or the bonding area
- H01L2224/8203—Reshaping, e.g. forming vias
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- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Description
2 半導体基板
3,5 半導体チップ
4 再配線層
6 保護膜
8 電子回路
10 第2の端子
11 パッシベーション膜
12,23,27 配線パターン
13,22,25,26 ビア導体
14 絶縁膜
15,15a〜15e 第1の端子
20,21,24 絶縁層
25a,26a ビアホール
30 樹脂基板
31 電子部品内蔵基板
50,52 シリコンウエハ
51 再配線層
60〜62 導体層
60a,61a 開口部
Claims (11)
- 樹脂基板と、
裏面を前記樹脂基板に向けて該樹脂基板の表面に載置された半導体装置と、
前記半導体装置を覆う絶縁層と、
前記絶縁層の内部に埋め込まれた少なくとも1つのビア導体と、
それぞれ前記少なくとも1つのビア導体のいずれかと電気的に接続するよう前記絶縁層の表面に形成された少なくとも1つの配線パターンとを備え、
前記半導体装置は、
電子回路と、
主面に露出し、かつそれぞれ前記電子回路と電気的に接続された少なくとも1つの第1の端子とを有し、
前記主面のうち前記少なくとも1つの第1の端子が露出していない非端子領域と前記裏面とがともに粗化されている
ことを特徴とする電子部品内蔵基板。 - 前記半導体装置は、前記非端子領域に露出した保護膜をさらに備え、
前記保護膜の表面が粗化されている
ことを特徴とする請求項1に記載の電子部品内蔵基板。 - 前記半導体装置は、
前記電子回路を内蔵する半導体基板と、
前記半導体基板の主面に形成され、かつそれぞれ前記電子回路の電極を構成する少なくとも1つの第2の端子と、
前記半導体基板の主面に形成され、かつそれぞれ前記少なくとも1つの第2の端子のいずれかと接続する少なくとも1つの配線パターンを含む再配線層とを備え、
前記保護膜は、前記再配線層の表面を覆うように形成される
ことを特徴とする請求項2に記載の電子部品内蔵基板。 - 内部に電子回路が形成され、かつそれぞれ前記電子回路と電気的に接続される少なくとも1つの第1の端子が主面に露出した半導体装置の該主面に第1の粗面加工を施す主面側粗化工程と、
前記半導体装置の裏面を研削することにより該半導体装置を薄型化する薄型化工程と、
前記半導体装置の裏面に第2の粗面加工を施す裏面側粗化工程と、
前記半導体装置を樹脂基板に載置する載置工程と、
前記半導体装置を覆う絶縁層を形成する絶縁層形成工程と、
前記絶縁層の内部に、それぞれ前記半導体装置の前記少なくとも1つの第1の端子のいずれかと電気的に接続される少なくとも1つのビア導体を形成するビア導体形成工程と、
前記絶縁層の表面に、それぞれ前記少なくとも1つのビア導体のいずれかと電気的に接続される少なくとも1つの配線パターンを形成する配線パターン形成工程と
を備えることを特徴とする電子部品内蔵基板の製造方法。 - 内部に電子回路が形成され、かつそれぞれ前記電子回路と電気的に接続される少なくとも1つの第1の端子が主面に露出した半導体装置の裏面を研削することにより、該半導体装置を薄型化する薄型化工程と、
前記半導体装置の裏面に第2の粗面加工を施す裏面側粗化工程と、
前記裏面側粗化工程を経た前記半導体装置を樹脂基板の主面に載置する載置工程と、
前記半導体装置を載置した後の前記樹脂基板の前記主面に第1の粗面加工を施す主面側粗化工程と、
前記主面側粗化工程の後、前記半導体装置を覆う絶縁層を形成する工程と、
前記絶縁層の内部に、それぞれ前記少なくとも1つの第1の端子のいずれかと電気的に接続される少なくとも1つのビア導体を形成する工程と、
前記絶縁層の表面に、それぞれ前記少なくとも1つのビア導体のいずれかと電気的に接続される少なくとも1つの配線パターンを形成する工程と
を備えることを特徴とする電子部品内蔵基板の製造方法。 - 前記半導体装置は、前記主面のうち前記少なくとも1つの第1の端子が露出していない領域に露出した保護膜を有し、
前記第1の粗面加工により、少なくとも前記保護膜の表面が粗化される
ことを特徴とする請求項4又は5に記載の電子部品内蔵基板の製造方法。 - 前記第1の粗面加工により前記保護膜の膜厚を減少させる
ことを特徴とする請求項6に記載の電子部品内蔵基板の製造方法。 - 前記第1の粗面加工はウエットブラスト加工である
ことを特徴とする請求項7に記載の電子部品内蔵基板の製造方法。 - 前記複数の第1の端子はそれぞれ金属材料によって構成され、
前記保護膜は樹脂材料によって構成される
ことを特徴とする請求項8に記載の電子部品内蔵基板の製造方法。 - 前記主面側粗化工程、前記薄型化工程、及び前記裏面側粗化工程は、前記半導体装置がウエハ状態であるときに行われ、
前記載置工程の前に、ウエハ状態の前記半導体装置を個片化することにより複数の前記半導体装置を得る個片化工程をさらに備える
ことを特徴とする請求項4乃至9のいずれか一項に記載の電子部品内蔵基板の製造方法。 - 内部に形成された電子回路、それぞれ前記電子回路と電気的に接続され、かつ主面に露出した少なくとも1つの第1の端子、及び該主面のうち前記少なくとも1つの第1の端子が露出していない領域に露出した保護膜を有する半導体装置の該主面に、前記保護膜の膜厚を減少させる膜厚低減加工を施す膜厚低減工程と、
前記半導体装置の裏面を研削することにより該半導体装置を薄型化する薄型化工程と、
前記半導体装置を樹脂基板に載置する載置工程と、
前記半導体装置を覆う絶縁層を形成する絶縁層形成工程と、
前記絶縁層の内部に、それぞれ前記半導体装置の前記少なくとも1つの第1の端子のいずれかと電気的に接続される少なくとも1つのビア導体を形成するビア導体形成工程と、
前記絶縁層の表面に、それぞれ前記少なくとも1つのビア導体のいずれかと電気的に接続される少なくとも1つの配線パターンを形成する配線パターン形成工程と
を備えることを特徴とする電子部品内蔵基板の製造方法。
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