JP5894047B2 - 電子部品収納用パッケージ - Google Patents
電子部品収納用パッケージ Download PDFInfo
- Publication number
- JP5894047B2 JP5894047B2 JP2012208369A JP2012208369A JP5894047B2 JP 5894047 B2 JP5894047 B2 JP 5894047B2 JP 2012208369 A JP2012208369 A JP 2012208369A JP 2012208369 A JP2012208369 A JP 2012208369A JP 5894047 B2 JP5894047 B2 JP 5894047B2
- Authority
- JP
- Japan
- Prior art keywords
- frame
- electronic component
- shaped
- recess
- bonding material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/183—Connection portion, e.g. seal
- H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
Landscapes
- Solid State Image Pick-Up Elements (AREA)
Description
枠状部の内側面にかけて広がったとしても、その接合材が凹部内に溜まる。そのため、接合材が枠状部の上面にまで広がることは抑制される。そして、枠状部の内側面の表面粗さが、前記枠状部の前記凹部内の表面粗さよりも大きいことから、流動性を有する状態の接合材が枠状部の内側面に沿って濡れ広がることが効果的に抑制されるとともに、枠状部の内側面から凹部内に接合材が入り込んだときには、接合材が凹部の内側まで容易に広がるので、凹部内において、接合材の溜まりが容易に形成され、枠状部の上面への接合材の広がりがより効果的に抑制され得る。したがって、電子部品を搭載部に接合する接合材が枠状部の上面まで広がることが効果的に抑制された電子部品収納用パッケージを提供することができる。
よび有機溶剤とともにシート状に成形した複数のセラミックグリーンシートを積層した後に焼成することによって製作されている。この場合、複数のセラミックグリーンシートの一部を、打ち抜き加工等の方法で枠状に成形して、枠状部2となる枠状のセラミックグリーンシートを作製する。枠状のセラミックグリーンシートを平板状のセラミックグリーンシートの上面に積層すれば、上面に凹状の収納部を有する絶縁基板を製作することができる。
続パッド3とを含む電子部品収納用パッケージ10に実装される。電子部品5は、例えば上記のように封止用枠状部4の上面に蓋体7が接合されることによって気密封止される。これにより、電子部品5が気密封止されてなる電子装置が形成される。
とする。
示すような溝状のものであるとき、凹部2aの高さは、0.1〜0.4mm程度に設定すればよい。
ッケージの生産性および経済性等も考慮すれば、5〜10μm程度の表面粗さであることがより望ましい。
1a・・搭載部
2・・・枠状部
2a・・凹部
2b・・補助凹部
3・・・接続パッド
4・・・封止用枠状部
5・・・電子部品
6・・・ボンディングワイヤ
7・・・蓋体
8・・・接続導体
9・・・接合材
10・・・電子部品収納用パッケージ
Claims (3)
- 電子部品の搭載部を含む上面を有する平板部と、
該平板部の上面に、前記搭載部を取り囲むように積層された枠状部と、
該枠状部の上面に設けられた接続パッドとを備えており、
前記枠状部は、その内側面に凹部を有しているとともに、前記枠状部の前記内側面の表面粗さが、前記枠状部の前記凹部内の表面粗さよりも大きいことを特徴とする電子部品収納用パッケージ。 - 前記凹部は、前記枠状部の前記内側面の幅方向に延びる溝状のものであることを特徴とする請求項1記載の電子部品収納用パッケージ。
- 前記枠状部の前記内側面に疎水性材料が付着していることを特徴とする請求項1または請求項2記載の電子部品収納用パッケージ。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012208369A JP5894047B2 (ja) | 2012-06-26 | 2012-09-21 | 電子部品収納用パッケージ |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012143224 | 2012-06-26 | ||
JP2012143224 | 2012-06-26 | ||
JP2012208369A JP5894047B2 (ja) | 2012-06-26 | 2012-09-21 | 電子部品収納用パッケージ |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2014029974A JP2014029974A (ja) | 2014-02-13 |
JP5894047B2 true JP5894047B2 (ja) | 2016-03-23 |
Family
ID=50202350
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012208369A Expired - Fee Related JP5894047B2 (ja) | 2012-06-26 | 2012-09-21 | 電子部品収納用パッケージ |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5894047B2 (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102172630B1 (ko) * | 2015-04-16 | 2020-11-04 | 삼성전기주식회사 | 반도체 소자 패키지 및 그 제조방법 |
WO2017145326A1 (ja) * | 2016-02-25 | 2017-08-31 | 新電元工業株式会社 | ケース、ケースユニット、及びケースユニットの製造方法 |
JP6952396B2 (ja) * | 2018-01-29 | 2021-10-20 | 京セラ株式会社 | 電子部品収納用基板およびこれを用いたパッケージ |
JP7298201B2 (ja) | 2019-03-08 | 2023-06-27 | 三菱マテリアル株式会社 | ヒートシンク付き絶縁回路基板及びパワーモジュール |
CN110767610B (zh) * | 2019-10-15 | 2021-06-25 | 四川豪威尔信息科技有限公司 | 一种集成电路及其制造方法 |
JP7435306B2 (ja) * | 2020-06-25 | 2024-02-21 | Tdk株式会社 | キャビティを有する回路基板及びその製造方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2530002B2 (ja) * | 1988-06-27 | 1996-09-04 | 富士通株式会社 | 半導体装置 |
US4926240A (en) * | 1989-03-28 | 1990-05-15 | Motorola, Inc. | Semiconductor package having recessed die cavity walls |
EP1480264A1 (en) * | 2003-05-21 | 2004-11-24 | Alps Electric Technology Centre (UK) Ltd. | Electrical circuit device |
JP2007173496A (ja) * | 2005-12-22 | 2007-07-05 | Matsushita Electric Ind Co Ltd | 固体撮像素子用パッケージおよび固体撮像装置 |
-
2012
- 2012-09-21 JP JP2012208369A patent/JP5894047B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2014029974A (ja) | 2014-02-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5894047B2 (ja) | 電子部品収納用パッケージ | |
US8658908B2 (en) | Multiple patterning wiring board, wiring board and electronic apparatus | |
WO2014119729A1 (ja) | 電子素子搭載用基板、電子装置および撮像モジュール | |
JP5734434B2 (ja) | 配線基板、電子装置および電子モジュール | |
JP5731404B2 (ja) | 多数個取り配線基板および配線基板ならびに電子装置 | |
JP6760796B2 (ja) | 電子素子実装用基板、電子装置および電子モジュール | |
US11315844B2 (en) | Electronic device mounting board, electronic package, and electronic module | |
US11276617B2 (en) | Electronic device mounting board, electronic package, and electronic module | |
JP6039311B2 (ja) | 配線基板、電子装置および電子モジュール | |
JP2008235864A (ja) | 電子装置 | |
JP5052470B2 (ja) | 多数個取り配線基板および配線基板ならびに電子装置 | |
US10312168B2 (en) | Electronic element mounting substrate, and electronic device | |
JP7163409B2 (ja) | 電子素子実装用基板、および電子装置 | |
JP7210191B2 (ja) | 電子素子実装用基板、電子装置、および電子モジュール | |
JP2011249526A (ja) | 多数個取り配線基板 | |
US10681831B2 (en) | Electronic component mounting board, electronic device, and electronic module | |
US11996339B2 (en) | Electronic element mounting substrate, and electronic device | |
JP7237990B2 (ja) | 電子素子実装用基板、および電子装置 | |
JP2018107181A (ja) | 電子装置および電子モジュール | |
JP7307161B2 (ja) | 電子素子実装用基板、電子装置、および電子モジュール | |
JP2015076584A (ja) | 電子部品収納用パッケージ | |
JP2017022334A (ja) | 多数個取り配線基板及びその製造方法 | |
JP2017079258A (ja) | 電子部品搭載用基板および電子装置 | |
JP6258768B2 (ja) | 配線基板および電子装置 | |
JP2021158322A (ja) | 実装基板、電子装置、および電子モジュール |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20150115 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20150709 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20150806 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20150915 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20160126 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20160225 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5894047 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
LAPS | Cancellation because of no payment of annual fees |